Introduction To Computer Architecture Jean-Michel RICHER University of Angers France...

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Introduction To Computer Architecture Jean-Michel RICHER University of Angers France [email protected] January 2003

Transcript of Introduction To Computer Architecture Jean-Michel RICHER University of Angers France...

Page 1: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

IntroductionTo

Computer Architecture

Jean-Michel RICHER

University of AngersFrance

[email protected]

January 2003

Page 2: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

WARNING !

This document can be reproduced, modified and used freely.

Please report any change or improvement to Jean-Michel Richer at :

[email protected](http://www.info.univ-angers.fr/pub/richer)

January 2003

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OUTLINE

Memory organization

Some CPU organizations

Example of program execution with the Intel 8086

Example of program execution with pipeline technology

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MEMORY ORGANIZATION

The operating system organizes the memory as follows :

contains the program codeCode

contains the program dataData

contains subprograms callsSTACK

contains the rest of the memoryHEAP

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DIFFERENT CPU ORGANIZATIONS

808680486

Pentium IIIPentium IV

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Code

Data

STACK

HEAP

Load Instruction

Decode

Load Operand

Execute

ALU

Registe

rs

Write Result

Intel 8086

Instruction path

Data path

Cpu diemotherboard

Coprocessor

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Code

Data

STACK

HEAP

Load Instruction

Decode

Load Operand

Execute

ALU

Registe

rs

Write Result

Intel 80486

L1 Cache - I

L1 Cache

FPU

Integrated FPUL2

Cach

e

L2 Cache onMotherboard

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Code

Data

STACK

HEAP

L1 Cache - I

Load Instruction

Decode

Load Operand

Execute

FPU

Registe

rs

Write Result

Intel Pentium

BTB TLB

Branch Prediction

ALU1

ALU2

Superscalar

L2 C

ach

e

L1 C

ach

e - D

L1 Cache

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Code

Data

STACK

HEAP

L1 Cache - I

Load Instruction

Decode

Load Operand

Execute

ALU1

ALU2

FPU

BTB TLB

L2 C

ach

e

Registe

rs

L1 C

ach

e - D

Write Result

Intel Pentium III

L2 Cache on-die

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Code

Data

STACK

HEAP

Load Instruction

Decode

Load Operand

Execute

UAL1

UAL2

FPU

BTB TLB

L2 C

ach

e

Registe

rs

L1 C

ach

e - D

Write Result

Intel Pentium IV

Trace Cache

Trace Cache

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PROGRAM EXECUTION

The 8086 case

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int a, b ,c

a = 1;b = 2;c = a + b

C Language

(a) 100 0000000000000001(b) 102 0000000000000010(c) 104 0000000000000000

Program

mov ax, [100]mov bx, [102]add ax, bxmov [104], ax

Assembler 8086

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Micro code

OP Value 1 Value 2 R1 R2

2 bits 2 bits 2 bits16 bits 16 bits

00 mov r1,[adr]01 mov [adr],r111 add r1,r2

00 AX01 BX10 CX11 DX

Instructions are converted into micro-operations that can be handled by the CPU (Central Processing Unit) of the micro-processor

Operation Values Registers

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

RegistersLoad Instruction

Decode

Load Operand

Execute

UAL

Write Result

AX=?BX=?CX=?DX=?

Starting point

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov ax,[100]

Decode

Load Operand

Execute

UAL

Write Result

AX=?BX=?CX=?DX=?

Load Instruction : mov ax,[100]

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov ax,[100]

00 100 ? 00 ?

Load Operand

Execute

UAL

Write Result

AX=?BX=?CX=?DX=?

Decode Instruction : mov ax,[100]

Micro code

00 00100 ??

op val1 val2 r1 r2

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov ax,[100]

00 100 ? 00 ?

00 100 1 00 ?

Execute

UAL

Write Result

AX=?BX=?CX=?DX=?

Load operand : mov ax,[100]

Micro code

00 00100 ?1

op val1 val2 r1 r2

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov ax,[100]

00 100 ? 00 ?

00 100 1 00 ?

Execute

UAL

Write Result

AX=?BX=?CX=?DX=?

Execute : mov ax,[100]

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov ax,[100]

00 100 ? 00 ?

00 100 1 00 ?

Execute

UAL

00 100 1 00 ?

AX=1BX=?CX=?DX=?

Write result : mov ax,[100]

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov bx,[102]

Decode

Load Operand

Execute

UAL

Write Result

AX=1BX=?CX=?DX=?

Load Instruction : mov bx,[102]

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov bx,[102]

00 102 ? 01 ?

Load Operand

Execute

UAL

Write Result

AX=1BX=?CX=?DX=?

Decode Instruction : mov bx,[102]

Micro code

00 01102 ??

op val1 val2 r1 r2

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov bx,[102]

00 102 ? 01 ?

00 102 2 00 ?

Execute

UAL

Write Result

AX=1BX=?CX=?DX=?

Load operand : mov bx,[102]

Micro code

00 01102 ?2

op val1 val2 r1 r2

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov bx,[102]

00 102 ? 01 ?

00 102 2 00 ?

Execute

UAL

Write Result

AX=1BX=?CX=?DX=?

Execute : mov bx,[102]

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov bx,[102]

00 102 ? 01 ?

00 102 2 01 ?

Execute

UAL

00 102 2 01 ?

AX=1BX=2CX=?DX=?

Write result : mov bx,[102]

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersadd ax,bx

Decode

Load Operand

Execute

UAL

Write Result

AX=1BX=2CX=?DX=?

Load Instruction : add ax,bx

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersadd ax,bx

11 ? ? 00 01

Load Operand

Execute

UAL

Write Result

AX=1BX=2CX=?DX=?

Decode Instruction : add ax,bx

Micro code

11 00? 01?

op val1 val2 r1 r2

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersadd ax,bx

11 ? ? 00 01

11 1 2 00 01

Execute

UAL

Write Result

AX=1BX=2CX=?DX=?

Load Operand : add ax,bx

Micro code

11 001 012

op val1 val2 r1 r2

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersadd ax,bx

11 ? ? 00 01

11 1 2 00 01

Execute

1+2 11 3 2 00 01

Write Result

AX=1BX=2CX=?DX=?

Execute : add ax,bx

Micro code

11 003 012

op val1 val2 r1 r2

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersadd ax,bx

11 ? ? 00 01

11 1 2 00 01

Execute

11 3 2 00 01

11 3 2 00 01

AX=3BX=2CX=?DX=?

Write Result : add ax,bx

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov [104],ax

Decode

Load Operand

Execute

UAL

Write Result

AX=3BX=2CX=?DX=?

Load Instruction : mov [104],ax

Page 35: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov [104],ax

01 104 ? 00 ??

Load Operand

Execute

UAL

Write Result

AX=3BX=2CX=?DX=?

Decode Instruction : mov [104],ax

Micro code

01 00104 ??

op val1 val2 r1 r2

Page 36: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov [104],ax

01 104 ? 00 ??

01 104 3 00 ??

Execute

UAL

Write Result

AX=3BX=2CX=?DX=?

Load Operand : mov [104],ax

Micro code

01 00104 ?3

op val1 val2 r1 r2

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mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=0

STACK

HEAP

Registersmov [104],ax

01 104 ? 00 01

01 104 3 00 01

Execute

UAL

Write Result

AX=3BX=2CX=?DX=?

Load Operand : mov [104],ax

Micro code

01 00104 ?3

op val1 val2 r1 r2

Page 38: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

mov ax,[100]mov bx,[102]add ax, bxmov [104],ax

[100]=1[102]=2[104]=3

STACK

HEAP

Registersmov [104],ax

01 104 ? 00 01

01 104 3 00 01

Execute

UAL

01 104 3 00 01

AX=3BX=2CX=?DX=?

Write Result : mov [104],ax

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PROGRAM EXECUTION WITH PIPELINE

Pentium-Like

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DEPENDENCIES

mov ax, [100]

mov bx, [102]

add ax, bx

mov [104], ax

The 8086 code shows there are 2 dependencies :

RAW

WAW

Forward

Forward

Page 41: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

AVOID DEPENDENCIES

To avoid dependencies we can add a field to the micro-code in order to indicate when data need to be forwarded into the pipeline :

OP Value 1 Value 2 R1 R2

2 bits 2 bits 2 bits16 bits 16 bits

Operation Values Registers

F

1 bit

If F = 1 then Forward Data

Flag

Page 42: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

00 00100 ??

op val1 val2 r1 r2

TRADUCTION INTO MICRO-OPs

mov ax, [100]

mov bx, [102]

add ax, bx

mov [104], ax

00 01102 ??

11 00? 01?

01 00104 ??

0

f

1

1

0

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Load Operand

Execute

UAL

Write Result

Load Operand : mov ax,[100]

00 00100 ?? 01

Step 1

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Load Operand

Execute

UAL

Write Result

Load Operand : mov bx,[102]Execute : mov ax,[100]

00 01102 ?? 1

00 00100 ?1 0

2

Step 2

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Load Operand

Execute

UAL

Write Result

Execute : mov bx,[102]

AX=1

Load Operand : add ax,bx

11 00? 01? 1

00 01102 ?2 1

Write Result : mov ax,[100]

00 00100 ?1 0

1

Step 3

Forward result

1

2

Page 46: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

Load Operand

Execute

UAL

Write Result BX=2

Load Operand : mov [104],ax

01 00104 ?? 0

Execute : add ax, bx

11 001 012 1

Write Result : mov bx,[102]

00 01102 ?2 1

1+2

11 00 012 13

Step 4

Forward result

1

3

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Load Operand

Execute

UAL

Write Result AX=3

Execute : mov ax,[104]

01 00104 ?3 0

Write Result : add ax, bx

11 003 012 1

Step 5

Page 48: Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003.

Load Operand

Execute

UAL

Write Result

Write Result : mov ax, [104]

01 00104 ?3 0

RAM

Step 6