Introduction to Circuit Layout
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Transcript of Introduction to Circuit Layout
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Introduction to Circuit Layoutwith Virtuoso and Calibre
Integrated Circuit Application and Design Lab.Chung Yuan Christian University
Prepared by C. Y. Chiou
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Environment SetupLab.1 Ruler
Contact Layers
Lab.2 VIA12_Cell Layout
MOS Layout
Lab 3 NMOS Layout
ScheduleSchedule
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Step 1 mkdir Layout
cd Layout
cp /process/TSMC/018um/PDK-13D/T018MMSP001K1/PDK13D/cds.lib .
cp /process/TSMC/018um/PDK-13D/T018MMSP001K1/PDK13D/display.drf.
cp /process/TSMC/018um/PDK-13D/T018MMSP001K1/PDK13D/techfile .
layout &
Step 2.1 File >> New >> Library
Environment SetupEnvironment Setup
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Step 2.2 Step 2.3
Step 2.4
Environment SetupEnvironment Setup
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Step 3.1
Step 3.2
Environment SetupEnvironment Setup
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Step 3.3
Environment SetupEnvironment Setup
1. 2.
3.
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Step 4.1
Environment SetupEnvironment Setup
Library Name: Exercise
Cell Name: Rule
Tool: Virtuoso
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Step 4.2
(1)Minor Spacing: 0.01
Major Spacing: 5
X Snap Spacing: 0.005
Y Snap Spacing: 0.005
Library
(2)Click Save To
Click OK
Environment SetupEnvironment Setup
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Lab.1Lab.1
k: Ruler
Shift + k: Clear Rulers
Shift + z: Zoom out
Ctrl + z: Zoom in
Lab 1 Ruler
Case 1: (Zoom in)Distance = ? Answer : 0.01Answer : 0.01
Case 2: (Zoom out)Distance = ? Answer : 5Answer : 5
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Outline1. Gate, Source, Drain2. Substrate3. Contact Layers
4. MCO Layout5. Calibre DRC of MCO6. MCP Layout and DRC
Contact LayersContact Layers
VIN1
VIN2
VOUT
VDD
GND
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Gate: POLY Contacted to Metal 1Drain: Oxide Contacted to Metal 1Source: Oxide Contacted to Metal 1
Input/output signal is always feed in/out from Metal Line.
Contact LayersContact Layers
VIN1
VIN2
VOUT
VDD
GND
Gate, Source, Drain
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One chip can only have only one P-Substrate, but itcan have multiple N-Well.
Minimize chip area: Use only 1 N-Well.
Contact LayersContact LayersSubstrate (1)
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Substrate of NMOS: (1) In P-Substrate(2) Diffusion + P-IMP
Substrate of PMOS: (1) In N-Well(2) Diffusion + N-Well
Contact LayersContact LayersSubstrate (2)
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Contact LayersContact LayersSubstrate (3)
Reduce Rs to avoid latch-up.
That is, eliminate the distance from MOS to the nearest substrate contact.
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MCOMCO Metal1Metal1 + ContactContact + OxideOxide (Diffusion)MCPMCP Metal1Metal1 + ContactContact + PolyPoly
VIA12_CellVIA12_Cell Metal2Metal2 + VIA12VIA12 + Metal1Metal1
Contact LayersContact LayersContact Layers
VIN1
VIN2
VOUT
VDD
GND
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Contact LayersContact Layers
Library Name: Exercise
Cell Name: MCO
Tool: Virtuoso
MCO Layout
Step 1
Step 2
Create >> Rectangle (or click r )
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MCO Layout
Step 3
Click CONT in LSW.
Step 4
Draw a rectangle.
( Dont care the size! )
Contact LayersContact Layers
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Contact LayersContact LayersMCO Layout
Step 5
1. Click the rectangle.2. Press q.3. Key in the parameters.4. OK
Design RuleCO.W.1 = 0.22u
Step 6
Check the length with ruler.
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Contact LayersContact Layers
Step 7
1. Click the rectangle.
2. Create3. Layer Generation
Step 8.1
1. CONT2. GROW BY3. 0.1
4. DIFF5. OK
Design RuleCO.E.1 = 0.1u
MCO Layout
Hot Key: f (Fit)
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MCO Layout
Step 8.2
Check the distance with ruler.
Design RuleM1.E.1 = 0.005u
M1.E.2 = 0.06u
Step 9.1
1. Click the rectangle.
2. Create3. Layer Generation4. CONT (Grow by) 0.005 = Metal1
Contact LayersContact Layers
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(Step 9.2)1. Click the rectangle made of Metal1.
2. Press q.3. Top = 0.225 + (0.06-0.005) = 0.284. Bottom = -0.005 - (0.06-0.005) = -0.065. OK
MCO Layout
Contact LayersContact Layers
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Contact LayersContact LayersCalibre DRC of MCO
Step 1
Calibre >> Run DRC
Step 2 Step 3
Calibre-DRC Rules File:/process/TSMC/018um/PDK-13D/T018MMDR001C1/calibre_modified.drc
Calibre-DRC Run Directory: .
C L
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Step 4 Flat Step 5 Run DRC
Contact LayersContact LayersCalibre DRC of MCO
C LC L
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(Step 6)
Calibre DRC of MCO
Contact LayersContact Layers
C LC t t L
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Step 1
MCP Layout and DRC
Step 2
Contact LayersContact Layers
Press and holdthe right keyof the mouse.
C t t LC t t L
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Contact LayersContact LayersMCP Layout and DRC
Step 3
Step 4
Remove of DIFF in MCP
C t t LC t t L
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MCP Layout and DRCContact LayersContact Layers
1. Click the rectangle made of CONT.2. Create
3. Layer Generation
Design RuleCO.E.2 = 0.1u
4. CONT (Grow by) 0.1 POLY15. Calibre >> Run DRC
Step 5
C t t LContact Layers
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MCP Layout and DRCContact LayersContact Layers
Lab 2Lab 2
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Lab.2Lab.2
Mx.E.1 = 0.01umMx.E.2 = 0.06um
VIA.W.1 = 0.26um
Related Design Rules
Lab.2 VIA12_Cell Layout and Verification
VIAx.E.1 = 0.01umVIAx.E.2 = 0.06um
Lab 2Lab 2
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Lab.2Lab.2Lab.2 VIA12_Cell Layout and Verification
MOS LayoutMOS Layout
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Layers: DIFFDIFF, CONTCONT, POLY1POLY1, Metal 1Metal 1, VIA12VIA12, Metal 2Metal 2Rules: Space (Clearance), Overlap, Extension
MOS LayoutMOS Layout
MOS LayoutMOS Layout
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334th MetalM4
Via3 hole between M4 and M3VIA3
3rd MetalM3
Via2 hole between M3 and M2VIA2
2nd MetalM2
Via1 hole between M2 and M1VIA1
1st MetalM1
Contact Window from M1 to ODCO
N+ ImplantationNP
P+ ImplantationPP
Poly-SiliconPO
Thin OxideOD
N-WellNM
MOS LayoutMOS Layout/process/TSMC/018um/PDK-13D/T018MMDR001C1/calibre_modified.drc
MOS LayoutMOS Layout
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/process/TSMC/018um/PDK-13D/T018MMDR001C1/calibre_modified.drc
W: Minimum Width
S: Space( Distance between the same layer)
C: Clearance(Distance between different layer)
O: Overlap E: Extension
MOS LayoutMOS Layout
MOS LayoutMOS Layout
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1. Width: Diff
2. Length: Poly
3. D: Clearance
4.X : ContactNumber of Contact = ?>> Spacing Rule
5. Implant
MOS LayoutMOS Layout
MOS LayoutMOS Layout
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Space of Two MCOs
Related Rule: CO.S.1 = 0.25
Original Space = 0.2
0.25-0.2 = 0.05
Increase the distance by 0.05.
MOS LayoutMOS LayoutSpace: Example of MCO
Height of 1st MCO = 0.42Height of 2nd MCO = 0.42+0.05=0.47
MOS LayoutMOS Layout
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Space of Two VIA12_Cells
Related Rule: VIA1.S.1 = 0.26
Original Space = 0.12
0.26-0.12 = 0.14
Increase the distance by 0.14.
Space: Example of VIA12_Cell
MOS LayoutMOS Layout
Height of 1st VIA12_Cell = 0.38Height of 2nd VIA12_Cell = 0.38+0.14=0.52
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MOS LayoutMOS Layout
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P-Implant
PP.E.1 = 0.18
MOS LayoutMOS Layout
MOS LayoutMOS Layout
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Overlap
MOS LayoutMOS Layout
PO.O.1 = 0.22
MOS LayoutMOS Layout
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MOS LayoutMOS Layout
MOS LayoutMOS Layout
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Clearance
MOS Layouty
OD.C.4= 0.43
MOS LayoutMOS Layout
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Cancel the invoked commandEsc
Remove all marker in the diagramShift + k
Stretchs
Ruler (marker)k
Deleted
Instance invokingi
Copy and call its detailed optionsc, F3
Move and call its detailed optionsm, F3
Hierarchy/Flat ViewCtrl + f Shift + fZoom In/OutCtrl + z Shift + zView total layout diagramf
Common-Used Bind-Key
yy
MOS LayoutMOS Layout
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PMOS Layout Flowyy
Step 1File >> New >> CellviewLibrary Name: Exercise
Cell Name: PMOS_Mp1Tool: Virtuoso
Step 2(1) r(2) DIFF
(3) Draw a Rectangle(4) Select the Rectangle(5) q
W=3.32u, L=0.18u
Step 3
Left: 0Right: 0+0.42*2+0.06*2+0.18= 1.14Bottom: 0Top: 3.32
Step 4
(1) r(2) POLY1(3) Draw a Rectangle(4) Select the Rectangle (POLY1)(5) q
Step 5Left: 0+0.42+0.06= 0.48Right: 0.48+0.18= 0.66Bottom: 0-0.22= (-0.22)Top: 3.32+0.22= 3.54
MOS LayoutMOS Layout
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PMOS Layout Flow
Step 1~5 Step 6
3.32-0.42=2.9
2.9/0.47=6.1702
Number of MCO= 6+1 = 7
Height of MCO= 0.42 + 0.47*6= 3.24
3.32-3.24 = 0.08(even)
0.08/2 = 0.04
yy
MOS LayoutMOS Layout
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Step 7
(1) i >> MCO(2) Rows = 7, Delta Y = 0.47
Column = 2,Delta X = 0.42+0.18+0.06*2
= 0.72(3) Put MCO into the PMOS(4) Shift + f
PMOS Layout Flowyy
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Step 8
(1) Select the Rectangle of DIFF(2) Create >> Layer Generation
(3) DIFF (Grow by) 0.18 = PIMP(4) Apply
(5) DIFF (Grow by) 0.43 = NWELL(6) OK(7) Stretch PIMP to fit PP.C.5
(8) Calibre >> Run DRC
PMOS Layout Flow
Lab.3Lab.3
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W=1u, L=0.18u
NMOS Layout
Design RuleNP.E.1 = 0.18umNP.C.5 = 0.35um
Library Name: ExerciseCell Name: NMOS_Mn1Tool: Virtuoso