Introduction System Control Block Vectored …jesus/hardware_empotrado/LPC2103teo2.pdfLPC2103....

INDEX

• Introduction

• System Control Block

• Vectored Interrupt Controller (VIC)

• GPIO

• UART

• Timers

• SPI

• I2C

• ADC

The LPC2103 microcontroller

ext.int.

GPIO

Legacy

Timers

0,1,2,3

ADC

bridgeAPB

Fast

GPIO

SPI/SSP

0,1

I2C

UART0,1

Pclk

Pin Connect Block

Boot32 kB

FlashSRAM

8 kB

Local Bus

AH

B

AHBbridge

VBat

vectoredinterrupt

controller(VIC)

RTC

(MAM)accel.memory

RTC power domain

ROM

8 kBSystem

functions

Vcc

/reset

fosc

PLLCclk

JTAGdebug

CPU

ARM7TDMI-S

Control

System

AP

B

watchdog

32 I/O pins

32 kHz

LPC2103. Memory map

• Memory mapped I/O

• Bootloader ROM for Flash

programming

• User code can run from Flash

or RAM

vectors (64 bytes)

RAM (8 kB)

APB peripherals

AHB peripherals

0x3F

0xE0000000

0xF0000000

0x7FFFFFFF

0x40000000

0x7FFFE000bootloader (8 kB)

FLASH (32 kB)

0x7FFF

0x0

1G

32k

0

0x40001FFF

2G

3.5G

4G

3.75G

INDEX

• Introduction


- Clock generation - Vector mapping

- Power control - Memory Accelerator


• GPIO

• UART

• Timers

• …

LPC2103. System control block

• Controls several functions of the MCU

– Clock generation (PLL, APB divider)

– Power control (low power modes, peripheral

power control)

– External interrupts

– Other controls (vector mapping,…)

LPC2103 System clock (PLL)

TCM counter

CCOfilter

+PFD

(PLLCFG)

MSEL

(PLLCFG)

PLLE

PLLC(PLLCON)

(PLLCON)

PLLEPSEL

SYNC

fosc

Cclk

mux

mux

1

0

1/16

1/2

1/4

1/8

(PLLSTAT)

PLOCK

0xAA,0x55sequencedetector

wr_PLLFEED Register write

load

init value

1/2 1/2 1/2 1/2

LPC2103 PLL registers

- PSEL MSEL

7 6 5 4 3 2 1 0

-

7 6 5 4 3 2 1 0

- - - - -

PLLE

PLLC

- - PSEL MSEL

7 6 5 4 3 2 1 09 8101112131415

PLLE

PLLCPLOCK

- - - -

7 6 5 4 3 2 1 0

KEY VALUE

PLLCFG(WO)

PLLCON(WO)

PLLSTAT(RO)

PLLFEED(WO)

these conditions must be meet:

f_cco = f_cclk * 2(PSEL+1)

f_cclk = f_osc* (MSEL + 1)

156 MHz < f_cco < 320 MHz

10 MHz < f_osc < 25 MHz

f_cclk < 70 MHz

LPC2103 PLL turn-on procedure

• After Reset or a wakeup interrupt the microcontroller runs on

the crystal oscillator

• To enable the PLL:

1. Set PLLCFG with proper values for MSEL and PSEL

2. Write 0xAA to PLLFEED, write 0x55 to PLLFEED

3. Set PLLCON=0x01 (PLL enable on)


5. Wait until bit 10 in PLLSTAT (PLOCK) becomes 1. If MSEL and PSEL

have reasonable values this step would not take more than 100 µs

6. Set PLLCON=0x03 (PLL enable on, PLL connect on)


APB divider

• The peripheral bus (APB) can run at a lower clock

frequency than the CPU (cclk)

• Register APBDIV selects the APB clock (pclk):

APBDIV[1:0] pclk/cclk

00 1/4 (reset value)

01 1

10 1/2

11 reserved

Low power modes

• 3 operating modes

– Normal all clocks running

– Idle CPU clock stopped, remaining clocks running.

Any interrupt reverts to normal mode without delay.

– Power Down all clocks stopped (except WD and RTC). Only

wakeup interrupts revert to normal mode (with PLL disabled

and after a several millisecond start-up). Microampere current

consumption

• Idle and Power down modes are entered by writing to

register PCON:

– Bit 0: IDL: writing 1 to this bit enters Idle mode

– Bit 1: PD: writing 1 to this bit enters power down mode.

(if PCON[1:0]=11 power down mode is entered)

Low power modes

Found by experimentation:

• Writing ones to PCON doesn’t always put the processor

in low power mode:

– IDLE mode is not entered if there are pending IRQ or FIQ

requests to the core (Even if IRQs are disabled in CPSR).

– Power-Down mode is not entered if there is a pending

INTWAKE interrupt (Even if IRQs are disabled in the VIC or

CPSR). INTWAKE interrupts include EINTx and RTC.

Power control of peripherals

• Many peripherals can be turned off to save power

• After reset all peripherals are powered

• The register PCONP controls which peripheral is

powered (bit at 1 means ON):

Bit Periph. Bit Periph. Bit Periph.

1 TIMER0 7 I2C0 12 ADC

2 TIMER1 8 SPI0 19 I2C1

3 UART0 9 RTC 22 TIMER2

4 UART1 10 SPI1/SSP 23 TIMER3

• Unpowered peripherals does not hold the values

written into their registers

LPC2xxx Vector block mapping

• The first 32 bytes of the address space contains the ARM

vectors for reset, interrupts and exceptions.

• Some space is also usually required for constants

• In the LPC2xxx MCUs the first 64 bytes can be assigned to

different memory areas through the MEMMAP register:

MEMMAP[1:0] Memory Accesses to 0x0 – 0x3F

mapped to

00 Bootloader 0x7FFFE000 – 0x7FFFE03F

01 Flash 0x0 – 0x3F

10 RAM 0x40000000 – 0x4000003F

11 reserved

• After reset the bootloader is always executed. If a valid code

(correct checksum) is found in flash the vectors are mapped

to flash and then a jump to address 0x0 is executed

LPC2xxx Memory Accelerator Module (MAM)

• Flash memory is slow (50 ns access time). It takes 4 cycles per

access for a 70 MHz CCLK

• MAM speeds-up code execution from flash by fetching data

128 bits at a time (4 op-codes)

• Useful for sequential accesses (code execution)

• Registers

– MAMCR MAM control register. Only bits [1:0] used:

00 MAM disabled

01 MAM partially enabled (only sequential reads)

10 MAM fully enabled (like a small cache)

11 Reserved

– MAMTIM bits [2:0]: number of CCLK cycles per flash read.

It should be MAMTIM = f_cclk*50ns (round to upper value. 000 is invalid)

• After reset MAM is disabled and 7 cycles per access are used

INDEX

• Introduction



– VIC

– External interrupts

• GPIO

• UART

• Timers

• …

Vectored interrupt controller (VIC)

• Features

– 32 interrupt inputs

– 16 IRQ vectors

– Default vector for non-vectored IRQs

– Individual mask and software request

– Interrupts can trigger IRQ of FIQ (selectable)

– Priority chain

• Vector #0: highest priority

• …

• Vector #15: lowest priority

VIC diagram

VICINT.i

SOFTINTCLEAR.i INTENABLECLEAR.i

INTSELECT.i

FIQSTATUS

IRQSTATUS

32

32

Interrupt request, masking and selection (x32)

SOFTINT.i INTENABLE.i

(source)

/FIQ

source enableVECTCNTL0

vector interrupt #15

VECTADDR0

LOGIC

PRIORITY

addressselect

32

55

VECTADDR

/IRQ

interrupt priority logic

32

/priority0

/priority1

/priority15

'0'

vector interrupt #1

vector interrupt #0

non-vectored IRQ

DEFAULTVECTADDR

RAWINTERRUPT.i

FIQ

IRQ

VIC registers I

• Control (32-bits, one bit per VIC input, see interrupt mapping):

– VICIntEnable: 1: Enable INT, 0: no action

– VICIntEnClr: 1: Disable INT, 0: no action

– VICIntSelect: 1: request as FIQ, 0: request as IRQ

Interrupt request can be forced by setting bits in the SoftInt register:

– VICSoftInt: 1: Set INT request, 0: no action

– VICSoftIntClr: 1: Clear INT request, 0: no action

(rarely used, may be useful for debugging purposes)

• Status (32-bits, one bit per VIC input , see interrupt mapping):

– VICRawIntr: 1: Interrupt active, 0: no interrupt

– VICIRQStatus: 1: Interrupt request made as IRQ, 0: no request

– VICFIQStatus: 1: Interrupt request made as FIQ, 0: no request

VIC registers II

• Vectors:

– VICDefVectAddr: Holds the ISR address for non-vectored and spurious IRQs

– VICVectAddr0 to VICVectAddr15: Holds the ISR address of the

corresponding vector

– VICVectCntl0 to VICVectCntl15 (vector control):

• Bits [4:0] Input channel selection (See interrupt mapping)

• Bit 5 1: Vector enabled, 0: Vector disabled

• Vector reading:

– VICVectAddr: Holds the address of the ISR for the current IRQ

This register is read automatically by putting the following instruction in the

ARM vector table:

0x18: 0xE51FFFF0 LDR pc, [pc, #-0xFF0] ; IRQ handler

This instruction reads the PC from address 0xFFFFF030 (VICVectAddr register)

– Writing any value to VICVectAddr updates the priority logic of the VIC. This

has to be done at the end of ISRs (End Of Interrupt).

LPC2103. Interrupt mapping

Source VICINT #

WDT 0

TIMER0 4

TIMER1 5

UART0 6

UART1 7

I2C0 9

Source VICINT #

SPI0 10

SPI1/SSP 11

PLL 12

RTC 13

EINT0 14

EINT1 15

Source VICINT #

EINT2 16

ADC 18

I2C1 19

TIMER2 26

TIMER3 27

LPC2103. External interrupts

• Features

– Part of the System Control Block peripheral

– 3 interrupt inputs: EINT0, EINT1, EINT2

– Level or edge sensitive

– Any polarity

– Can awake the microcontroller from power-down

modes

LPC2103 External Interrupt Diagram

Glitchfilter

S

R

QD S

R R

S QQ

PCLK PCLKreset

wr_EXTINT

EINTn

APB BUS: Dn

rd_EXTINT

other wakeup sources

Wakeup timer

VICINTx'1'EXTPOLAR.n

EXTMODE.n

EXTWAKE.n

LPC2103. External Interrupt Registers

• EXTINT (8-bit): External Interrupt flags

– Bits 0,1,2: EINT0, EINT1, EINT2

Read: 1: active interrupt request, 0: no interrupt

Write: 1: Clear interrupt flag 0: no action

(These flags have to be cleared explicitly by the ISR for edge-mode ints.)

• EXTMODE (8-bit): External Interrupt mode

– Bits 0,1,2: EXTMODE0, EXTMODE1, EXTMODE2

0: Level sensitive 1: Edge sensitive

• EXTPOLAR (8-bit): External interrupt polarity

– Bits 0,1,2: EXTPOLAR0, EXTPOLAR1, EXTPOLAR2

0: Low level or falling edge 1: High level or rising edge

• INTWAKE (16-bit): Wakeup interrupts

– Bits 0,1,2: EXTWAKE0, EXTWAKE1, EXTWAKE2

– Bit 15: RTCWAKE

1: The interrupt will awake the processor, 0: no wakeup

INDEX

• Introduction



• GPIO

– Pin Connect Block

– GPIO logic

• UART

• Timers

• …

LPC2103 Pin Connect Block

• PINSELx registers select which peripheral is

connected with each pin

• 2 bits per pin selects 4 possible connections:

0123468901234567890123478901 6 5 7 5111111111122222222233 2

0123468901234567890123478901 6 5 7 5111111111122222222233 2

Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin

Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin

023457891314

171820212731 2225

15

24 23 1926282930

6 1Pin

Pin16

101112

PINSEL0

PINSEL1

• After reset all pins are selected as GPIO

LPC2103

Pin

Connect

Block.

PINSEL0

PIN Bits: 00 01 10 11

P0.0 1:0 GPIO TXD0 MAT3.1 -

P0.1 3:2 GPIO RXD0 MAT3.2 -

P0.2 5:4 GPIO SCL0 CAP0.0 -

P0.3 7:6 GPIO SDA0 MAT0.0 -

P0.4 9:8 GPIO SCK0 CAP0.1 -

P0.5 11:10 GPIO MISO0 MAT0.1 -

P0.6 13:12 GPIO MOSI0 CAP0.2 -

P0.7 15:14 GPIO SSEL0 MAT2.0 -

P0.8 17:16 GPIO TXD1 MAT2.1 -

P0.9 19:18 GPIO RXD1 MAT2.2 -

P0.10 21:20 GPIO RTS1 CAP1.0 AD0.3

P0.11 23:22 GPIO CTS1 CAP1.1 AD0.4

P0.12 25:24 GPIO DSR1 MAT1.0 AD0.5

P0.13 27:26 GPIO - MAT1.1 DTR1

P0.14 29:28 GPIO EINT1 SCK1 DCD1

P0.15 31:30 GPIO EINT2 - RI1

UART0

I2C0

SPI0

SPI1

UART1

A/D

Timers

Ext. INT

LPC2103

Pin

Connect

Block.

PINSEL1

PIN Bits: 00 01 10 11

P0.16 1:0 GPIO EINT0 MAT0.2 -

P0.17 3:2 GPIO SCL1 CAP1.2 -

P0.18 5:4 GPIO SDA1 CAP1.3 -

P0.19 7:6 GPIO MISO1 MAT1.2 -

P0.20 9:8 GPIO MOSI1 MAT1.3 -

P0.21 11:10 GPIO SSEL1 MAT3.0 -

P0.22 13:12 GPIO - - AD0.0

P0.23 15:14 GPIO - - AD0.1

P0.24 17:16 GPIO - - AD0.2

P0.25 19:18 GPIO - - AD0.6

P0.26 21:20 GPIO - - AD0.7

P0.27 23:22 GPIO TRST CAP2.0 -

P0.28 25:24 GPIO TMS CAP2.1 -

P0.29 27:26 GPIO TCK CAP2.2 -

P0.30 29:28 GPIO TDI MAT3.3 -

P0.31 31:30 GPIO TDO - -

I2C1

SPI1

A/D

Timers

Ext. INT

JTAG (debug)

LPC2xxx GPIO

• Fast or legacy GPIO

– Same pins but different timings

– Only one of these two peripherals can be active

• Selectable from System Control Block register:

GPIOM, bit 0: 0: Legacy GPIO 1: Fast GPIO

– Legacy GPIO after reset

• APB bus timings

• Same interface as for older LPC2xxx microcontrollers

• Four 32-bit registers per I/O port:

IOxDIR (rw)

IOxPIN (rw)

IOxSET (rw)

IOxCLR (wo) (replace ‘x’ with port number, for example: IO0DIR)

LPC2xxx. GPIO: pin diagram

LE

D Q

QS

R

wr_IOxDIR

MU

X

10

11

01

rd_IOxDIR

Latch SR

Latch D

bidi

rect

iona

l

uC Pin

Px.i

blockconnect

Pin

alternate

functionsPeripherals

Other

PINSELy

wr_IOxSET

wr_IOxPIN

wr_IOxCLR

Di

(APB)

Perif. Data Bus

00

rd_IOxSET

rd_IOxPIN

LPC2xxx GPIO. Registers

• Registers (32-bit, one bit per pin)

– IOxDIR (rw): Pin direction

0: Input 1: Output

– IOxPIN (rw): Pin Value

Read: The bit reflects the logic level of the pin regardless of its

direction or the function selected in Pin Connect Block

Write: The level of the pin is changed to the written bit

– IOxSET (rw) Pin Set

Write: 1: Set pin (pin=1) 0: no action

Read: The value of the output latch is returned

– IOxCLR (wo) Pin Clear

Write: 1: Clear pin (pin=0) 0: no action

Only pins programmed as GPIO in the Pin Connect Block and as outputs

in IOxDIR are actually changed by writes to IOxPIN, IOxSET and IOxCLR

INDEX

• Introduction



• GPIO

• UART

• Timers

• SPI

• I2C

• ADC

Asynchronous serial communications

• Asynchronous: no clock transmitted

– Requires accurate clocks (relative error less than 3%) in both receiver

and transmitter

• Character oriented

– LSB first

– Delimited by Start and Stop bits

– Stop bits: minimum time with line high between characters

• Common data rates (data rate = 1/Tbit):

300 bps, 1200 bps, 9600 bps, 19200 bps, 38400 bps, 115200 bps

D0 D7START D1 D2 D3 D4 D5 D6 STOP STOPPARITY(optional)

(Nbit+1+Nstop+(parity?))*Tbit

character lengthTbit 1 or 2 Tbit

idle idle5 to 8 data bits

Asynchronous serial communications

Data signals (DTE):

• TXD: Transmitted data

• RXD: Received data

Flow control (data block):

• RTS: Request to send

• CTS: Clear to send

Flow control (session):

• DTR: Data terminal ready

• DSR: Data set ready

Modem status

• DCD: Data carrier detect

• RI: Ring indicator

TXD

RXD

RTS

CTS

DSR

DCD

RI

TXD

RXD

RTS

CTS

DSR

DCD

RI

DTR DTR

status

Control

DATA

MODEM

FLOW

(computer)DTE DCE

(modem)

Many serial ports only include the data lines and, maybe, a minimal flow-control

(RTS,CTS)

UART 16550. Block diagram

• UART: Universal Asynchronous Receiver-Transmitter

• 16550: Industry standard. Used in PCs and many MCUs (LPC2xxx)

• 8-bit peripheral, banked register set

Transmitter

shift register

shift registerSYNC

CTS

DTRRTS

DSRDCDRI

modeloop

TXD

RXD

generator

BAUD RATE

DataBUS

Receiver

clk

TX

FIFO(16 bytes)

RX

FIFO(16 bytes)

ck16

Control

MODEM

Interrupt logicINT

UART 16550 Register map

• RBR: Receiver Buffer Register

• THR: Transmitter Holding Reg.

• IER: Interrupt Enable Register

• IIR: Interrupt Identification Reg.

• FCR: FIFO Control Register

• LCR: Line Control Register

• MCR: Modem Control Register

• LSR: Line Status Register

• MSR: Modem Status Register

• DLM:DLL: Divisor Latch

RD RD

DLAB=1

0 RBR THR

1

FCR

4

6

Scratch

MCR

LCR (DLAB is here)

IER

-

-

-

-

2

3

5

7

LSR

MSR

LSR

MSR

FCR

DLL

DLM

DLAB=0

WR WRaddr.

IIR IIR

• DLAB is only relevant for addresses 0 and 1

• In the LPC2xxx the register address are word aligned (multiply address by 4)

UART 16550 Registers

• RBR and THR. These registers hold the data received (RBR)

and sent to transmitter (THR)

• Even with FIFOs disabled there are 1-byte buffers in front of

shift registers

• With FIFOs enabled RBR and THR are used as RX_FIFO read

and TX_FIFO write registers, respectively


• FCR: FIFO control register (write only)

Bit 0: FIFO enable: Enables both TX and RX FIFOs when 1

Bit 1: RX FIFO Reset: Flush RX FIFO when written as 1 (bit not stored)

Bit 2: TX FIFO Reset: Flush TX FIFO when written as 1 (bit not stored)

Bits 3 to 5: Reserved

Bits [7:6]: RX interrupt trigger level:

FCR[7:6] Trigger level

00 1 byte

01 4 bytes

10 8 bytes

11 14 bytes

An RX data available interrupt is requested when the RX FIFO holds the

same or more bytes than the programmed trigger level .


• LCR: Line Control Register

Bits [1:0]: Character Length

Bit 2: Number of Stop bits: 0: 1 stop bit, 1: 2 stop bits (1.5 bits for

5-bit characters)

Bit 3: Parity enable: 0: no parity, 1: parity added

Bit 4: Even parity: 0: Odd parity 1: Even parity

Bit 5: Stick parity: 0: normal parity 1: replace parity bit with (~LCR[4])

Bit 6: Break control: 0: no break 1: TXD is forced low (Break state)

Bit 7: DLAB: Select which register to access for address 0 and 1. DLAB=1

allows the access to the divisor latch of the Baud rate generator

LCR[1:0] Char. Len.

00 5 bits

01 6 bits

10 7 bits

11 8 bits


• LSR: Line Status Register (read only):

Bit 0: Data Ready: 1: there is data ready for read from RBR, 0: no data

Bit 1: Overrun Error: 1: The RX FIFO was full and data was lost, 0: no error

Bit 2: Parity Error: 1: Wrong parity in the received character, 0: no error

Bit 3: Framing Error: 1: The Stop bit(s) was 0 (wrong data rate?), 0: no error

Bit 4: Break interrupt: 1: The RXD line was low for more time than the

duration of the character, 0: no break

Bit 5: THR Empty: 1: THR is empty or TX FIFO is not full. This means:

Transmitter can accept new data

0: THR or TX FIFO are full

Bit 6: TX Empty: 1: Both the TX FIFO and the shift register are empty

0: At least there is a character in the shift register being

transmitted

Bit 7: Error in RX FIFO: 1: There are errors in the data stored in the RX FIFO

0: Data without errors


• IER: Interrupt Enable Register

Bit 0: RX Data Available interrupt enabled when 1

(RX FIFO trigger level reached or RX timeout, if FIFO enabled)

Bit 1: Transmitter Holding Register Empty interrupt enabled when 1

(TX FIFO empty if FIFO enabled)

Bit 2: Receiver Line Status interrupt enabled when 1

(When an OE, PE, FE error or a Break state are detected)

Bit 3: Modem Status Change interrupt enabled when 1

(When CTS, DRS, DCD or RI change value with respect to last MSR read)

Bits 4-7: Reserved


• IIR: Interrupt Identification Register (read only)

Bit 0: Pending INT: 0: Pending interrupt, 1: no interrupt

Bits [2:1]: Interrupt cause

Bit 3: RX timeout:

Set along RX Data Available when some characters have been stored in the RX

FIFO without reaching the programmed trigger level for more than 4 character

times

Bits 4,5: Always 0

Bits 6,7: 00 if FIFOs are disabled, 11 if FIFOs are enabled

IIR[2:1] Priority Cause Clearing Action

00 Lowest Modem Status MSR read

01 Second THR Empty THR write

10 Third RX Data Available RBR read

11 Highest RX Line Status LSR read


• MCR: Modem Control Register

Bit 0: /DTR: Data Terminal Ready 0: DTR High, 1: DTR Low

Bit 1: /RTS: Request to Send 0: RTS High, 1: RTS Low

Bit 2: /OUT1 (GPIO) 0: OUT1 High, 1: OUT1 Low

(OUT1 is used in PCs to further enable the UART interrupt through a tristate

gate outside the UART)

Bit 3: /OUT2 (GPIO, not used) 0: OUT2 High, 1: OUT2 Low

Bit 4: Loop mode: 0: Normal mode 1: Loop mode

In loop mode the TXD and RXD signals are connected together inside the

UART. Any character transmitted is sent to the receiver. Also, DTR,RTS,OUT1

and OUT2 are tied to DSR,CTS,RI and DCD, respectively.

Bits 5 to 7: Reserved


• MSR: Modem Status Register (read only)

Bit 0: Delta CTS 1: CTS changed 0: no change

Bit 1: Delta DSR 1: DSR changed 0: no change

Bit 2: Delta RI 1: RI changed 0: no change

Bit 3: Delta DCD 1: DCD changed 0: no change

Bit 4: /CTS, Clear to Send, 1: CTS Low 0: CTS High

Bit 5: /DSR, Clear to Send, 1: DSR Low 0: DSR High

Bit 6: /RI, Clear to Send, 1: RI Low 0: RI High

Bit 7: /DCD, Clear to Send, 1: DCD Low 0: DCD High

• Delta bits are set when the corresponding input pin changes its level with

respect to that of the last MSR read.

• Any delta bit set can trigger a Modem Status interrupt


• Baud Rate Divider (accessed when DLAB=1)

DLM: Most significant byte of the 16-bit divider

DLL: Least significant byte of the 16-bit divider

• Baud Rate Calculation:

f_baud = f_clk/(16*divider)

• f_clk is PCLK for LPC2xxx MCUs (and 1.8432 MHz for PCs)

• A divider value of zero has the same effect as divider=1

INDEX

• Introduction



• GPIO

• UART

• Timers

– Basics. Capture. Compare. PWM

– Watchdog

• SPI

• I2C

• ADC

LPC2103 Timers/Counters• 4 Timers:

– Timer0, Timer1: 32-bit

– Timer2, Timer3: 16-bit

• Each Timer can include up to:

– 4 capture inputs, sensitive to signal edges. These signals

can also be used as an external clock (counter mode)

– 4 matching outputs, that can set, clear, or toggle a pin on

matching events. They can also generate PWM waveforms

Some lines are unavailable:

Timer 0: no CAP0.3, no MAT0.3

Timer 2: no CAP2.3

Timer 3: no CAP3.0, no CAP3.1, no CAP3.2, no CAP3.3

• All timers have the same architecture and register set (but

many registers have different widths: 32 or 16 bits)

(In the following slides replace ‘x’ with the timer number. e.g. TxTC -> T1TC )

LPC2xxx Timers. Block Diagram

logic

logic

capture

capture

logic

logic

capture

capture

=

=

=

=

PCLK

CAPTURE

wr

wr

wr

wr

logic & PWM

matching

logic & PWM

logic & PWM

logic & PWM

matching

matching

matchingMATx.2

MATx.3

MATx.1

MATx.0

CAPx.0

CAPx.1

CAPx.2

CAPx.3

TxMR0

TxMR1

TxMR2

TxMR3

TxCR0

TxCR1

TxCR2

TxCR3COUNTER

MATCHING

resetstopTxTC

INT=

TxPR

PRESCALER

reset

TxPC

LPC2xxx Timers. Registers. Control

• TxTC: Timer counter

• TxPC: Prescaler counter

• TxPR: Prescaler register:

TxPC increments at PCLK rate until the value stored in TxPR is reached.

Next cycle, TxPC resets and TxTC increments (if timer mode). The clock

frequency of TxTC is then: PCLK/(TxPR+1)

• TxTCR: Timer Control Register:

Bit 0: Enable 1: Timer enabled, 0: Timer disabled

Bit 1: Reset When 1 both TxTC and TxPC are reset. The reset

state will last until this bit is written with 0

Bits 2-7: Reserved

LPC2xxx Timers. Registers. Control

• TxCTCR: Counter Control Register

Bits [1:0]: Mode select (00 after reset)

Bits [3:2]: Clock source in counter mode

Bits 4-7: Reserved

TxCTCR[1:0] Mode

00 Timer. Increment TxTC on PCLK divided by (TxPR+1)

01 Counter. Increment TxTC on rising edges

10 Counter. Increment TxTC on falling edges

11 Counter. Increment TxTC on both edges

TxCTCR[3:2] Clock source

00 CAPx.0

01 CAPx.1

10 CAPx.2

11 CAPx.3

LPC2xxx Timers. Registers. Capture

• TxCR0, TxCR1, TxCR2, TxCR3 : Capture registers. When a

capture event happens the value of TxTC is copied into one of

these registers

• TxCCR: Capture Control register (3 bits per channel)

Bits [2-0]: CAPx.0 control:

Bit 0: Capture on rising edges if 1

Bit 1: Capture on falling edges if 1

Bit 2: Generate Interrupt on capture if 1

Bits [5-3]: CAPx.1 control (same coding)



Bits [15-12]: Reserved

LPC2xxx Timers. Registers. Matching

• TxMR0, TxMR1, TxMR2, TxMR3 : Matching registers. When

TxTC matches the value of one of these registers several

possible actions can take place

• TxMCR: Matching Control register (3 bits per match register)

Bits [2-0]: MR0 control:

Bit 0: Generate interrupt on matching if 1

Bit 1: Reset TxTC on matching if 1

Bit 2: Stop TxTC on matching if 1

Bits [5-3]: MR1 control (same coding)




LPC2xxx Timers. Registers. Matching

• TxEMR: External Match register (matching actions on pins)

Bit 0: Logic value of MATx.0




Bits [5:4]: MATx.0 Control

Bits [7:6]: MATx1 Control (same coding)




00 Do nothing

01 Clear MATx.0

10 Set MATx.0

11 Toggle MATx.0

LPC2xxx Timers. Registers. PWM

• PWMxCON:PWM Control

Bit 0: MATx.0 PWM mode enabled if 1





• PWM modulation is achieved by turning the MATx.n pin

LOW when TxTC is 0 and HIGH when a match happens

• When PWM mode is selected for a pin its TxEMR bits are

ignored

• Another TxMR register has to be used to define the cycle

period (by resetting TxTC)

LPC2xxx Timers. Registers. PWM timing

• If TxMRn=0 => MATx.n always High

• If TxMRn=TxMRm => Single-cycle High pulse on MATx.n

• If TxMRn>TxMRm => MATx.n always Low

TCvalue

0

MRm value

top

match

match

match

match

match

match

MATx.n

(PWM)

(TC reset)

time

MRn value

Th=(MRm+1-MRn)

T=(MRm+1)

LPC2xxx Timers. Registers. Interrupts

• TxIR: Interrupt Register

Bit 0: TxMR0 match interrupt




Bit 4: Capture to TxCR0 interrupt




These bits have to be cleared by program by writing a mask to

TxIR: (1: Clear interrupt, 0: no effect)

• No interrupt on timer overflow is available. Use a match

interrupt with TxMRn=0 if needed

Watchdog

D

Q

WDTV (down counter)

enable

load

underflow

WDTC

1/4

seq. detectWDFEED

feederror

WDMOD:

reset

interrupt

(to VIC)

WDENWDRESETWDINTWDTOF

WDCLKSEL

RTC osc

PCLK

RC osc

pclk

LPC24xx only

mux

32

Watchdog. Registers

• WDMOD: Mode control and status

Bit name access Reset val. Function

0 WDEN R/W 0 Enable WD (after feed). Sticky

1 WDRESET R/W 0 Enable reset on timeout. Sticky

2 WDTOF R/W 0 if external reset

1 if WD reset

Timeout flag

3 WDINT RO 0 Interrupt flag. Sticky

Note: sticky bits can only be cleared by reset. Writing zeroes has no effect.

• WDTC: Timer count (32-bit, r/w). This value is loaded into the counter on

each feed sequence. Minimum value: 255

• WDTV: Timer value (32-bit, read only). The current value of the counter

• WDFEED: Feed register (8-bit, write only). Writing 0xAA followed by 0x55

reloads the counter with WDTC. An improper writing sequence will trigger

the watchdog interrupt /reset without delay if enabled

Watchdog. Operation

To enable the watchdog the following steps are required:

1. Write the count value to WDTC

2. Write WDMOD with the bits WDEN (and WDRESET) as one

3. Write 0xAA to WDFEED

4. Write 0x55 to WDFEED

To periodically clear the watchdog only these steps are needed:

1. Write 0xAA to WDFEED

2. Write 0x55 to WDFEED

Note that the WD counter runs on the PCLK clock, and therefore, it is stopped

in power down mode severely compromising its efficacy. In the LPC24xx series

of microcontrollers the WD is upgraded allowing the selection of clock sources

from non stoppable oscillators.

INDEX

• Introduction



• GPIO

• UART

• Timers

• SPI

• I2C

• ADC

SPI BUS

SCK MISO

/SS2 /SS3/SS1

MOSI

/SS /SS /SS

SCK MOSI MISO SCK SCKMOSI MOSIMISO MISO

SLAVE3 SLAVE2 SLAVE1

SCK

MISO

MOSI

(uC)MASTER

• Clock and data lines shared between devices

• Independent «slave select» lines: one per slave device

• Clock signal generated by master

SPI bus. Internals

Q7 SDIshift

counter

Q7 SDIshift

gen.CLK

busy

MOSI

MISO

SCK

/SS counterreset

data

MASTER SLAVE

GPIO

dataavail.

BASICS:

• Full-duplex data exchange between master and slave

• MSB bit (D7) first

• Fixed number of bits exchanged (8 bits)

• Burst of 8 clock pulses at SCK

SPI bus timing (POL=0, PHA=0)

SPI mode 0

D2D7 D6 D5 D4 D3 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

/SS

MISO

MOSI

SCK

Both in master and slave:

• Output signals change on falling SCK edges.

• Input signals are sampled on rising SCK edges

• D7 is valid as soon as /SS is low. No SCK edge needed


SPI mode 1

/SS

MISO

MOSI

SCK

D7 D6 D5 D4 D3 D2 D1

D7 D6 D5 D4 D3 D2 D1 D0

D0


• Output signals change on rising SCK edges.

• Input signals are sampled on falling SCK edges

• D7 is valid after the first SCK edge


SPI mode 2

D2D7 D6 D5 D4 D3 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

/SS

MISO

MOSI

SCK


• Output signals change on rising SCK edges.

• Input signals are sampled on falling SCK edges

• D7 is valid as soon as /SS is low. No SCK edge needed


SPI mode 3

/SS

MISO

MOSI

SCK

D7 D6 D5 D4 D3 D2 D1

D7 D6 D5 D4 D3 D2 D1 D0

D0


• Output signals change on falling SCK edges.

• Input signals are sampled on rising SCK edges

• D7 is valid after the first SCK edge

LPC2xxx SPI. Registers

Register Access Function

SxSPCR R/W Control Reg.

SxSPSR RO Status Reg.

SxSPDR WR Data TX

RD Data RX

SxSPCCR R/W Clock Control Reg.

SxSPINT R/W Interrupt Flag

Notes:

• Replace “x” with the SPI port number (i.e. 0 for SPI0 and so on)

• The SSP peripheral can also operate in SPI mode, but it is a different and

more versatile synchronous serial port.

• All registers are addressable as 32-bit words.

LPC2xxx SPI. SxSPCR (Control Reg.)

Bit Symbol meaning

2 BitEnable 0 = 8-bit transfer 1 = variable length

3 CPHA Clock phase (SPI mode)

4 CPOL Clock polarity (SPI mode)

5 MSTR 0 = Slave 1 = Master

6 LSBF 0 = MSB first 1 = LSB first

7 SPIE 0 = INT disabled 1 = INT enabled

11:8 BITS Transfer Length (1000=8,… 1111=15, 0000=16)

rest reserved Do not write “1” to reserved bits

• Master mode: SCK and MOSI are outputs. MISO is input. /SS not used (usually

programmed as GPIO) or input (see mode fault, next slide). Timing generated

internally.

• Slave mode: SCK, MOSI and /SS are inputs. MISO is output. Timing controlled by

SCK.

LPC2xxx SPI. SxSPSR (Status Reg.)

• Slave abort happens if /SS is raised before the end of the data

• Mode fault happens on a Master SPI if /SS is forced low externally (another master

is selecting us). This should never happen in a properly designed system. Also, /SS is

seldom used in a master, with /SS usually being programmed as GPIO

• Read overrun happens if data is received while SPIF is high (old data already in the

buffer)

• Write collision happens if SxSPDR is written while a transfer is in progress (no buffer

for TX)

• SPIF is not the interrupt flag (see SxSPINT)

Bit Symbol Meaning Action to clear bit

3 ABRT 1= Slave abort Read SxSPSR

4 MODF 1= Mode Fault Read SxSPSR + write SxSPCR

5 ROVR 1=Read Overrun Read SxSPSR

6 WCOL 1=Write Collision Read SxSPSR + R/W SxSPDR

7 SPIF 1=SPI transfer complete Flag Read SxSPSR + R/W SxSPDR

LPC2xxx SPI. Other Registers

• SxSPDR: Data register.

• Up to 16 bit long

• A write to SxSPDR starts a transfer.

• After the transfer is complete (SPIF=1), SxSPDR contains the data sent

from the other device.

• SxSPCCR: Clock Counter register.

• 8-bit clock frequency divider

• Fsck=PCLK/SxSPCCR

• Only even values ≥8 are valid

• SxSPINT: Interrupt Flag register.

• Bit 0: Interrupt flag. When set it request an interrupt to the VIC

• Set when SPIF=1 (transfer complete) or WCOL=1 (write collision)

• Cleared by writing an 1 to this bit. (It has to be done in the interrupt

routine)

INDEX

• Introduction



• GPIO

• UART

• Timers

• SPI

• I2C

• ADC

I2C bus.

SDA SCL

addr=0x50

SLAVE

SDA_OUT

SDA_IN SDASDA_OUT

L to GND

H open

SDA

SCL_OUT SCL

SCLSDA

MASTER

(uC)

SDA SCL

SLAVE

SDA SCL

SLAVE

addr=0x51

SCL_IN

SCL_OUT

SCL

Vdd

I2C device I2C device

addr=0x3E

• Two-wire, synchronous, serial interface

• Open-drain / open collector logic. External pull-ups (10kohm typical)

• Slave devices selected via internal address (7-bit, typical)

I2C. Features

• Patented by Philips. Other names: TWI (Atmel), SMBus (Intel)

• Open-drain lines guarantee no electrical contention, and also:

• Can synchronize master speed to slow slaves

• Allows mixed 5V and 3.3V devices (just tie pull-ups to 3.3V)

• Maximum data rate: 100 Kbit/s (400 Kbit/s becoming common today)

• MSB first.

• Slave address. Typically:

• 7 bit. (10 bit address is also defined but almost never used)

• MSB bits fixed depending on slave function (1010xxx for memories)

• LSB bits selected via device pins

• 8th bit of the address byte used to select data direction (read or write)

• Every byte sent is acknowledged by the receiver

I2C. Bit timing

valid bit

Tbit (10us min)

SDA

SCL

• SDA only changes when SCL is low

Bitbanging code (master):

uchar I2Cbit(uchar b) {uchar ret=0;if(b) SET_SDA_H();else SET_SDA_L();_delay_T4();SET_SCL_H();_delay_T4();_delay_T4();if (GET_SDA()) ret=1;SET_SCL_L();_delay_T4();return ret;

}

I2C. Start, Stop

SCL

SDA SDA

SCL

STOPSTART

• SDA edge with SCL high

• Bus idle with SDA and

SCL both high before

start and after stop

Bitbanging code:

void I2Cstart(){SET_SDA_L();_delay_T4();SET_SCL_L();_delay_T4();

}

void I2Cstop(){SET_SDA_L();_delay_T4();SET_SCL_H();_delay_T4();SET_SDA_H();_delay_T4();

}

I2C. Byte transfer

D6 D4 D3 D2 D1D7 D5 D0SDA_out

SDA_out

SCL

(TX)

(RX)

1 2 3 4 5 6 7 8 9(master)

ACK

NACK

SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK

• The device who listen to data must left SDA high

• Slave devices must assert ACK (SDA low) after reading a

byte (address or data)

• The master must assert ACK on data read. In this case the

last byte of the frame is followed by NACK instead of ACK

I2C. Write Frame

start 0

r/w

data #1 data #2MASTER

SLAVE

stop

ack ack ack

sl. address

Bitbanging code:

char I2Cwrite (uchar addr, uchar *buffer, uchar len){uchar i,d;d=addr&0xFE; // LSB=0 => WriteI2Cstart();for(i=8;i;i--) {I2Cbit(d&0x80); d<<=1;} if(I2Cbit(1)) {I2Cstop(); return -NACK; }for(;len;len--){

d=*buffer++;for(i=8;i;i--) {I2Cbit(d&0x80); d<<=1;} if(I2Cbit(1)) {I2Cstop(); return -NACK;}

}I2Cstop();return 0; // all OK, no error

}

I2C. Read Frame

start

r/w

MASTER

SLAVE ack

sl. address

data #1

ack

data #2

1 ack

data #n

nack stop

Bitbanging code:

char I2Cread (uchar addr, uchar *buffer, uchar len){uchar i,d;d=addr|1; // LSB=1 => ReadI2Cstart();for(i=8;i;i--) {I2Cbit(d&0x80); d<<=1;} if(I2Cbit(1)) {I2Cstop(); return -NACK; }for(;len;len--){

for(i=8;i;i--) {d<<=1; if (I2Cbit(1)) d++;} *buffer++=d;I2Cbit((len>1)?0:1); // ACK or NACK

}I2Cstop();return 0; // all OK, no error

}

I2C Read/Write Framechar I2Cframe (unsigned char addr, unsigned char *buffer, unsigned char len){

unsigned char i,d;char ret=0; // return 0 if OKI2Cstart();// Address byted=addr;for(i=8;i;i--) {I2Cbit(d&0x80); d<<=1;}if(!I2Cbit(1)) { // ACK for address: continue

// data bytesif (addr&1) {

// Read framefor(;len;len--){

for(i=8;i;i--) {d<<=1; if (I2Cbit(1)) d++;}*buffer++=d;I2Cbit((len>1)?0:1); // ACK or NACK

}} else {

// Write framefor(;len;len--){

d=*buffer++;for(i=8;i;i--) {I2Cbit(d&0x80); d<<=1;}if(I2Cbit(1)) {ret=-NACK; break;} // NACK for data: abort

}}

} else ret=-NACK; // NACK for address: abortI2Cstop();return ret;

}

I2C. Hardware dependent Bitbang

• Only 5 I/O functions/macros to be defined. In this example SCL is

simulated by P0.2 and SDA by P0.3:#define SET_SDA_L() (IO0DIR|=(1<<3)) // SDA -> P0.3#define SET_SDA_H() (IO0DIR&=~(1<<3))#define SET_SCL_L() (IO0DIR|=(1<<2)) // SCL -> P0.2void SET_SCL_H() {

IO0DIR&=~(1<<2);while ((IO0PIN&(1<<2))==0);

}#define GET_SDA() (IO0PIN&(1<<3))

• P0.2 and P0.3 must be set low before using the I2C codeIO0CLR=(1<<3)|(1<<2);

• SET_SCL_H must wait until SCL is really high because an slave can hold

SCL low when busy (flow control)

Hardware I2C controller. Registers

Register Access Description

I2CONSET R/W Write: Set bits in Control Reg.

I2CONCLR WO Write: Clear bits in Control Reg.

I2STAT RO Status Reg.

I2DAT R/W Data reg.

I2ADR R/W I2C slave address (only used in slave mode)

I2SCLH R/W SCL high time (PCLK cycles)

I2SCLL R/W SCL low time (PCLK cycles)

• Writing zeroes to bits in I2CONSET or I2CONCLR has no effect

Hardware I2C controller. Control Reg.

• Bit 6: I2EN. I2C Enable bit.

• Bit 5: STA. Start bit. Setting this bit enters master mode and sends

an START condition to the bus. SI is set when done.

• Bit 4: STO. Stop bit. Setting this bit transmits a STOP condition

(master mode)

• Bit 3: SI. Interrupt Flag. Set when an action is complete. When

one, the I2STA register provides a suitable status code. This bit

has to be cleared by program (by writing to I2CONCLR). Byte

transfer is stopped while SI is set, therefore, I2DAT must have

valid data before clearing SI.

• Bit 2: AA. Assert Acknowledge. Enables the assertion of the ACK

bit in receiver modes.

Hardware I2C controller. Address Reg.

• Bit 0: GC. General Call. Enables the acknowledge of General Call

(broadcast) address (slave address = 0)

• Bits 7:1: Slave Address.

Hardware I2C controller operation

• Byte oriented controller.

• Master Mode

• First byte after START is the slave address plus R/W bit.

• If R/W was one the controller enters master receiver mode.

Otherwise it continues operating as master transmitter.

• In master receiver mode AA must be set except for the last

byte.

Hardware I2C controller.

Status Codes for Master Transmitter

I2STAT Status Next action

0x08 START condition transmitted Load Slave address + R/W=0

0x18 Slave address transmitted. ACK received Load data byte

0x20 Slave address transmitted. NACK received Transmit STOP

0x28 Data byte transmitted. ACK received Load data byte / transmit STOP

0x30 Data byte transmitted. NACK received Transmit STOP


Status Codes for Master Receiver

I2STAT Status Next action

0x08 START condition transmitted Load Slave address + R/W=1

0x40 Slave address transmitted. ACK received Data byte will be received

0x48 Slave address transmitted. NACK received Transmit STOP

0x50 Data byte received. ACK transmitted Data byte will be received

0x58 Data byte received. NACK transmitted Transmit STOP


Master Transmitter (write) procedure1. Set I2EN (enable I2C), and load I2SCLH and I2SCLL with proper values.

2. Clear SI.

3. Set STA.

4. Wait until SI becomes one. I2STAT should be 0x08

5. Clear STA

6. Write I2DAT=(address<<1); in order to send the slave address

7. Clear SI

8. Wait until SI becomes one. I2STAT should be 0x18. Set STO otherwise and

abort

9. Write I2DAT with data byte

10.Clear SI

11.Wait until SI becomes one. I2STAT should be 0x28. Set STO otherwise and

abort

12.Repeat from step #9 until all data bytes are transmitted

13.Set STO

14.Clear SI


Master Receiver (read) procedure1. Set I2EN (enable I2C), and load I2SCLH and I2SCLL with proper values.

2. Clear SI.

3. Set STA.

4. Wait until SI becomes one. I2STAT should be 0x08

5. Clear STA

6. Write I2DAT=(address<<1)+1; in order to send the slave address

7. Clear SI

8. Wait until SI becomes one. I2STAT should be 0x40. Set STO otherwise and

abort

9. Set AA in order to acknowledge incoming bytes

10.Clear SI

11.Wait until SI becomes one. I2STAT should be 0x50. Set STO otherwise and

abort

12.Read the received byte from I2DAT and store it

13.If just one byte is pending clear AA

14.Repeat from step #10 until all data bytes are received

15.Set STO

16.Clear SI


Notes• Slave modes are better managed from interrupt routines because

we must react quickly to external masters.

• SCL is stretched in the low state while the SI flag is one. This

guarantees that no data is lost if the slave is slow to respond,

but the average data rate can decrease significantly

• I2STAT provides information for a state-machine implementation

(switch-case statement) in the ISR routine

• Refer to NXP datasheet and code examples for more detailed

information.

INDEX

• Introduction



• GPIO

• UART

• Timers

• SPI

• I2C

• ADC

Analog to Digital Converter (ADC)

Dout=Vin

Vref2

n

n-bits

ADCVin

Vref

Doutn

input range

7

Vref

DoutExample (3-bit)

1

2

3

4

5

6

0

Vin

Vdd

• Analog inputs (Vin): any voltage between GND (0V) and Vdd allowed

• Result (Dout): a n-bit data proportional (as long as quantization is ignored) to Vin

• Successive approximation method common:

• 1 clock cycle (guess iteration) per bit of resolution.

• Analog input sampled at the beginning of iteration.

LPC2103 ADC. Block diagram

AD0

AD1

AD2

AD3

AD4

AD6

AD7

AD5

Vref

ADC 10-bit

SEL

start clk

EDGEW

R_A

D0C

R

P0.

16

P0.

22

MA

T0.

1

MA

T0.

3

MA

T1.

0

MA

T1.

1

AD0INTEN

AD0CR

AD0DR7

AD0DR6

AD0DR5

AD0DR4

AD0DR3

AD0DR2

AD0DR1

AD0DR0

mux

anal

og m

ux.

AD0GDRAD0STAT

dividerSTART

CLKDIV

PCLK

AVdd

LPC2103 ADC. Control reg. AD0CR (R/W)

• Bits [7:0] SEL: Channel select mask. 1 bit per enabled input. Example: 00000101

enables conversions on AD0 and AD2. Selected channels are converted sequentially

• Bits [15:8] CLKDIV: PCLK frequency is divided by (CLKDIV+1) to obtain the ADC clock

frequency. This frequency must be less than 4.5MHz.

• Bit 16 BURST: Enables repeated conversions if set to 1: The ADC is triggered again after

each conversion is complete. Single conversion if 0.

• Bits [19:17] CLKS: Clock cycles per conversion / ADC resolution

value Clocks resolution

000 11 10-bit

001 10 9-bit

010 9 8-bit

011 8 7-bit

100 7 6-bit

101 6 5-bit

110 5 4-bit

111 4 3-bit

LPC2103 ADC. Control reg. AD0CR (R/W)

• Bit 21 PDN: 1 – The ADC is operational. 0 – The ADC is in power-down mode

• Bits [26:24] START: Select the event to trigger the conversions

value Trigger source

000 No start (used with burst mode)

001 Start conversion now

010 Start on edge on P0.16

011 Start on edge on P0.22

100 Start on edge on MAT0.1




• Bit 27 EDGE: Start conversions on: 1 – Falling edge. 0 – Rising Edge

LPC2103 ADC

Global DATA reg. AD0GDR (R/W)• Bits [5:0] Reserved

• Bits [15:6] RESULT: The value of the last converted channel is stored in this field

• Bits [26:24] CHN: Number of the last channel converted

• Bit 30 OVERRUN: 1: Data lost in burst mode. Cleared automatically when reading AD0GDR

• Bit 31 DONE: Set to 1 when an ADC conversion completes. Cleared after AD0GDR is read

and after AD0CR is written.

Individual DATA registers AD0DRx (R/0)• Bits [5:0] Reserved

• Bits [15:6] RESULT: The value of the last conversion for this channel is stored in this field

• Bit 30 OVERRUN: 1: Data lost in burst mode. Cleared automatically when reading AD0DRx

• Bit 31 DONE: Set to 1 when an ADC conversion completes. Cleared after AD0DRx is read

LPC2103 ADC

Status reg. AD0STAT (RO)• Bits [7:0] DONE7 – DONE0: Individual DONE flags (one per channel)

• BITS [15:8] OVERRUN7 – OVERRUN0: Individual OVERRUN Flags

• BIT 16 ADINT: Interrupt flag. Set when a conversion completes in an interrupt-enabled

channel (DONE=1). Cleared along with DONE.

Interrupt Enable register AD0INTEN (R/W)• Bits [7:0] ADINTEN7 – ADINTEN0: Interrupt enable bits. If 1 the corresponding channel

will generate an interrupt when its conversion completes.

LPC2103 ADC. Usage notes

• The AVdd and AGND pins must be connected to an accurate 3.3V power supply.

There is no Vref pin. Therefore the ADC reference is AVdd (3.3V)

• The selected channels are scanned sequentially. The resulting sampling rate is

then: Fsamp=Fpclk/(CLKDIV+1)/(Nbit+1)/Nch, were Nbit is the selected

resolution and Nch is the number of selected channels.

• The analog function of the ADC pins has to be selected in the PINSEL0 and

PINSEL1 registers.

• When a MATx.x pin is used as the ADC trigger source the corresponding TxEMR

(external match) register has to be programmed even if the MATx.x pin is

programmed as GPIO in PINSELx

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