Introduction Feature - Microchip...
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8-bit AVR Microcontrollers
ATmega164PA
DATASHEET SUMMARY
Introduction
The Atmel® picoPower® ATmega164PA is a low-power CMOS 8-bitmicrocontroller based on the AVR® enhanced RISC architecture. Byexecuting powerful instructions in a single clock cycle, the ATmega164PAachieves throughputs close to 1MIPS per MHz. This empowers systemdesigner to optimize the device for power consumption versus processingspeed.
Feature
High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family• Advanced RISC Architecture
– 131 Powerful Instructions– Most Single Clock Cycle Execution– 32 x 8 General Purpose Working Registers– Fully Static Operation– Up to 20 MIPS Throughput at 20MHz– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments– 16KBytes of In-System Self-Programmable Flash Program
Memory– 512Bytes EEPROM– 1KBytes Internal SRAM– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM– Data Retention: 20 Years at 85°C/100 Years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits• In-System Programming by On-chip Boot Program• True Read-While-Write Operation
– Programming Lock for Software Security
• Atmel QTouch® Library Support– Capacitive Touch Buttons, Sliders and Wheels– QTouch and QMatrix acquisition– Up to 64 Sense Channels
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• JTAG (IEEE std. 1149.1 Compliant) Interface– Boundary-scan Capabilities According to the JTAG Standard– Extensive On-chip Debug Support– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode– Real Time Counter with Separate Oscillator– Six PWM Channels– 8-channel 10-bit ADC
• Differential Mode with Selectable Gain at 1×, 10× or 200×– One Byte-oriented 2-wire Serial Interface (Philips I2C compatible)– Two Programmable Serial USART– One Master/Slave SPI Serial Interface– Programmable Watchdog Timer with Separate On-chip Oscillator– On-chip Analog Comparator– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features– Power-on Reset and Programmable Brown-out Detection– Internal Calibrated RC Oscillator– External and Internal Interrupt Sources– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby• I/O and Packages
– 32 Programmable I/O Lines– 40-pin PDIP– 44-lead TQFP– 44-pad VQFN/QFN– 44-pad DRQFN– 49-ball VFBGA
• Operating Voltage:– 1.8 - 5.5V
• Speed Grades– 0 - 4MHz @ 1.8V - 5.5V– 0 - 10MHz @ 2.7V - 5.5V– 0 - 20MHz @ 4.5 - 5.5V
• Power Consumption at 1MHz, 1.8V, 25°C– Active Mode: 0.4mA– Power-down Mode: 0.1μA– Power-save Mode: 0.6μA (Including 32kHz RTC)
Note: 1. Refer to Data Retention
Related Links
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Data Retention on page 16
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Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description.................................................................................................................5
2. Configuration Summary.............................................................................................6
3. Ordering Information .................................................................................................7
4. Block Diagram........................................................................................................... 8
5. Pin Configurations..................................................................................................... 95.1. Pinout........................................................................................................................................... 95.2. Pin Descriptions..........................................................................................................................12
6. I/O Multiplexing........................................................................................................14
7. General Information.................................................................................................167.1. Resources.................................................................................................................................. 167.2. Data Retention............................................................................................................................167.3. About Code Examples................................................................................................................167.4. Capacitive Touch Sensing.......................................................................................................... 16
8. Packaging Information.............................................................................................178.1. 40-pin PDIP................................................................................................................................ 178.2. 44-pin TQFP...............................................................................................................................188.3. 44-pin VQFN...............................................................................................................................198.4. 44-pin QFN.................................................................................................................................208.5. 49-pin VFBGA............................................................................................................................ 21
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1. DescriptionThe Atmel® ATmega164PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISCarchitecture. By executing powerful instructions in a single clock cycle, the ATmega164PA achievesthroughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for powerconsumption versus processing speed.
The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registersto be accessed in a single instruction executed in one clock cycle. The resulting architecture is more codeefficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega164PA provides the following features: 16Kbytes of In-System Programmable Flash withRead-While-Write capabilities, 512bytes EEPROM, 1Kbytes SRAM, 32 general purpose I/O lines, 32general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with comparemodes and PWM, two serial programmable USARTs , one byte-oriented 2-wire Serial Interface (I2C), a 8-channel 10-bit ADC with optional differential input stage with programmable gain, a programmableWatchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG testinterface, also used for accessing the On-chip Debug system and programming and six softwareselectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contentsbut freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. InPower-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer basewhile the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/Omodules except asynchronous timer and ADC to minimize switching noise during ADC conversions. InStandby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. Thisallows very fast start-up combined with low power consumption. In Extended Standby mode, both themain oscillator and the asynchronous timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionalityinto AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing andincludes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™)technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows youto explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISPFlash allows the program memory to be reprogrammed In-System through an SPI serial interface, by aconventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.The Boot program can use any interface to download the application program in the Application Flashmemory. Software in the Boot Flash section will continue to run while the Application Flash section isupdated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-SystemSelf-Programmable Flash on a monolithic chip, the Atmel ATmega164PA is a powerful microcontrollerthat provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega164PA is supported with a full suite of program and system development tools including: CCompilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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2. Configuration SummaryThe table below compares the device series of feature and pin compatible devices, providing a seamlessmigration path.
Table 2-1. Configuration Summary and Device Comparison
Features ATmega164PA ATmega324PA ATmega644PA ATmega1284P
Pin Count 40/44/49 40/44/49 40/44 40/44
Flash (Bytes) 16K 32K 64K 128K
SRAM (Bytes) 1K 2K 4K 16K
EEPROM (Bytes) 512 1K 2K 4K
General PurposeI/O Lines
32 32 32 32
SPI 1 1 1 1
TWI (I2C) 1 1 1 1
USART 2 2 2 2
ADC 10-bit 15ksps 10-bit 15ksps 10-bit 15ksps 10-bit 15ksps
ADC Channels 8 8 8 8
Analog Comparator 1 1 1 1
8-bit Timer/Counters
2 2 2 2
16-bit Timer/Counters
1 1 1 2
PWM channels 6 6 6 8
Packages PDIP
TQFP
VQFN/QFN
DRQFN
VFBGA
PDIP
TQFP
VQFN/QFN
DRQFN
VFBGA
PDIP
TQFP
VQFN/QFN
PDIP
TQFP
VQFNQFN
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3. Ordering InformationSpeed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range
20 1.8 - 5.5 ATmega164PA-AU
ATmega164PA-AUR(5)
ATmega164PA-PU
ATmega164PA-MU
ATmega164PA-MUR(5)
ATmega164PA-MCH(4)
ATmega164PA-MCHR(4)(5)
ATmega164PA-CU
ATmega164PA-CUR(5)
44A
44A
40P6
44M1
44M1
44MC
44MC
49C2
49C2
Industrial(-40°C to 85°C)
20 1.8 - 5.5 ATmega164PA-AN
ATmega164PA-ANR(5)
ATmega164PA-PN
ATmega164PA-MN
ATmega164PA-MNR(5)
44A
44A
40P6
44M1
44M1
Industrial(-40°C to 105°C)
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.3. Refer to Speed Grades for Speed vs. VCC4. NiPdAu Lead Finish.5. Tape & Reel.
Package Type
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
44M1 44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44MC 44-lead (2-row Staggered), 5 × 5 × 1.0mm body, 2.60 × 2.60mm Exposed Pad, Quad Flat No-LeadPackage (QFN)
49C2 49-ball, (7 × 7 Array) 0.65mm Pitch, 5 × 5 × 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
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4. Block DiagramFigure 4-1. Block Diagram
CPU
USART 0
ADCADC[7:0]AREF
RxD0TxD0XCK0
I/OPORTS
DATABUS
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASHNVM
programming
JTAG
IN/OUT
DATABUS
TC 0(8-bit)
SPI
ACAIN0AIN1ACOADCMUX
EEPROM
EEPROMIF
TC 1(16-bit)
OC1A/BT1
ICP1
TC 2(8-bit async) TWI
SDASCL
USART 1RxD1TxD1XCK1
InternalReference
Watchdog Timer
Power management
and clock control
VCC
GND
Clock generation
8MHzCalib RC
128kHz int osc
32.768kHz XOSC
External clock
Power SupervisionPOR/BOD &
RESET
TOSC2
XTAL2
RESET
XTAL1
TOSC1
16MHz LP
XOSC
TCKTMSTDI
TDO
PCINT[31:0]INT[2:0]
T0OC0AOC0B
MISOMOSISCKSS
OC2AOC2B
PA[7:0]PB[7:0]PC[7:0]PD[7:0]
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5. Pin Configurations
5.1. Pinout
5.1.1. PDIP
(PCINT8/XCK0/T0)
(PCINT9/CLKO/T1)
(PCINT10/INT2/AIN0)
(PCINT11/OC0A/AIN1)(PCINT12/OC0B/
(PCINT13/MOSI)(PCINT14/MISO)
(PCINT15//SCK)
(PCINT24/RXD0)
(PCINT25/TXD0)
(PCINT26/RXD1/INT0)(PCINT27/TXD1/INT1)
(PCINT28/XCK1/OC1B)(PCINT29/OC1A)
(PCINT30/OC2B/ICP1)
(ADC0/PCINT0)
(ADC1/PCINT1)
(ADC2/PCINT2)(ADC3/PCINT3)
(ADC4/PCINT4)
(ADC5/PCINT5)(ADC6/PCINT6)
(ADC7/PCINT7)
(TOSC2/PCINT23)
(TOSC1/PCINT22)
(TDI/PCINT21)(TDO/PCINT20)
(TMS/PCINT19)
(TCK/PCINT18)
(SDA/PCINT17)(SCL/PCINT16)
(OC2A/PCINT31)
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
XTAL2XTAL1
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5.1.2. TQFN and QFN
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
1
2
3
443 42 41 40 39 38 37
5
6
7
8
35 34222120191817
36
9
10
11
12 13 14 15 16
(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6
(PCINT15/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
4432
31
30
29
28
27
26
24
23
25
33
PB4
(SS/
OC0
B/PC
INT1
2)
PB3
(AIN
1/O
C0A
/PCI
NT1
1)
PB2
(AIN
0/IN
T2/P
CIN
T10)
PB1
(T1/
CLK
O/P
CIN
T9)
PB0
(XCK
0/T0
/PCI
NT8
)
GN
D
VCC
PA0
(AD
C0/P
CIN
T0)
PA1
(AD
C1/P
CIN
T1)
PA2
(AD
C2/P
CIN
T2)
PA3
(AD
C3/P
CIN
T3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
(PC
INT2
7/TX
D1/
INT1
) PD
3
(PCI
NT2
8/X
CK1/
OC1
B) P
D4
(
PCIN
T29/
OC1
A) P
D5
(PC
INT3
0/O
C2B/
ICP1
) PD
6
(
PCIN
T31/
OC2
A) P
D7
V
CC
G
ND
(PC
INT1
6/SC
L) P
C0
(PC
INT1
7/SD
A) P
C1
(PC
INT1
8/TC
K) P
C2
(PC
INT1
9/TM
S) P
C3
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5.1.3. DRQFN
Top view Bottom view
A1B1 A2B2 A3B3 A4B4 A5B5 A6
A18 B15A17 B14A16 B13A15 B12A14 B11A13
A12
B
10A1
1
B9
A10
B8A9
B7
A8
B6A7
A24 B20A23 B19A22 B18A21 B17A20 B16A19
A18B15 A17B14 A16B13 A15B12 A14B11 A13
A1 B1A2 B2A3 B3A4 B4A5 B5A6
A7
B6A8
B7
A9
B8A1
0
B9
A11
B10
A12
A19 B16A20 B17A21 B18A22 B19A23 B20A24
Table 5-1. DRQFN Pinout
A1 PB5 A7 PD3 A13 PC4 A19 PA3
B1 PB6 B6 PD4 B11 PC5 B16 PA2
A2 PB7 A8 PD5 A14 PC6 A20 PA1
B2 RESET B7 PD6 B12 PC7 B17 PA0
A3 VCC A9 PD7 A15 AVCC A21 VCC
B3 GND B8 VCC B13 GND B18 GND
A4 XTAL2 A10 GND A16 AREF A22 PB0
B4 XTAL1 B9 PC0 B14 PA7 B19 PB1
A5 PD0 A11 PC1 A17 PA6 A23 PB2
B5 PD1 B10 PC2 B15 PA5 B20 PB3
A6 PD2 A12 PC3 A18 PA4 A24 PB4
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5.1.4. VFBGA
67
VCC
XTAL1
PD02
PB04
PB05
XTAL2
PD01
PD03
PD04
PB02
PB03
PB07
PD00
PD05
PD06
VCC
PB00
PB01
PD07
PC00
VCC
PC05
PC02
PC01
PA06
PA07
PC07
PC04
PC03
AREF
AVCC
PC06
Programming/debug
5.2. Pin Descriptions
5.2.1. VCCDigital supply voltage.
5.2.2. GNDGround.
5.2.3. Port A (PA[7:0])This port serves as analog inputs to the Analog-to-digital Converter.
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.The output buffers have symmetrical drive characteristics, with both high sink and source capability. Asinputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Portpins are tri-stated when a reset condition becomes active, even if the clock is not running.
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5.2.4. Port B (PB[7:0])This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.The output buffers have symmetrical drive characteristics, with both high sink and source capability. Asinputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Portpins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of various special features.
5.2.5. Port C (PC[7:0])This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.The output buffers have symmetrical drive characteristics, with both high sink and source capability. Asinputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Portpins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of the JTAG interface, along with special features.
5.2.6. Port D (PD[7:0])This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.The output buffers have symmetrical drive characteristics, with both high sink and source capability. Asinputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Portpins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of various special features.
5.2.7. RESETReset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even ifthe clock is not running. Shorter pulses are not guaranteed to generate a reset.
5.2.8. XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
5.2.9. XTAL2Output from the inverting Oscillator amplifier.
5.2.10. AVCCAVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externallyconnected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC througha low-pass filter.
5.2.11. AREFThis is the analog reference pin for the Analog-to-digital Converter.
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6. I/O MultiplexingEach pin is by default controlled by the PORT as a general purpose I/O and alternatively it can beassigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
32-pinTQFP/ QFN/MLF Pin #
40-pinPDIP Pin#
DRQFN Pin# VFBGA Pin# PAD EXTINT PCINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
1 6 A1 B2 PB[5] PCINT13 MOSI
2 7 B1 B1 PB[6] PCINT14 MISO
3 8 A2 C3 PB[7] PCINT15 SCK
4 9 B2 C2 RESET
5 10 A3 A5 VCC
6 11 B3 A1 GND
7 12 A4 D2 XTAL2
8 13 B4 E1 XTAL1
9 14 A5 D3 PD[0] PCINT24 RxD0
10 15 B5 E2 PD[1] PCINT25 TxD0
11 16 A6 F1 PD[2] INT0 PCINT26 RxD1
12 17 A7 F2 PD[3] INT1 PCINT27 TXD1
13 18 B6 G2 PD[4] PCINT28 OC1B XCK1
14 19 A8 E3 PD[5] PCINT29 OC1A
15 20 B7 F3 PD[6] PCINT30 OC2B ICP1
16 21 A9 E4 PD[7] PCINT31 OC2A
17 - B8 C1 VCC RxD2 MISO1
18 - A10 A4 GND TxD2 MOSI1
19 22 B9 F4 PC[0] PCINT16 SCL
20 23 A11 G5 PC[1] PCINT17 SDA
21 24 B10 F5 PC[2] PCINT18 TCK
22 25 A12 G6 PC[3] PCINT19 TMS
23 26 A13 F6 PC[4] PCINT20 TDO
24 27 B11 E5 PC[5] PCINT21 TDI
25 28 A14 F7 PC[6] PCINT22 TOSC1
26 29 B12 E6 PC[7] PCINT23 TOSC2
27 30 A15 E7 AVCC
28 31 B13 D1 GND
29 32 A16 C7 AREF AREF
30 33 B14 D6 PA[7] PCINT7 ADC7
31 34 A17 C6 PA[6] PCINT6 ADC6
32 35 B15 B7 PA[5] PCINT5 ADC5
33 36 A18 D5 PA[4] PCINT4 ADC4
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32-pinTQFP/ QFN/MLF Pin #
40-pinPDIP Pin#
DRQFN Pin# VFBGA Pin# PAD EXTINT PCINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
34 37 A19 B6 PA[3] PCINT3 ADC3
35 38 B16 A6 PA[2] PCINT2 ADC2
36 39 A20 C5 PA[1] PCINT1 ADC1
37 40 B17 B5 PA[0] PCINT0 ADC0
38 - A21 G3 VCC SDA1
39 - B18 A7 GND SCL1
40 1 A22 B4 PB[0] PCINT8 T0 XCK0
41 2 B19 C4 PB[1] PCINT9 CLKO T1
42 3 A23 A3 PB[2] INT2 PCINT10 AIN0
43 4 B20 B3 PB[3] PCINT11 AIN1 OC0A
44 5 A24 A2 PB[4] PCINT12 OC0B SS
- - - D4 GND
- - - D7 GND
- - - G1 GND
- - - G4 GND
- - - G7 GND
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7. General Information
7.1. ResourcesA comprehensive set of development tools, application notes, and datasheets are available for downloadon http://www.atmel.com/avr.
7.2. Data RetentionReliability Qualification results show that the projected data retention failure rate is much less than 1 PPMover 20 years at 85°C.
7.3. About Code ExamplesThis documentation contains simple code examples that briefly show how to use various parts of thedevice. These code examples assume that the part specific header file is included before compilation. Beaware that not all C compiler vendors include bit definitions in the header files and interrupt handling in Cis compiler dependent. Confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructionsmust be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
7.4. Capacitive Touch Sensing
7.4.1. QTouch LibraryThe Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces onmost Atmel AVR® microcontrollers. The QTouch Library includes support for the Atmel QTouch and AtmelQMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for theAVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,and then calling the touch sensing API’s to retrieve the channel information and determine the touchsensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location: http://www.atmel.com/technologies/touch/. For implementation details and other information, refer to the AtmelQTouch Library User Guide - also available for download from the Atmel website.
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http://www.atmel.com/avrhttp://www.atmel.com/technologies/touch/http://www.atmel.com/technologies/touch/http://www.atmel.com/dyn/resources/prod_documents/doc8207.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc8207.pdf
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8. Packaging Information
8.1. 40-pin PDIP
PIN1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
1. This package conforms to JEDEC reference MS-011, Variation AC.2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
Notes:
40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual Inline Package (PDIP) 40P6 C
13/02/2014
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8.2. 44-pin TQFP
44A, 44-lead, 10 x 10mm body s ize , 1.0mm body thickness ,0.8 mm lead pitch, thin profile plas tic quad fla t package (TQFP) C
44A
06/02/2014
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1D
eE1 E
B
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes : 1. This package conforms to JEDEC refe rence MS-026, Varia tion ACB.
2. Dimens ions D1 and E1 do not include mold protrus ion. Allowable protrus ion is 0.25mm per s ide . Dimens ions D1 and E1 a re maximum plas tic body s ize dimens ions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 0.37 0.45
C 0.09 (0.17) 0.20
L 0.45 0.60 0.75
e 0.80 TYP
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8.3. 44-pin VQFN
TITLE DRAWING NO.GPC REV.Package Drawing Contact: [email protected] 44M1ZWS H
44M1, 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (VQFN)
9/26/08
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 – 0.02 0.05
A3 0.20 REF
b 0.18 0.23 0.30
D
D2 5.00 5.20 5.40
6.90 7.00 7.10
6.90 7.00 7.10
E
E2 5.00 5.20 5.40
e 0.50 BSC
L 0.59 0.64 0.69
K 0.20 0.26 0.41Note : JEDEC Standard MO-220, Fig . 1 (S AW Singulation) VKKD-3 .
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D
E
Marked Pin# 1 I D
E2
D2
b e
Pin #1 Co rne rL
A1
A3
A
SE ATING PLANE
Pin #1 Triangle
Pin #1 Cham fer(C 0.30)
Option A
Option B
Pin #1 Notch (0.20 R)
Option C
K
K
123
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8.4. 44-pin QFN
TITLE DRAWING NO. REV.Package Drawing Contact:[email protected] 44MC A
9/13/07
D2
E2L L
B15
A18
B11
A13
B10
A12
B6
A7
A6
B5
B1
B20
A1
A24
eT
L
b
R0.20 0.40
eR
A19
B16
eT/2
SIDE VIEW
A1A
y
C
D
E
Pin 1 ID
TOP VIEW
BOTTOM VIEW
Note: 1. The terminal #1 ID is a Laser-marked Feature.
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
b 0.18 0.23 0.30
C 0.20 REF
D 4.90 5.00 5.10
D2 2.55 2.60 2.65
E 4.90 5.00 5.10
E2 2.55 2.60 2.65
eT – 0.70 –
eR – 0.40 –
K 0.45 – –
L 0.30 0.35 0.40
y 0.00 – 0.075
44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00mm Body, 2.60 x 2.60mm Exposed Pad, Quad Flat No Lead Package
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8.5. 49-pin VFBGA
TITLE DRAWING NO.GPC REV.Package Drawing Contact:[email protected] 49C2CBD A
49C2, 49-ball (7 x 7 array), 0.65mm pitch, 5.0 x 5.0 x 1.0mm, very thin, f ne-pitch ball grid array package (VFBGA)
3/14/08
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTEA – – 1.00 A1 0.20 – – A2 0.65 – – D 4.90 5.00 5.10 D1 3.90 BSC E 4.90 5.00 5.10 E1 3.90 BSC b 0.30 0.35 0.40 e 0.65 BSC
TOP VIEW
SIDE VIEW
A1 BALL ID
G F E D C B A
1 2 3 4 5 6 7
AA1
A2
D
E0.10
E1
D1
49 - Ø0.35 ±0.05
e
A1 BALL CORNER
BOTTOM VIEW
b e
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© 2016 Atmel Corporation. / Rev.: Atmel-42713C-ATmega164PA_Datasheet_Summary-10/2016
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IntroductionFeatureTable of Contents1. Description2. Configuration Summary3. Ordering Information4. Block Diagram5. Pin Configurations5.1. Pinout5.1.1. PDIP5.1.2. TQFN and QFN5.1.3. DRQFN5.1.4. VFBGA
5.2. Pin Descriptions5.2.1. VCC5.2.2. GND5.2.3. Port A (PA[7:0])5.2.4. Port B (PB[7:0])5.2.5. Port C (PC[7:0])5.2.6. Port D (PD[7:0])5.2.7. RESET5.2.8. XTAL15.2.9. XTAL25.2.10. AVCC5.2.11. AREF
6. I/O Multiplexing7. General Information7.1. Resources7.2. Data Retention7.3. About Code Examples7.4. Capacitive Touch Sensing7.4.1. QTouch Library
8. Packaging Information8.1. 40-pin PDIP8.2. 44-pin TQFP8.3. 44-pin VQFN8.4. 44-pin QFN8.5. 49-pin VFBGA