Intro to Verilog
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Assembly Language and Computer Organization
Richard A. Goodrum
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SourcesComputer Organization and Design, Fourth
Edition, Patterson and HennessyVerilog Hardware Description Language,
The, Fifth Edition, Thomas and Moorbyhttp://www.asic-world.com/verilog/
syntax.html
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White SpaceBlank spaces Tabs Carriage returns New-line Form-feeds
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CommentsC and C++ Style Comments
From // to the end-of lineMulti-line comments beginning with /* and
ending with */
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Case SensitivityVerilog is case sensitive
“Code” is not the same as “code”All Verilog keywords are lower case.
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IdentifiersBegin with alphabetic or underscore symbolsMay contain alphanumeric, underscore, or $
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Escaped IdentifiersBegin with backslashEnd with white space
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NumbersIntegersReal (Floating Point)
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Data TypesTo connect ports requires a “wire”
wire [31:0] xyzzy; // is a 32-bit wirewire [3:0] plugh; is a 4-bit wire
To store values requires a “reg”reg [5:0] omega; // is a single 6-bit registerreg [31:0] delta[0:31]; // is 32 32-bit registers
otherwise known as a memory
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Data Types in VerilogData values
01x - unknownz – high impedience
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Data Representationw’rnw is the field width, an unsigned decimal value
specifying the number of bits in the value.r is the radix
h – hexd – decimalo – octalb – binary
n is the number represented in the appropriate radix
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Data Examples6’d51 is the decimal value 51 stored as a 6-
bit quantity3’b010 is the 3-bit quantity 010 binary = 2
decimal8’o67 is the 8-bit value 0011_0111 binary =
55 decimal12’h31 is the 12-bit value 0000_0011_0001
binary = 49 decimal
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Data Concatenation{r1{b1}[,ri{bi}]}
The braces are dropped after evaluationThe brackets represent optional, repeatable
fields.rj – an optional repeat count for the bit fieldbj – bit field representation of a value
bj Data Representation
Example{3{1’b1},2’b0,3’b111} = 8’b1110_0111 = 8’he7
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Exercise – Verilog ValuesWhich of the following define exactly the
same values?8’b111100008’hF08’d240{{4{1’b1}},{4{1’b0}}}{4’b1,4’b0}
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Answer – Verilog ValuesAll of them
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Operators in Verilog Assignment Operators
=, <= Arithmetic Operators
+, -, *, /, % Logical Operators
&&, ||, ! Bit-wise
~, &, |, ^, ~^, ^~ Comparison Operators
==, ===, !=, !==, >, <, <=, >= Shift Operators
<<, >> Conditional Operator
?: Unary Reduction Operators
&, ~&, |, ~|, ^, ~^, ^~ Concatenation Operator
{}
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Concatenation Operator{r1{b1}[,ri{bi}]}
The braces are dropped after evaluationThe brackets represent optional, repeatable
fields.rj – an optional repeat count for the bit fieldbj – bit field representation of a value or
variablebj
Data RepresentationBit Selection
Variable[high bit:low bit]
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Structure of a Verilog ModelModel hierarchy consists of:
ModulesPorts
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Components of a ModuleParametersNetsRegistersPrimitives and InstancesContinuous AssignmentsProcedural BlocksTask/Function definitions
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General Structuremodule <module_name> (<port_list>); module contentendmodule
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Top Level Structuremodule name; module contentendmodule
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Module Invocation• Module may invoke other modules:
– module <module_name_1> (<port_list_1>);– .– . – <module_name_2>
<instance_name> (<port_list_2>);
– .– .– endmodule
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Multiple Modules• module foo;• bar boo (port1, port2);• bar hoo (port1, port2);• endmodule
• module bar (port1, port2);• ...• endmodule
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Declaring Port Directionsmodule foo ( a, b, c ); input a; output b; inout c; …endmodule
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Declaring Port Directionsmodule foo ( input a, output b, inout c ); …endmodule
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Verilog PortsPorts equate to wiresType Data Direction
input parent->child output child->parent inout child<->parent
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Instantiating Portsmodule top; wire x, y, z; feefi fofum( x, y, z ); …endmodule
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Assign Statements
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Combinational Logicmodule half_adder ( A, B, Sum, Carry ) input A, B; // two 1-bit inputs; output Sum, Carry; // two 1-bit outputs assign Sum = A ^ B; // Sum is A xor B assign Carry = A & B; // Carry is A and
Bendmodule
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Common ProblemCreating sequential logic which imply the
existence of a latch or register
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Tips and TechniquesPlace all combinational logic in a continuous
assignment or an always blockMake sure that all the signals used as inputs
appear in the sensitivity list of an always block
Ensure that every path through an always block assigns a value to the exact same set of bits
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ExerciseAssuming all values are initially zero, what
are the values of A and B after executing this Verilog code inside an always block?C = 1;A <= C;B = C;
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AnswerA = 0B = 1
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Sensitivity Lists
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Representing Complex Combinatorial Logic in VerilogSensitivity list
always @(list of signals that cause reevaluation) begin Verilog statements including assignments and other control statementsend
Blocking assignmentsStatements using the = assignment operator
Non-blocking assignmentsStatements using the <= assignment operator
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Sensitivity Listalways @( list of signals that cause
reevaluation) begin Verilog Statements end
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4 to 1 Multiplexor• module Mult4to1(Out , Sel, In1, In2, In3, In4 );• input [31:0] In1, In2, In3, In4;• input [1:0] Sel; // Selector signal• output [31:0] Out;• always @(Sel, In1, In2, In3, In4 )• case (Sel) // a 4 -> 1 multiplexor• 0: Out <= In1;• 1: Out <= In2;• 2: Out <= In3;• default: Out <= In4;• endcase• endmodule
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Basic MIPS ALU• module MIPSALU (ALUOut, Zero, ALUctl, A, B );• input [3:0] ALUctl;• input [31:0] A, B;• output reg [31:0] ALUOut;• output Zero;• assign Zero = (ALUOut==0); // Zero is 1 if ALUOut is 0• always• @( ALUctl, A, B )• case (ALUOut)• 0: ALUOut <= A & B;• 1: ALUOut <= A | B;• 2: ALUOut <= A + B;• 6: ALUOut <= A - B;• 7: ALUOut <= A < B ? 1 : 0;• 12: ALUOut <= ~(A | B); // nor• default: ALUOut <= 0;• endcase• endmodule
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One Bit Adder
a b
cico
z
+
a b ci co z
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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One Bit Adder – Gate Level module OneBitAdder( input a, input b, input ci, output co, output z ); wire na, nb, nci, x0, x1, x2, y0, y1, y2, y3; not #1 ng1( na, a ), ng2( nb, b ), ng3( nci, ci ); and #1 ag1( x0, a, b ), ag2( x1, b, ci ), ag3( x2, a, ci ),
ag4( y0, a, nb, nci ), ag5( y1, na, b, nci ), ag6( y2, na, nb, ci ), ag6( y3, a, b, ci );
or #1 og1( co, x0, x1, x2 ), og2( z, y0, y1, y2, y3 ); endmodule
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ClocksClock PeriodCycle TimeEdge-triggered
Rising EdgeFalling Edge
Level triggeredAssertedDeasserted
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Specifying Sequential Logic in VerilogSpecifying a clock
reg clock; // clock is a registeralways #1 clock = 1; #1 clock = 0;
Using a clockreg [31:0] A;wire [31:0] b;always @(posedge clock) A <= b;
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Clock Module DiscussionA clock signal stays high for some length of
time, HI,Then, it transitions to low and stays there for
some length of time, LO.It is appropriate to use parameters to define
these
HILO
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Clock Modulemodule Clock( clock ); #( parameter LO = 10, HI = 10 ) output reg clock;
initial clock = 0;
always begin #LO clock = ~clock; #HI clock = ~clock; end
endmodule
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Clock Testbenchmodule testClock; wire clock;
Clock c0( clock );
initial begin $monitor( $time,,”clock = %b”,
clock ); #100 $finish; end
endmodule
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Compiling and Executing
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Verilog TutorialChapter 6 - Advanced Features
System Tasks and Functions $readmem
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Reading File DataVerilog supports the following system tasks for
reading files into a model:$readmemx( “file”, <mem>, <<start><,<end>>?>?);
Underscore characters, _, are ignoredEnd of line comments, //, are ignoredPlaces the contents of each value into a different
memory location.Values are white space delimited@hh…h may be used, in the file, to specify the
location of subsequent data.
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Reading File Datawhere
x – isb – binary formatted datah – hexidecimal formatted data
mem – the Verilog Identifier being referenced start – starting address within mem end – ending address within mem
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$readmemh example module read;
reg [31:0] m[0:31]; reg [5:0] i;
initial begin $readmemh( "memory.dat", m ); end
always for( i=0; i<32; i=i+1 ) begin if( m[i] ) $display( "m[%d] = %x", i, m[i] ); else $finish; end
endmodule
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memory.data0123_4567 // comments are ignored89ab_cdef // underscores are ignored@4 dead beef@2 feed babe
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Compile and Execute
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Defining the MIPS ALU in Verilog – Behavioral Definition module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero; assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase end endmodule
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Defining the MIPS ALU in Verilog – Control Definition module ALUControl (FuncCode, ALUCtl); input [5:0] FuncCode; output [3:0] reg ALUCtl; always case (FuncCode) 32: ALUCtl <=2; // add 34: ALUCtl <=6; //subtract 36: ALUCtl <=0; // and 37: ALUCtl <=1; // or 39: ALUCtl <=12; // nor 42: ALUCtl <=7; // slt default: ALUCtl <=15; // should not happen endcase endmodule
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Specifying Sequential Logic in VerilogSpecifying a clock
reg clock; // clock is a registeralways#1 clock = 1; #1 clock = 0;
Using a clockreg [31:0] A;wire [31:0] b;always @(posedge clock) A <= b;
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MIPS Register File:Rising Edge Triggered
module registerfile (Read1,Read2,WriteReg,WriteData,RegWrite,Data1,Data2,clock);
input [5:0] Read1,Read2,WriteReg; // the register numbers to read or write input [31:0] WriteData; // data to write input RegWrite, // the write control clock; // the clock to trigger write output [31:0] Data1, Data2; // the register values read reg [31:0] RF [31:0]; // 32 registers each 32 bits long
assign Data1 = RF[Read1]; assign Data2 = RF[Read2];
always begin // write the register with new value if Regwrite is high @(posedge clock) if (RegWrite) RF[WriteReg] <= WriteData; end
endmodule