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Intelligent Instrumentation(EIC-012)

UNIT-III

A process monitor or control device must have some input and outputs. The inputsand outputs may in the form of analog or digital.

Analog Inputs & Outputs:-

The standard communications protocols have existed for many years; the ranges of 

analog variables are dominated by 4 mA to 20 mA, 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10

V.

The best process control device is PLC and the block diagram is shown in fig 2.1

Figure 2.1. Program Logic Controller

Hardware-configurable input ranges include 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V, 4 mA to

20 mA, 0 mA to 20 mA, ±20 mA, as well as thermocouple and RTD. Software-

 programmable output ranges include 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V, 4 mA to 20mA, 0 mA to 20 mA, and 0 mA to 24 mA.

Figure 2.2 Analog input/output module

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A better solution would be to integrate all of the above on a single IC, such as the

AD5412/AD5422  low-cost, high-precision, 12-/16-bit digital-to-analog converters. They

 provide a solution that offers a fully integrated programmable current source and programmable voltage output designed to meet the requirements of industrial process-

control applications.

Figure 2.3 AD5422 programmable voltage/current output.

The output current range is programmable to 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to24mA over range function. A voltage output, available on a separate pin, can be configured

to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V ranges, with a 10% overrange available

on all ranges. Analog outputs are short-circuit protected, a critical feature in the event of miswired outputs—for example, when the user connects the output to ground instead of to

the load. The AD5422 also has an open-circuit detection feature that monitors the current-

output channel to ensure that no fault has occurred between the output and the load. In the

event of an open circuit, the FAULT pin will go active, alerting the system controller. TheAD5750 programmable current/voltage output driver features both short-circuit detection

and protection.

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Figure 2.4 Output module block level

Figure 2.5 Input module design

Digital Inputs/outputs

Digital inputs and outputs voltage level of a process control system is depends upon CPUinternal structure technology or protocol of the control system. The internal structure

technology means the manufacturing logic family like Resistor–transistor logic (RTL),

Diode–transistor logic (DTL), Emitter-coupled logic (ECL), Positive emitter-coupled logic 

(PECL), Complementary metal–oxide–semiconductor  (CMOS), Integrated injection logic (I2L) and Transistor-transistor logic.

Digital I/O is designed to deal directly with transistor-to-transistor logic (TTL) level

voltage changes. TTL typically sets the low voltage level between 0 and 0.8 V and the highvoltage level between 2.0 and 5.0 V. Voltage levels between 0.8 and 2.0 V are not allowed.

A voltage change, then, from the high range to the low range (or vice versa) represents a

digital change of state from high to low, on to off, etc.And because acquiring an analog signal is more complex than acquiring a digital one,

analog I/O channels also are more expensive. Hence, if digital I/O is adequate, do not

 bother with analog.

Digital Inputs:

Many types of digital input signals from switch closures, relay contacts, or TTL-compatibleinterfaces can be read directly by digital I/O cards (Figure 2-1). Other types of inputs may

require some signal conditioning, most likely to reduce higher-level voltage changes to

TTL levels. A variety of signal conditioning modules are available to provide isolation and

other digital conditioning functions.

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Figure 2.6: Signal Processing Requirementfor Digital and Analog Signals

The most common type of digital input is the contact closure (Figure 2-2).

Essentially a sensor or switch of some type closes or opens a set of contacts in accordancewith some process change. An applied electrical signal then determines whether the circuit

is open or closed. Current flows if the circuit is closed, registering a "1" in a transistor atthe computer interface. Conversely, an open circuit retains a high voltage (and no current),

registering a "0" at the transistor.

Another type of digital input useful in data acquisition applications is the hardware trigger.

This allows an external event-a high reactor temperature, perhaps, or a low tank level-to

control data collection. If during routine operation data is only being acquired for archivalstorage on a once-per-second basis, a hardware trigger can be used to boost the data

acquisition rate during an upset until normal conditions are restored.

Figure 2.7: Digital Input Applied to a Contact Closure

 The list below shows typical ranges for input voltages, and is roughly inorder of popularity for PLC modules.12-24 Vdc100-120 Vac10-60 Vdc

12-24 Vac/dc5 Vdc (TTL)200-240 Vac48 Vdc

24 Vac

Digital Outputs

At its simplest, a digital output provides a means of turning something on or off.

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Applications range from driving a relay to turning on an indicator lamp to transmitting data

to another computer. For latching outputs, a "1" typically causes the associated switch or 

relay to latch, while a "0" causes the switch to unlatch. Devices can be turned on or off,depending on whether the external contacts are normally open or normally closed.

Standard TTL level signals can be used to drive 5-V relay coils; a protective diode is used

to protect the digital output circuitry (Figure 2-3). Because data acquisition boards cantypically supply only 24 mA of driving current, they are intended primarily to drive other 

logic circuits, not final control elements. Scaling may be needed so that logical voltage

levels are sufficient to cause switching in larger relays. Outputs intended to drive larger solenoids, contactors, motors, or alarms also may require a boost. 

Figure 2.8:Digital Output Applied to a Relay

TTL Input & Output Voltage Levels

Ideal Digital Logic Voltage Levels

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Where the opening or closing of the switch produces either a logic level "1" or a logic level

"0" with the resistor R and it is being known as a "pull-up" resistor.

 Typical output voltages are listed below, and roughly ordered bypopularity for PLC.

24 Vdc12-48 Vac12-48 Vdc5Vdc (TTL)

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230 Vac

Counters:-

Mechanical Counters:

Mechanical counters are used to record number of revolutions turned by its axial shaft. So

the display is mechanical based. The best example is counter of electrical energy meter.

The electrical energy meter is worked based induction principle. The most common type of 

electricity meter is the electromechanical induction watt-hour meter.

The electromechanical induction meter operates by counting the revolutions of an

aluminium disc which is made to rotate at a speed proportional to the power. The number 

of revolutions is thus proportional to the energy usage. It consumes a small amount of 

 power, typically around 2 watts.

The metallic disc is acted upon by two coils. One coil is connected in such a way that it produces a magnetic flux in proportion to the voltage and the other produces a magnetic

flux in proportion to the current. The field of the voltage coil is delayed by 90 degreesusing a lag coil. This produces eddy currents in the disc and the effect is such that a force is

exerted on the disc in proportion to the product of the instantaneous current and voltage. A

 permanent magnet exerts an opposing force proportional to the speed of rotation of the

disc. The equilibrium between these two opposing forces results in the disc rotating at aspeed proportional to the power being used.

Electronic Counters

The display is generally a 7 segment display or alpha numeric LC Display. So the input to

the Display must be electrical signal and not mechanical rotations. The electrical signal will

 be in digital form. The voltage level will be in TTL logic family. The sensing signal will bein the form of electric pulses. The counting process of counter is done by a IC chip and not

 by display like mechanical counter. The recording of values may not be there.

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Digital Counters

The digital counters are microprocessor or microcontroller based. In this system also, the

input signal is sensed in terms of pulses. There will recording facility in this system. Inautomation system or software, the software based timers may be used. A microcontroller 

 based counter circuit is shown below.

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Timers

Timers are used to know elapsed time of a process. Timers also classified into three and

they are i) mechanical ii) electronic and ii) Digital. The basic principles also same like

counters but there is no input and it would be from constant source like oscillators for electronic and digital types.

Mechanical Timers

In mechanical timers, there is no need to use any electrical power supply or battery.The power is provided with spiral spring and it is called mainspring. It is used to know

elapsed time of a process. The elapsed time may indicated by mechanical alarm. There may

 be three keys and their purpose is to reset, pause or start and spiral key for power.

Electro-Mechanical Timers

In this type, the power may be electrical mechanical. The elapsed time indicator is

generally electrical relay or electronic relay like normally open or close. The relay may beused to start or stop a process. If it is powered electrically then the motor may be

synchronous motor.

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Electronic Timers

The electronic timer is generally designed with electronic timer IC and relays. Once

it gets a signal to start then it will stop or activate a relay after predetermined time. Thedelay may be done with help of RC components. The basic timer using 555 IC is shown in

fig below. Some electronic modules may included with display device.

 A simple astable timer made with the 555, the mark (on) and space (off) values may be setindependently. The timing chain consists of resistors Ra, Rb and capacitor Ct. The capacitor, Ctcharges via Ra which is in series with the 1N4148 diode. The discharge path is via Rb into pin 7 of the IC. Both halves of the timing period can now be set independently.

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The charge time (output high) is calculated by:

T(on) = 0.7 Ra Ct

The discharge time (output low) is calculated by:

T(off) = 0.7 Rb Ct

Please note that the formula for T(on) ignores the series resistance and forward voltage of the1N4148 and is therefore approximate, but T(off) is not affected by D1 and is therefore precise.

Digital Timers

Digital timers may be built with help of flip-flops or processors or computers. A circuit

diagram using microcontroller for timer application is shown below

PLC are also having in built timer for different application of automation in industry.Timers can be programmed in digital timers like seconds, minutes and hours etc.

Interfacing methods of DAQ

The interfacing methods of DAQ are depends upon the system’s input ports.

Basically there are two types i) serial port and ii) Parallel port. There may be some protocols to access the data through ports. DAQ are used to bring signals of different

sensors to control system.The ports may be simple analog inputs or digital inputs or RS232, RS 423, USB, Parallel

 port etc. The voltage levels will vary depends upon the port. Example: The RS-232 Voltage

levels are +-15 VWe have seen already the different voltage levels of analog and digital inputs.

The computer based ports are explained in UNIT 4 of this subject.

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ADC design

What is a ADC ?

Analog to digital converters (ADC) are utilized broadly in signal processing systems for 

converting analog signals into digital signals. The function of an analog to digital converter 

(ADC) is to accurately convert an analog input signal into a digital output represented by acoded array of binary bits. The output bits are generated by processing the analog input

signal through a number of comparator steps. An ADC receives an analog signal as input

and provides (generates) a digital code corresponding to strength of the analog signal atvarious time instances as output. The number of bits in the generated digital code

represents the resolution of the ADC. A reference signal is often used by an ADC in

 providing such conversions. The digital output signal represents a number that is

 proportional to the current magnitude and/or amplitude of the analog input signal. A/Dconverters are often used with microprocessors to convert an analog signal to a

corresponding digital signal which is processed by the microprocessor. A/D converters of 

the parallel type and the serial and parallel type are advantageous for high speed operation.Such A/D converters generally comprise a plurality of comparators for comparing an

analog input signal with analog reference voltages and an encoder for converting output

signals of the comparators to a multibit digital signal. Multi-stage pipelined analog todigital converters provide efficient high speed conversion of analog signals to digital

equivalents. A/D converters are employed in a wide variety of applications. Many modern

electronic systems require conversion of signals from analog to digital or from digital toanalog form. Circuits for performing these functions are now required in numerous

common consumer devices such as digital cameras, cellular telephones, wireless data

network equipment, audio devices such as MP3 players, and video equipment such as DVD

 players, high definition digital television (HDTV) equipment, and etc. For example, ADCs

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are often used in audio recording equipment to convert analog audio signals into digital

signals that can be stored on digital media. Also, ADCs are usually employed to convert a

received wireless (analog) signal into a digital signal for further processing by other components in a mobile device. Wireless communications products and other modern

electronic devices typically process and generate both digital and analog signals. To

 perform their intended functions, these systems often convert analog signals into digitalsignals.

Digital ramp ADC

Also known as the stairstep-ramp, or simply counter A/D converter, this is also fairly easy

to understand but unfortunately suffers from several limitations.

The basic idea is to connect the output of a free-running binary counter to the inpt of a

DAC, then compare the analog output of the DAC with the analog input signal to be

digitized and use the comparator’s output to tell the counter when to stop counting and

reset. The following schematic shows the basic idea:

As the counter counts up with each clock pulse, the DAC outputs a slightly higher (more

 positive) voltage. This voltage is compared against the input voltage by the comparator. If 

the input voltage is greater than the DAC output, the comparator’s output will be high and

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the counter will continue counting normally. Eventually, though, the DAC output will

exceed the input voltage, causing the comparator’s output to go low. This will cause two

things to happen: first, the high-to-low transition of the comparator’s output will cause theshift register to “load” whatever binary count is being output by the counter, thus updating

the ADC circuit’s output; secondly, the counter will receive a low signal on the active-low

LOAD input, causing it to reset to 00000000 on the next clock pulse.

The effect of this circuit is to produce a DAC output that ramps up to whatever level theanalog input signal is at, output the binary number corresponding to that level, and start

over again. Plotted over time, it looks like this:

 Note how the time between updates (new digital output values) changes depending on howhigh the input voltage is. For low signal levels, the updates are rather close-spaced. For 

higher signal levels, they are spaced further apart in time:

For many ADC applications, this variation in update frequency (sample time) would not be

acceptable. This, and the fact that the circuit’s need to count all the way from 0 at the

 beginning of each count cycle makes for relatively slow sampling of the analog signal, places the digital-ramp ADC at a disadvantage to other counter strategies.

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Successive approximation ADC

One method of addressing the digital ramp ADC’s shortcomings is the so-called

 successive-approximation ADC. The only change in this design is a very special counter circuit known as a successive-approximation register . bit and finishing at the least-

significant bit. Throughout the count process, the register Instead of counting up in binarysequence, this register counts by trying all values of bits starting with the most-significantmonitors the comparator’s output to see if the binary count is less than or greater than the

analog signal input, adjusting the bit values accordingly. The way the register counts is

identical to the “trial-and-fit” method of decimal-to-binary conversion, whereby differentvalues of bits are tried from MSB to LSB to get a binary number that equals the original

decimal number. The advantage to this counting strategy is much faster results: the DAC

output converges on the analog signal input in much larger steps than with the 0-to-full

count sequence of a regular counter.

Without showing the inner workings of the successive-approximation register (SAR), the

circuit looks like this:

It should be noted that the SAR is generally capable of outputting the binary number in

 serial (one bit at a time) format, thus eliminating the need for a shift register. Plotted over time, the operation of a successive-approximation ADC looks like this:

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Tracking ADC

A third variation on the counter-DAC-based converter theme is, in my estimation, the most

elegant. Instead of a regular “up” counter driving the DAC, this circuit uses an up/downcounter. The counter is continuously clocked, and the up/down control line is driven by the

output of the comparator. So, when the analog input signal exceeds the DAC output, the

counter goes into th “count up” mode. When the DAC output exceeds the analog input, thecounter switches into the “count down” mode. Either way, the DAC output always counts

in the proper direction to track the input signal.

 Notice how no shift register is needed to buffer the binary count at the end of a cycle. Since

the counter’s output continuously tracks the input (rather than counting to meet the input

and then resetting back to zero), the binary output is legitimately updated with every clock 

 pulse.

An advantage of this converter circuit is speed, since the counter never has to reset. Note

the behavior of this circuit:

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 Note the much faster update time than any of the other “counting” ADC circuits. Also notehow at the very beginning of the plot where the counter had to “catch up” with the analog

signal, the rate of change for the output was identical to that of the first counting ADC.

Also, with no shift register in this circuit, the binary output would actually ramp up rather than jump from zero to an accurate count as it did with the counter and successive

approximation ADC circuits.

Perhaps the greatest drawback to this ADC design is the fact that the binary output is never 

stable: it always switches between counts with every clock pulse, even with a perfectlystable analog input signal. This phenomenon is informally known as bit bobble, and it can

 be problematic in some digital systems.

This tendency can be overcome, though, through the creative use of a shift register. For 

example, the counter’s output may be latched through a parallel-in/parallel-out shiftregister only when the output changes by two or more steps. Building a circuit to detect

two or more successive counts in the same direction takes a little ingenuity, but is worth the

effort.

Slope (integrating) ADC

So far, we’ve only been able to escape the sheer volume of components in the flash

converter by using a DAC as part of our ADC circuitry. However, this is not our only

option. It is possible to avoid using a DAC if we substitute an analog ramping circuit and adigital counter with precise timing.

The is the basic idea behind the so-called single-slope, or integrating ADC. Instead of 

using a DAC with a ramped output, we use an op-amp circuit called an integrator to

generate a sawtooth waveform which is then compared against the analog input by acomparator. The time it takes for the sawtooth waveform to exceed the input signal voltage

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level is measured by means of a digital counter clocked with a precise-frequency square

wave (usually from a crystal oscillator). The basic schematic diagram is shown here:

The IGFET capacitor-discharging transistor scheme shown here is a bit oversimplified. Inreality, a latching circuit timed with the clock signal would most likely have to beconnected to the IGFET gate to ensure full discharge of the capacitor when the

comparator’s output goes high. The basic idea, however, is evident in this diagram. When

the comparator output is low (input voltage greater than integrator output), the integrator isallowed to charge the capacitor in a linear fashion. Meanwhile, the counter is counting up

at a rate fixed by the precision clock frequency. The time it takes for the capacitor to charge

up to the same voltage level as the input depends on the input signal level and thecombination of -Vref , R, and C. When the capacitor reaches that voltage level, the

comparator output goes high, loading the counter’s output into the shift register for a final

output. The IGFET is triggered “on” by the comparator’s high output, discharging the

capacitor back to zero volts. When the integrator output voltage falls to zero, thecomparator output switches back to a low state, clearing the counter and enabling the

integrator to ramp up voltage again.

This ADC circuit behaves very uch like the digital ramp ADC, except that the comparator reference voltage is a smooth sawtooth waveform rather than a “stairstep:”

The single-slope ADC suffers all the disadvantages of the digital ramp ADC, with the

added drawback of calibration drift . The accurate correspondence of this ADC’s output

with its input is dependent on the voltage slope of the integrator being matched to thecounting rate of the counter (the clock frequency). With the digital ramp ADC, the clock 

frequency had no effect on conversion accuracy, only on update time. In this circuit, since

the rate of integration and the rate of count are independent of each other, variation between the two is inevitable as it ages, and will result in a loss of accuracy. The only good

thing to say about this circuit is that it avoids the use of a DAC, which reduces circuit

complexity.

An answer to this calibration drift dilemma is found in a design variation called the dual- slope converter. In the dual-slope converter, an integrator circuit is driven positive and

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negative in alternating cycles to ramp down and then up, rather than being reset to 0 volts

at the end of every cycle. In one direction of ramping, the integrator is driven by the

 positive analog input signal (producing a negative, variable rate of output voltage change,or output slope) for a fixed amount of time, as measured by a counter with a precision

frequency clock. Then, in the other direction, with a fixed reference voltage (producing a

fixed rate of output voltage change) with time measured by the same counter. The counter stops counting when the integrator’s output reaches the same voltage as it was when it

started the fixed-time portion of the cycle. The amount of time it takes for the integrator’s

capacitor to discharge back to its original output voltage, as measured by the magnitudeaccrued by the counter, becomes the digital output of the ADC circuit.

The dual-slope method can be thought of analogously in terms of a rotary spring such as

that used in a mechanical clock mechanism. Imagine we were building a mechanism to

measure the rotary speed of a shaft. Thus, shaft speed is our “input signal” to be measured by this device. The measurement cycle begins with the spring in a relaxed state. The spring

is then turned, or “wound up,” by the rotating shaft (input signal) for a fixed amount of 

time. This places the spring in a certain amount of tension proportional to the shaft speed: agreater shaft speed corresponds to a faster rate of winding. and a greater amount of spring

tension accumulated over that period of time. After that, the spring is uncoupled from the

shaft and allowed to unwind at a fixed rate, the time for it to unwind back to a relaxed state

measured by a timer device. The amount of time it takes for the spring to unwind at thatfixed rate will be directly proportional to the speed at which it was wound (input signal

magnitude) during the fixed-time portion of the cycle.

This technique of analog-to-digital conversion escapes the calibration drift problem of the

single-slope ADC because both the integrator’s integration coefficient (or “gain”) and thecounter’s rate of speed are in effect during the entire “winding” and “unwinding” cycle

 portions. If the counter’s clock speed were to suddenly increase, this would shorten thefixed time period where the integrator “winds up” (resulting in a lesser voltageaccumulated by the integrator), but it would also mean that it would count faster during the

 period of time when the integrator was allowed to “unwind” at a fixed rate. The proportion

that the counter is counting faster will be the same proportion as the integrator’saccumulated voltage is diminished from before the clock speed change. Thus, the clock 

speed error would cancel itself out and the digital output would be exactly what it should

 be.

Another important advantage of this method is that the input signal becomes averaged as itdrives the inegrator during the fixed-time portion of the cycle. Any changes in the analog

signal during that period of time have a cumulative effect on the digital output at the end of 

that cycle. Other ADC strategies merely “capture” the analog signal level at a single pointin time every cycle. If the analog signal is “noisy” (contains significant levels of spurious

voltage spikes/dips), one of the other ADC converter technologies may occasionally

convert a spike or dip because it captures the signal repeatedly at a single point in time. A

dual-slope ADC, on the other hand, averages together all the spikes and dips within theintegration period, thus providing an output with greater noise immunity. Dual-slope ADCs

are used in applications demanding high accuracy.

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line into the noninverting input of the last comparator. This last comparator, seeing an input

voltage greater than the threshold voltage of 1/2 +V, saturates in a positive direction,

sending a full +V signal to the other input of the integrator. This +V feedback signal tendsto drive the integrator output in a negative direction. If that output voltage ever becomes

negative, the feedback loop will send a corrective signal (-V) back around to the top input

of the integrator to drive it in a positive direction. This is the delta-sigma concept in action:the first comparator senses a difference (Δ) between the integrator output and zero volts.

The integrator  sums (Σ) the comparator’s output with the analog input signal.

Functionally, this results in a serial stream of bits output by the flip-flop. If the analog input

is zero volts, the integrator will have no tendency to ramp either positive or negative,except in response to the feedback voltage. In this scenario, the flip-flop output will

continually oscillate between “high” and “low,” as the feedback system “hunts” back and

forth, trying to maintain the integrator output at zero volts:

If, however, we apply a negative analog input voltage, the integrator will have a tendency

to ramp its output in positive direction. Feedback can only add to the integrator’s ramping by a fixed voltage over a fixed time, and so the bit stream output by the flip-flop will not be

quite the same:

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By applying a larger (negative) analog input signal to the integrator, we force its output toramp more steeply in the positive direction. Thus, the feedback system has to output more

1′s than before to bring the integrator output back to zero volts:

As the analog input signal increases in magnitude, so does the occurrence of 1′s in the

digital output of the flip-flop:

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A parallel binary number output is obtained from this circuit by averaging the serial streamof bits together. For example, a counter circuit could be designed to collect the total

number of 1′s output by the flip-flop in a given number of clock pulses. This count wouldthen be indicative of the analog input voltage.

Variations on this theme exist, employing multiple integrator stages and/or comparator circuits outputting more than 1 bit, but one concept common to all ΔΣ converters is that of 

oversampling . Oversampling is when multiple samples of an analog signal are taken by an

ADC (in this case, a 1-bit ADC), and those digitized samples are averaged. The end result

is an effective increase in the number of bits resolved from the signal. In other words, anoversampled 1-bit ADC can do the same job as an 8-bit ADC with one-time sampling,

albeit at a slower rate.

Flash ADC

Also called the parallel A/D converter, this circuit is the simplest to understand. It is

formed of a series of comparators, each one comparing the input signal to a unique

reference voltage. The comparator outputs connect to the inputs of a priority encoder 

circuit, which then produces a binary output. The following illustration shows a 3-bit flashADC circuit:

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Vref  is a stable reference voltage provided by a precision voltage regulator as part of the

converter circuit, not shown in the schematic. As the analog input voltage exceeds thereference voltage at each comparator, the comparator outputs will sequentially saturate to a

high state. The priority encoder generates a binary number based on the highest-order 

active input, ignoring all other active inputs.

When operated, the flash ADC produces an output that looks something like this:

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For this particular application, a regular priority encoder with all its inherent complexityisn’t necessary. Due to the nature of the sequential comparator otput states (each

comparator saturating “high” in sequence from lowest to highest), the same “highest-order-

input selection” effect may be realized through a set of Exclusive-OR gates, allowing theuse of a simpler, non-priority encoder:

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And, of course, the encoder circuit itself can be made from a matrix of diodes,

demonstrating just how simply this converter design may be constructed:

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 Not only is the flash converter the simplest in terms of operational theory, but it is the most

efficient of the ADC technologies in terms of speed, being limited only in comparator andgate propagation delays. Unfortunately, it is the most component-intensive for any given

number of output bits. This three-bit flash ADC requires eight comparators. A four-bit

version would require 16 comparators. With each additional output bit, the number of required comparators doubles. Considering that eight bits is generally considered the

minimum necessary for any practical ADC (256 comparators needed!), the flash

methodology quickly shows its weakness.

An additional advantage of the flash converter, often overlooked, is the ability for it to

 produce a non-linear output. With equal-value resistors in the reference voltage divider network, each successive binary count represents the same amount of analog signal

increase, providing a proportional response. For special applications, however, the resistor values in the divider network may be made non-equal. This gives the ADC a custom,

nonlinear response to the analog input signal. No other ADC design is able to grant this

signal-conditioning behavior with just a few component value changes.

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Practical considerations of ADC circuits

Perhaps the most important consideration of an ADC is its resolution. Resolution is the

number of binary bits output by the converter. Because ADC circuits take in an analogsignal, which is continuously variable, and resolve it into one of many discrete steps, it is

important to know how many of these steps there are in total.

For example, an ADC with a 10-bit output can represent up to 1024 (210) unique conditions

of signal measurement. Over the range of measurement from 0% to 100%, there will beexactly 1024 unique binary numbers output by the converter (from 0000000000 to

1111111111, inclusive). An 11-bit ADC will have twice as many states to its output (2048,

or 211), representing twice as many unique conditions of signal measurement between 0%and 100%.

Resolution is very important in data acquisition systems (circuits designed to interpret and

record physical measurements in electronic form). Suppose we were measuring the height

of water in a 40-foot tall storage tank using an instrument with a 10-bit ADC. 0 feet of water in the tank corresponds to 0% of measurement, while 40 feet of water in the tank 

corresponds to 100% of measurement. Because the ADC is fixed at 10 bits of binary data

output, it will interpret any given tank level as one out of 1024 possible states. Todetermine how much physical water level will be represented in each step of the ADC, we

need to divide the 40 feet of measurement span by the number of steps in the 0-to-1024

range of possibilities, which is 1023 (one less than 1024). Doing this, we obtain a figure of 0.039101 feet per step. This equates to 0.46921 inches per step, a little less than half an

inch of water level represented for every binary count of the ADC.

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This step value of 0.039101 feet (0.46921 inches) represents the smallest amount of tank 

level change detectable by the instrument. Admittedly, this is a small amount, less than

0.1% of the overall measurement span of 40 feet. However, for some applications it maynot be fine enough. Suppose we needed this instrument to be able to indicate tank level

changes down to one-tenth of an inch. In order to achieve this degree of resolution and still

maintain a measurement span of 40 feet, we would need an instrument with more than tenADC bits.

To determine how man ADC bits are necessary, we need to first determine how many 1/10

inch steps there are in 40 feet. The answer to this is 40/(0.1/12), or 4800 1/10 inch steps in

40 feet. Thus, we need enough bits to provide at least 4800 discrete steps in a binarycounting sequence. 10 bits gave us 1023 steps, and we knew this by calculating 2 to the

 power of 10 (210 = 1024) and then subtracting one. Following the same mathematical

 procedure, 211-1 = 2047, 212-1 = 4095, and 213-1 = 8191. 12 bits falls shy of the amountneeded for 4800 steps, while 13 bits is more than enough. Therefore, we need an

instrument with at least 13 bits of resolution.

Another important consideration of ADC circuitry is its sample frequency, or conversion

rate. This is simply the speed at which the converter outputs a new binary number. Likeresolution, this consideration is linked to the specific application of the ADC. If the

converter is being used to measure slow-changing signals such as level in a water storage

tank, it could probably have a very slow sample frequency and still perform adequately.Conversely, if it is being used to digitize an audio frequency signal cycling at several

thousand times per second, the converter needs to be considerably faster.

Consider the following illustration of ADC conversion rate versus signal type, typical of a

successive-approximation ADC with regular sample intervals:

Here, for this slow-changing signal, the sample rate is more than adequate to capture itsgeneral trend. But consider this example with the same sample time:

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When the sample period is too long (too slow), substantial details of the analog signal will be missed. Notice how, especially in the latter portions of the analog signal, the digital

output utterly fails to reproduce the true shape. Even in the first section of the analogwaveform, the digital reproduction deviates substantially from the true shape of the wave.

It is imperative that an ADC’s sample time is fast enough to capture essential changes in

the analog waveform. In data acquisition terminology, the highest-frequency waveform thatan ADC can theoretically capture is the so-called Nyquist frequency, equal to one-half of 

the ADC’s sample frequency. Therefore, if an ADC circuit has a sample frequency of 5000

Hz, the highest-frequency waveform it can successfully resolve will be the Nyquist

frequency of 2500 Hz.

If an ADC is subjected to an analog input signal whose frequency exceeds the Nyquist

frequency for that ADC, the converter will output a digitized signal of falsely low

frequency. This phenomenon is known as aliasing . Observe the following illustration to see

how aliasing occurs:

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 Note how the period of the output waveform is much longer (slower) than that of the inputwaveform, and how the two waveform shapes aren’t even similar:

It should be understood that the Nyquist frequency is an absolute maximum frequency

limit for an ADC, and does not represent the highest practical frequency measurable. To besafe, one shouldn’t expect an ADC to successfully resolve any frequency greater than one-fifth to one-tenth of its sample frequency.

A practical means of preventing aliasing is to place a low-pass filter before the input of the

ADC, to block any signal frequencies greater than the practical limit. This way, the ADC

circuitry will be prevented from seeing any excessive frequencies and thus will not try to

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digitize them. It is generally considered better that such frequencies go unconverted than to

have them be “aliased” and appear in the output as false signals.

Yet another measure of ADC performance is something called step recovery. This is ameasure of how quickly an ADC changes its output to match a large, sudden change in the

nalog input. In some converter technologies especially, step recovery is a seriouslimitation. One example is the tracking converter, which has a typically fast update period

 but a disproportionately slow step recovery.

An ideal ADC has a great many bits for very fine resolution, samples at lightning-fast

speeds, and recovers from steps instantly. It also, unfortunately, doesn’t exist in the real

world. Of course, any of these traits may be improved through additional circuitcomplexity, either in terms of increased component count and/or special circuit designs

made to run at higher clock speeds. Different ADC technologies, though, have different

strengths. Here is a summary of them ranked from best to worst:

Software Structure

There are different types of software are used for industrial automation. The softwares mayclassify as general software and dedicated software. The general softwares are used to

manage the database as well as to control a process. Example: C, C++, Java, .NET etc

The general software are used to design PC based instrumentation system. It may not usefor high number of inputs and outputs. The below program is microcontroller program

using C coding. This program can be written using assemble language also. The gives more

advantages.

#include <reg51.h> /* define 8051 registers */

#include <stdio.h> /* define I/O functions */

extern unsigned int getnumber (void);

extern void output (unsigned int);

void main (void) { /* main program */

unsigned int number1, number2; /* define operation registers */

bit operation; /* define operation */

SCON = 0x52; /* SCON */ /* setup serial port control */

TMOD = 0x20; /* TMOD */ /* hardware (2400 BAUD @12MHZ) */

TCON = 0x69; /* TCON */TH1 = 0xf3; /* TH1 */

printf ("\n\nC compiler demonstration program\n\n");

while (1) { /* repeat forever */

number1 = getnumber (); /* read number1 */number2 = getnumber (); /* read number2 */

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printf ("Input operation: '+' (ADD) or '-' (SUB) ? ");

operation = (getchar () == '+'); /* get operation */

output (operation ? (number1 + number2) /* perform operation */: (number1 - number2) );

}

}

The dedicated software are used to control the process only like PLC software, SCADA,

DCS etc. This can handle large number of inputs and outputs. The ladder program of PLCis shown below.

Example 3:

Put a value in memory location vw200, and using shifting method, move this value to theoutput of the PLC.

 Solution:

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when we press the PLC input button (I0.0), the PLC will put the value (980) inside memorylocation vw200, and when the rising edge of the pulse arrives, the contents of memory

location will be shifted to the left for one bit (the instruction SLW = shift left word). we

could put 2 after # to shift two bits to left. If we put 7 after the #, the overflow indicator 

will be activated (SM1.1=1) which will activate the output in question.

here is the ladder diagram:

 

 Example 4:

Using two timers, write a program so we have a pulse on PLC output with (TON = 10 sec.)

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and (TOFF = 10 sec.)

*TON: timer output on, TOFF: timer output off. 

 Solution:

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Data Sockets

A socket is a software endpoint that establishes bidirectional communication between a

server program and one or more client programs. The socket associates the server program

with a specific hardware port on the machine where it runs so any client program anywhere

in the network with a socket associated with that same port can communicate with theserver program.

A server program typically provides resources to a network of client programs. Client

 programs send requests to the server program, and the server program responds to the

request.

In computer networking, an Internet socket or network socket is an endpoint of a

 bidirectional inter-process communication flow across an Internet Protocol-based computer 

network , such as the Internet.

The term Internet sockets is also used as a name for an application programming interface(API) for the TCP/IP protocol stack, usually provided by the operating system. Internet

sockets constitute a mechanism for delivering incoming data packets to the appropriate

application process or thread, based on a combination of local and remote IP addresses and

 port numbers. Each socket is mapped by the operating system to a communicatingapplication process or thread.

A socket address is the combination of an IP address (the location of the computer) and a

 port (which is mapped to the application program process) into a single identity, much likeone end of a telephone connection is the combination of a phone number and a particular 

extension.

An Internet socket is characterized by a unique combination of the following:

• Local socket address: Local IP address and port number 

• Remote socket address: Only for established TCP sockets. As discussed in theClient-Server section below, this is necessary since a TCP server may serve several

clients concurrently. The server creates one socket for each client, and these sockets

share the same local socket address.

• Protocol: A transport protocol (e.g., TCP, UDP), raw IP, or others. TCP port 53 and

UDP port 53 are consequently different, distinct sockets.

Within the operating system and the application that created a socket, the socket is referred

to by a unique integer number called socket identifier or  socket number . The operatingsystem forwards the payload of incoming IP packets to the corresponding application by

extracting the socket address information from the IP and transport protocol headers and

stripping the headers from the application data.

In IETF Request for Comments, Internet Standards, in many textbooks, as well as in thisarticle, the term socket refers to an entity that is uniquely identified by the socket number.

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In other textbooks[1], the socket term refers to a local socket address, i.e. a "combination of 

an IP address and a port number". In the original definition of  socket given in RFC 147, as

it was related to the ARPA network in 1971, "the socket is specified as a 32 bit number with even sockets identifying receiving sockets and odd sockets identifying sending 

 sockets." Today, however, socket communications are bidirectional.

On Unix-like and Microsoft Windows based operating systems the netstat command line

tool may be used to list all currently established sockets and related information.

There are several Internet socket types available:

• Datagram sockets, also known as connectionless sockets, which use User Datagram

Protocol (UDP)

• Stream sockets, also known as connection-oriented sockets, which useTransmission Control Protocol (TCP) or Stream Control Transmission Protocol 

(SCTP).

•

Raw sockets (or  Raw IP sockets), typically available in routers and other network equipment. Here the transport layer is bypassed, and the packet headers are not

stripped off, but are accessible to the application. Application examples are Internet

Control Message Protocol (ICMP, best known for the Ping suboperation), Internet

Group Management Protocol (IGMP), and Open Shortest Path First (OSPF).

There are also non-Internet sockets, implemented over other transport protocols, such as

Systems Network Architecture (SNA).[3] See also Unix domain sockets (UDS), for internal

inter-process communication.

Development of application programs that utilize this API is called socket programming or 

network programming.

These are examples of functions or methods typically provided by the API library:

• socket() creates a new socket of a certain socket type, identified by an integer 

number, and allocates system resources to it.

•  bind() is typically used on the server side, and associates a socket with a socket

address structure, i.e. a specified local port number and IP address.

• listen() is used on the server side, and causes a bound TCP socket to enter listening

state.

• connect() is used on the client side, and assigns a free local port number to a socket.

In case of a TCP socket, it causes an attempt to establish a new TCP connection.• accept() is used on the server side. It accepts a received incoming attempt to create

a new TCP connection from the remote client, and creates a new socket associated

with the socket address pair of this connection.

• send() and recv(), or write() and read(), or recvfrom() and sendto(), are used for sending and receiving data to/from a remote socket.

• close() causes the system to release resources allocated to a socket. In case of TCP,

the connection is terminated.

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• gethostbyname() and gethostbyaddr() are used to resolve host names and addresses.

• select() is used to prune a provided list of sockets for those that are ready to read,

ready to write or have errors

•  poll() is used to check on the state of a socket. The socket can be tested to see if it

can be written to, read from or has errors.

In computer networking, a raw socket is a socket that allows direct sending and receiving

of network  packets by applications, bypassing all encapsulation in the networking softwareof the operating system.

Most socket application programming interfaces (APIs), especially those based on

Berkeley sockets, support raw sockets.

Usually raw sockets receive packets inclusive of the header, as opposed to standard socketswhich receive just the packet payload without headers. When transmitting packets, the

automatic addition of a header may be a configurable option of the socket.

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Reference:

http://www.analog.com/library/analogDialogue/archives/43-04/process_control.html

  References and Further Reading

  The Data Acquisition Systems Handbook, Omega Press LLC, 1997.

  New Horizons in Data Acquisition and Computer Interfaces, Omega Press LLC, 1997.

  Omega® Universal Guide to Data Acquisition and Computer Interfaces, Omega Press LLC, 1997.

   Automation Systems for Control and Data Acquisition, Lawrence T. Amy, ISA, 1992.

Data Acquisition and Control, Microcomputer Applications for Scientists and Engineers, Joseph J. Carr,Tab Books Inc., 1988.

  Data Acquisition and Process Control Using Personal Computers, Tarik Ozkul, Marcel Dekker, 1996.

 Instrument Engineers' Handbook, Third Edition, Bela Liptak, Chilton Book Co., 1995.

Process/Industrial Instruments & Controls Handbook, Fourth Edition, Douglas M. Considine, McGraw-Hill Inc., 1993.

http://www.omega.com/literature/transactions/

http://www.electronics-tutorials.ws

http://en.wikipedia.org/wiki/Electricity_meter http://www.interfacebus.com/voltage_threshold.html

http://en.wikipedia.org/wiki/Clock 

http://www.piclist.com/images/www/hobby_elec/e_counter1.htm

http://www.8085projects.info/post/Digital-timer-with-LED-display-using-8051-microcontroller.aspx

http://en.wikipedia.org/wiki/Analog-to-digital_converter 1.The scientist and engineer's guide to digital signal processing,Second Edition,Prentice

Hall,1999

2.Horowitz P.,Hill W., The art of electronics , Second edition,1997,Cambridge

3.Websites: www.analog.com , www.national.com , www.maxim.com , www.intersil.com

http://www.rficdesign.com/types-of-adc

http://www.automation.com/resources-tools/evaluation-software/data-acquisition-

measurementhttp://www.plcmanual.com/programming-examples-ii