Intel FPGA SDK for OpenCL Programming Guide · 1.7.2 Allocating OpenCL Buffer for Manual...

Intel FPGA SDK for OpenCLProgramming Guide

UG-OCL0022016.10.31

Last updated for Quartus Prime Design Suite: 16.1

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Contents

1 Intel FPGA SDK for OpenCL Programming Guide..............................................................51.1 Intel FPGA SDK for OpenCL Programming Guide Prerequisites...................................... 51.2 Intel FPGA SDK for OpenCL FPGA Programming Flow...................................................61.3 Intel FPGA SDK for OpenCL Offline Compiler Kernel Compilation Flows...........................7

1.3.1 One-Step Compilation for Simple Kernels....................................................... 81.3.2 Multistep Intel FPGA SDK for OpenCL Design Flow...........................................9

1.4 Obtaining General Information on Software, Compiler, and Custom Platform................. 121.4.1 Displaying the Software Version (version).................................................... 121.4.2 Displaying the Compiler Version (--version).................................................. 121.4.3 Listing the Intel FPGA SDK for OpenCL Utility Command Options (help)............131.4.4 Listing the Intel FPGA SDK for OpenCL Offline Compiler Command Options

(no argument, --help, or -h)......................................................................131.4.5 Listing the Available FPGA Boards in Your Custom Platform (--list-boards)........ 131.4.6 Displaying the Compilation Environment of an OpenCL Binary (env).................14

1.5 Managing an FPGA Board....................................................................................... 141.5.1 Installing an FPGA Board (install)................................................................151.5.2 Uninstalling the FPGA Board (uninstall)........................................................ 171.5.3 Querying the Device Name of Your FPGA Board (diagnose)............................. 171.5.4 Running a Board Diagnostic Test (diagnose <device_name>)..........................181.5.5 Programming the FPGA Offline or without a Host (program <device_name>).... 181.5.6 Programming the Flash Memory (flash <device_name>)................................ 18

1.6 Structuring Your OpenCL Kernel..............................................................................191.6.1 Guidelines for Naming the Kernel................................................................ 201.6.2 Programming Strategies for Optimizing Data Processing Efficiency...................201.6.3 Programming Strategies for Optimizing Memory Access Efficiency....................231.6.4 Implementing the Intel FPGA SDK for OpenCL Channels Extension.................. 241.6.5 Implementing OpenCL Pipes.......................................................................421.6.6 Using Predefined Preprocessor Macros in Conditional Compilation.................... 581.6.7 Declaring __constant Address Space Qualifiers............................................. 591.6.8 Including Structure Data Types as Arguments in OpenCL Kernels.....................601.6.9 Inferring a Register................................................................................... 631.6.10 Enabling Double Precision Floating-Point Operations.....................................651.6.11 Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels............ 65

1.7 Designing Your Host Application..............................................................................681.7.1 Host Programming Requirements................................................................ 681.7.2 Allocating OpenCL Buffer for Manual Partitioning of Global Memory.................. 691.7.3 Collecting Profile Data During Kernel Execution............................................. 721.7.4 Accessing Custom Platform-Specific Functions...............................................741.7.5 Modifying Host Program for Structure Parameter Conversion...........................751.7.6 Managing Host Application......................................................................... 761.7.7 Allocating Shared Memory for OpenCL Kernels Targeting SoCs........................ 87

1.8 Compiling Your OpenCL Kernel................................................................................891.8.1 Compiling Your Kernel to Create Hardware Configuration File.......................... 891.8.2 Compiling Your Kernel without Building Hardware (-c)....................................901.8.3 Specifying the Location of Header Files (-I <directory>).................................901.8.4 Specifying the Name of an Intel FPGA SDK for OpenCL Offline Compiler

Output File (-o <filename>)...................................................................... 91

Contents

Intel FPGA SDK for OpenCL Programming Guide2

1.8.5 Compiling a Kernel for a Specific FPGA Board (--board <board_name>)........... 911.8.6 Resolving Hardware Generation Fitting Errors during Kernel Compilation (--

high-effort)............................................................................................. 931.8.7 Defining Preprocessor Macros to Specify Kernel Parameters (-D

<macro_name>)..................................................................................... 931.8.8 Generating Compilation Progress Report (-v)................................................ 951.8.9 Displaying the Estimated Resource Usage Summary On-Screen (--report)........ 961.8.10 Suppressing Warning Messages from the Intel FPGA SDK for OpenCL

Offline Compiler (-W)............................................................................... 961.8.11 Converting Warning Messages from the Intel FPGA SDK for OpenCL

Offline Compiler into Error Messages (-Werror)............................................ 961.8.12 Removing Debug Data from Compiler Reports and Source Code from

the .aocx File (-g0).................................................................................. 971.8.13 Disabling Burst-Interleaving of Global Memory (--no-interleaving

<global_memory_type>).......................................................................... 971.8.14 Configuring Constant Memory Cache Size (--const-cache-bytes <N>)............ 981.8.15 Relaxing the Order of Floating-Point Operations (--fp-relaxed).......................981.8.16 Reducing Floating-Point Rounding Operations (--fpc)....................................99

1.9 Emulating and Debugging Your OpenCL Kernel..........................................................991.9.1 Modifying Channels Kernel Code for Emulation............................................ 1001.9.2 Compiling a Kernel for Emulation (-march=emulator)...................................1011.9.3 Emulating Your OpenCL Kernel..................................................................1031.9.4 Debugging Your OpenCL Kernel on Linux.................................................... 1041.9.5 Limitations of the Intel FPGA SDK for OpenCL Emulator................................105

1.10 Reviewing Your Kernel's report.html File............................................................... 1061.11 Profiling Your OpenCL Kernel...............................................................................106

1.11.1 Instrumenting the Kernel Pipeline with Performance Counters (--profile)....... 1071.11.2 Launching the Intel FPGA SDK for OpenCL Profiler GUI (report)................... 107

1.12 Conclusion........................................................................................................1071.13 Document Revision History................................................................................. 108

2 Intel FPGA SDK for OpenCL Advanced Features........................................................... 1142.1 OpenCL Library...................................................................................................114

2.1.1 Understanding RTL Modules and the OpenCL Pipeline................................... 1162.1.2 Packaging an OpenCL Helper Function File for an OpenCL Library...................1252.1.3 Packaging an RTL Component for an OpenCL Library ...................................1252.1.4 Verifying the RTL Modules........................................................................ 1282.1.5 Packaging Multiple Object Files into a Library File.........................................1292.1.6 Specifying an OpenCL Library when Compiling an OpenCL Kernel...................1292.1.7 Using an OpenCL Library that Works with Simple Functions (Example 1).........1302.1.8 Using an OpenCL Library that Works with External Memory (Example 2).........1312.1.9 OpenCL Library Command-Line Options......................................................132

2.2 Kernel Attributes for Configuring Local Memory System............................................1332.2.1 Restrictions on the Usage of Local Variable-Specific Kernel Attributes............. 134

2.3 Kernel Attributes for Reducing the Overhead on Hardware Usage...............................1352.3.1 Hardware for Kernel Interface................................................................... 135

2.4 Kernel Replication Using the num_compute_units(X,Y,Z) Attribute............................. 1382.4.1 Customization of Replicated Kernels Using the get_compute_id() Function...... 1392.4.2 Using Channels with Kernel Copies............................................................ 140

2.5 Document Revision History...................................................................................141

Contents


A Support Statuses of OpenCL Features ......................................................................... 142A.1 Support Statuses of OpenCL 1.0 Features...............................................................142

A.1.1 OpenCL1.0 C Programming Language Implementation................................. 142A.1.2 OpenCL C Programming Language Restrictions............................................144A.1.3 Argument Types for Built-in Geometric Functions.........................................145A.1.4 Numerical Compliance Implementation...................................................... 146A.1.5 Image Addressing and Filtering Implementation.......................................... 146A.1.6 Atomic Functions.................................................................................... 146A.1.7 Embedded Profile Implementation............................................................. 147

A.2 Support Statuses of OpenCL 1.2 Features...............................................................147A.2.1 OpenCL 1.2 Runtime Implementation.........................................................147A.2.2 OpenCL 1.2 C Programming Language Implementation................................ 148

A.3 Support Statuses of OpenCL 2.0 Features...............................................................149A.3.1 OpenCL 2.0 Headers................................................................................149A.3.2 OpenCL 2.0 Runtime Implementation.........................................................149A.3.3 OpenCL 2.0 C Programming Language Restrictions for Pipes......................... 149

A.4 Intel FPGA SDK for OpenCL Allocation Limits...........................................................150A.5 Document Revision History...................................................................................151

Contents


1 Intel FPGA SDK for OpenCL Programming GuideThe Intel® FPGA SDK for OpenCL™ Programming Guide provides descriptions,recommendations and usage information on the Intel Software Development Kit (SDK)for OpenCL compiler and tools. The Intel FPGA SDK for OpenCL1 is an OpenCL2-basedheterogeneous parallel programming environment for Intel FPGA products.

1.1 Intel FPGA SDK for OpenCL Programming Guide Prerequisites

The Intel FPGA SDK for OpenCL Programming Guide assumes that you areknowledgeable in OpenCL concepts and application programming interfaces (APIs). Italso assumes that you have experience creating OpenCL applications and are familiarwith the OpenCL Specification version 1.0.

Before using the Intel FPGA SDK for OpenCL or the Intel FPGA Runtime Environment(RTE) for OpenCL to program your device, familiarize yourself with the respectivegetting started guides. This document assumes that you have performed the followingtasks:

• For developing and deploying OpenCL kernels, download the tar file and run theinstallers to install the SDK, the Quartus® Prime software, and device support.

• For deployment of OpenCL kernels, download and install the RTE.

• If you want to use the SDK or the RTE to program a Cyclone® V SoC DevelopmentKit, you also have to download and install the SoC Embedded Design Suite (EDS).

• Install and set up your FPGA board.

• Program your device with the device-compatible version of the hello_worldexample OpenCL application

If you have not performed the tasks described above, refer to the SDK's gettingstarting guides for more information.

Prior to creating an OpenCL design and programming your FPGA board, review theIntel FPGA SDK for OpenCL allocation limits.

Related Links

• Intel FPGA SDK for OpenCL Allocation Limits on page 150

• OpenCL References Pages

1 The Intel FPGA SDK for OpenCL is based on a published Khronos Specification, and has passedthe Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.

2 OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of the KhronosGroup™.

1 Intel FPGA SDK for OpenCL Programming Guide

© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX,Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/orother countries. Other marks and brands may be claimed as the property of others. Intel warrants performanceof its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty,but reserves the right to make changes to any products and services at any time without notice. Intel assumesno responsibility or liability arising out of the application or use of any information, product, or servicedescribed herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain thelatest version of device specifications before relying on any published information and before placing orders forproducts or services.

ISO9001:2008Registered

http://www.khronos.org/registry/cl/sdk/1.0/docs/man/xhtml/

https://www.khronos.org/conformance/

http://www.altera.com/support/devices/reliability/certifications/rel-certifications.html



• OpenCL Specification version 1.0

• Intel FPGA SDK for OpenCL Getting Started Guide

• Intel FPGA RTE for OpenCL Getting Started Guide

• Intel FPGA SDK for OpenCL Cyclone V SoC Getting Started Guide

1.2 Intel FPGA SDK for OpenCL FPGA Programming Flow

The Intel FPGA SDK for OpenCL programs an FPGA with an OpenCL application in atwo-step process. The Intel FPGA SDK for OpenCL Offline Compiler first compiles yourOpenCL kernels. The host-side C compiler compiles your host application and thenlinks the compiled OpenCL kernels to it.

Figure 1. Schematic Diagram of the Intel FPGA SDK for OpenCL Programming Model

Intel FPGA for OpenCLRuntime Environment

Host compiler

Host source code(.c or .cpp)

Host binary

SDK Offline Compiler

Kernel source code(.cl)

FPGA image (.aocx)

Execute hostapplication

on host

Quartus PrimeDesign Suite

Board-specificCustom Platform Design

Port and/orcustomize to

targetplatform

SDK’s board directoryfor version-compatible

target platform

Final computationresults

Runtime Execution

Host Code Path Kernel Code Path Custom Platform Path

Board developer-created item SDK user-created item Intel-supplied tool or design Board developer-supplied item

Third-party-supplied or open source tool Tool-generated item Process or action

Intel FPGA SDK for OpenCL Reference Platform Design

Three main parts in the SDK's programming model:

• The host application and the host compiler

• The OpenCL kernel and the offline compiler

• The Custom Platform

The Custom Platform provides the board design. The offline compiler targets the boarddesign when compiling the OpenCL kernel to generate the hardware image. The hostthen runs the host application to execute the hardware image onto the FPGA.



http://www.khronos.org/registry/cl/specs/opencl-1.0.pdf

https://documentation.altera.com/#/link/mwh1391807309901/mwh1391807297091/en-us

https://documentation.altera.com/#/link/mwh1391808173911/ewa1401738888275/en-us

https://documentation.altera.com/#/link/ewa1400875619714/ewa1400875828418/en-us

1.3 Intel FPGA SDK for OpenCL Offline Compiler Kernel CompilationFlows

The Intel FPGA SDK for OpenCL Offline Compiler can create your FPGA hardwareconfiguration file in a one-step or a multistep process. The complexity of your kerneldictates the compilation option you implement.

Figure 2. The Intel FPGA SDK for OpenCL FPGA Programming Flow

Kernel SourceCode #2 (.cl)



Host Binary

StandardC Compiler

Host Code

Offline Compiler forOpenCL Kernels

Kernel Binary A(.aocx)

Load .aocx into memory

PCIe

PCIe

Load runtime

Load runtime

Consolidated Kernel Binary A(.aoco, .aocx)




Consolidated Kernel Binary B(.aoco, .aocx)

Kernel Binary B(.aocx)

Offline Compiler forOpenCL Kernels

An OpenCL kernel source file (.cl) contains your OpenCL source code. The offlinecompiler groups one or more kernels into a temporary file and then compiles this fileto generate the following files and folders:



• A .aoco object file is an intermediate object file that contains information for laterstages of the compilation.

• A.aocx executable file is the hardware configuration file and contains informationnecessary at runtime.

• The <your_kernel_filename> folder or subdirectory, which contains datanecessary to create the .aocx file.

The offline compiler creates the .aocx file from the contents of the<your_kernel_filename> folder or subdirectory. It also incorporates information fromthe .aoco file into the .aocx file during hardware compilation. The .aocx filecontains data that the host application uses to create program objects for the targetFPGA. The host application loads these program objects into memory. The hostruntime then calls these program objects from memory and programs the target FPGAas required.

1.3.1 One-Step Compilation for Simple Kernels

By default, the Intel FPGA SDK for OpenCL Offline Compiler compiles your OpenCLkernel and creates the hardware configuration file in a single step. Choose thiscompilation option only if your OpenCL application requires minimal optimizations.

The following figure illustrates the OpenCL kernel design flow that has a singlecompilation step.

Figure 3. One-Step OpenCL Kernel Compilation Flow

<your_kernel_filename>.cl

aoc <your_kernel_filename>.cl [--report]Duration of compilation: hours

<your_kernel_filename>.aocxEstimated resource usage summaryin <your_kernel_filename>.log

(and on-screen with --report)

Optimization report in<your_kernel_filename>.log

SyntacticErrors?

Resource usageacceptable?

Singlework-item kernel

performancesatisfactory?

Execute onFPGA

LegendFile abc Command Kernel Execution abc For single work-item kernel

NO

YES

NO

NO

<your_kernel_filename>.aoco

YESYES

A successful compilation results in the following files and reports:



• A .aoco file

• A .aocx file

• In the <your_kernel_filename>/<your_kernel_filename>.log file, theestimated resource usage summary provides a preliminary assessment of areausage. If you have a single work-item kernel, the optimization report identifiesperformance bottlenecks.

Attention: It is very time consuming to iterate on your design using the one-step compilationflow. For each iteration, you must perform a full compilation, which takes hours. Thenyou must execute the kernel on the FPGA before you can assess its performance.

Related Links

Compiling Your Kernel to Create Hardware Configuration File on page 89You can compile an OpenCL kernel and create the hardware configuration file (thatis, the .aocx file) in a single step.

1.3.2 Multistep Intel FPGA SDK for OpenCL Design Flow

Choose the multistep Intel FPGA SDK for OpenCL design flow if you want to iterate onyour OpenCL kernel design to implement performance-improving optimizations .

The figure below outlines the stages in the SDK's design flow. The steps in the designflow serve as checkpoints for identifying functional errors and performancebottlenecks. They allow you to modify your OpenCL kernel code without performing afull compilation after each iteration.



Figure 4. The Multistep Intel FPGA SDK for OpenCL Design Flow

<your_kernel_filename>.aocx

<your_kernel_filename>.cl

aoc -c <your_kernel_filename> .cl [--report]Duration of compilation: minutes

Syntacticerrors?

aoc -march=emulator <your_kernel_filename> .clDuration of compilation: seconds

Emulationsuccessful?

Optimization Repot in<your_kernel_filename>.log

aoc --profile <your_kernel_filename>.clDuration of compilation: hours

profile.mon

aocl report <your_kernel_filename>.aocx profile.mon

ProfilerGUI

aoc <your_kernel_filename>.clDuration of compilation: hours

Execute kernelon FPGA

Kernelperformancesatisfactory?

Intermediate Compilation

Emulation

Profiling

Full Deployment

Execute kernelon FPGA

YESNO

NO

YES

<your_kernel_filename>.aocx

NO

YES

Legend

abcFileCommandKernel ExecutionGUI


<your_kernel_filename>.aocxExecute onemulation device

<your_kernel_filename>/reports/report.html

Review HTML Report


Estimated resource usage summaryin <your_kernel_filename>.log

(and on-screen with --report)

ResourceUsage

Acceptable?

NO YES

Kernelperformancesatisfactory?

Estimated kernelperformance data

acceptable?

Singlework-item

kernel?

NO

YES

YES

NO

NO

YES

abc Single work-item kernel step



The SDK's design flow includes the following steps:

1. Intermediate compilation

The intermediate compilation step checks for syntatic errors. It then generatesa .aoco file without building the hardware configuration file. The estimatedresource usage summary in the <your_kernel_filename>/<your_kernel_filename>.log file can provide insight into the type of kerneloptimizations you can perform. .

2. Emulation

Assess the functionality of your OpenCL kernel by executing it on one or multipleemulation devices on an x86-64 host. For Linux systems, the Emulator offerssymbolic debug support. Symbolic debug allows you to locate the origins offunctional errors in your kernel code.

3. Review HTML Report

Review the <your_kernel_filename>/reports/report.html file of yourOpenCL application to determine whether the estimated kernel performace data isacceptable. The HTML report also provides suggestions on how you can modifyyour kernel to increase performance.

4. Profiling

Instruct the Intel FPGA SDK for OpenCL Offline Compiler to instrumentperformance counters in the Verilog code in the .aocx file. During execution, theperformance counters collect performance information which you can then reviewin the Profiler GUI.

5. Full deployment

If you are satisfied with the performance of your OpenCL kernel throughout thedesign flow, perform a full compilation. You can then execute the .aocx file on theFPGA.

Related Links

• Reviewing Your Kernel's report.html File on page 106To launch the HTML report, open the report.html file in the<your_kernel_filename>/reports directory.

• Compiling Your OpenCL Kernel on page 89The Intel FPGA SDK for OpenCL offers a list of compiler options that allows youto customize the kernel compilation process.

• Emulating and Debugging Your OpenCL Kernel on page 99The Intel FPGA SDK for OpenCL Emulator assesses the functionality of yourkernel.

• Profiling Your OpenCL Kernel on page 106The Intel FPGA SDK for OpenCL Profiler measures and reports performancedata collected during OpenCL kernel execution on the FPGA.



1.4 Obtaining General Information on Software, Compiler, andCustom Platform

The Intel FPGA SDK for OpenCL includes two sets of command options: the SDK utilitycommands (aocl <command_option>) and the offline compiler commands (aoc<command_option>). Each set of commands includes options you can invoke toobtain general information on the software, the compiler, and the Custom Platform.

Displaying the Software Version (version) on page 12To display the version of the Intel FPGA SDK for OpenCL, invoke the versionutility command.

Displaying the Compiler Version (--version) on page 12To display the version of the Intel FPGA SDK for OpenCL Offline Compiler, invokethe --version compiler command.

Listing the Intel FPGA SDK for OpenCL Utility Command Options (help) on page 13To display information on the Intel FPGA SDK for OpenCL utility command options,invoke the help utility command.

Listing the Intel FPGA SDK for OpenCL Offline Compiler Command Options (noargument, --help, or -h) on page 13

To display information on the Intel FPGA SDK for OpenCL Offline Compilercommand options, invoke the compiler command without an argument, or invokethe compiler command with the --help or -h command option.

Listing the Available FPGA Boards in Your Custom Platform (--list-boards) on page 13To list the FPGA boards available in your Custom Platform, include the --list-boards option in the aoc command.

Displaying the Compilation Environment of an OpenCL Binary (env) on page 14To display the Intel FPGA SDK for OpenCL Offline Compiler's input arguments andthe environment for a compiled OpenCL design, invoke the env utility command.

1.4.1 Displaying the Software Version (version)

To display the version of the Intel FPGA SDK for OpenCL, invoke the version utilitycommand.

• At the command prompt, invoke the aocl version command.Example output:

aocl <version>.<build> (Intel(R) FPGA SDK for OpenCL(TM),Version <version> Build <build>, Copyright (C) <year> IntelCorporation)

1.4.2 Displaying the Compiler Version (--version)

To display the version of the Intel FPGA SDK for OpenCL Offline Compiler, invoke the--version compiler command.

• At a command prompt, invoke the aoc --version command.Example output:

Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline CompilerVersion <version> Build <build>Copyright (C) <year> Intel Corporation



1.4.3 Listing the Intel FPGA SDK for OpenCL Utility Command Options(help)

To display information on the Intel FPGA SDK for OpenCL utility command options,invoke the help utility command.

• At a command prompt, invoke the aocl help command.The SDK categorizes the utility command options based on their functions. It alsoprovides a description for each option.

1.4.3.1 Displaying Information on an Intel FPGA SDK for OpenCL UtilityCommand Option (help <command_option>)

To display information on a specific Intel FPGA SDK for OpenCL utility commandoption, include the command option as an argument of the help utility command.

• At a command prompt, invoke the aocl help <command_option> command.

For example, to obtain more information on the install utility command option,invoke the aocl help install command.

Example output:

aocl install - Installs a board onto your host system.

Usage: aocl install

Description:This command installs a board's drivers and other necessary software for the host operating system to communicate with the board.For example this might install PCIe drivers.

1.4.4 Listing the Intel FPGA SDK for OpenCL Offline Compiler CommandOptions (no argument, --help, or -h)

To display information on the Intel FPGA SDK for OpenCL Offline Compiler commandoptions, invoke the compiler command without an argument, or invoke the compilercommand with the --help or -h command option.

• At a command prompt, invoke one of the following commands:

— aoc

— aoc --help

— aoc -h

The SDK categorizes the offline compiler command options based on theirfunctions. It also provides a description for each option.

1.4.5 Listing the Available FPGA Boards in Your Custom Platform (--list-boards)

To list the FPGA boards available in your Custom Platform, include the --list-boards option in the aoc command.



To view the list of available boards in your Custom Platform, you must first set theenvironment variable AOCL_BOARD_PACKAGE_ROOT to point to the location of yourCustom Platform.

• At a command prompt, invoke the aoc --list-boards command.

The Intel FPGA SDK for OpenCL Offline Compiler generates an output thatresembles the following:

Board list: <board_name_1> <board_name_2>...

Where <board_name_N> is the board name you use in your aoc command totarget a specific FPGA board.

1.4.6 Displaying the Compilation Environment of an OpenCL Binary (env)

To display the Intel FPGA SDK for OpenCL Offline Compiler's input arguments and theenvironment for a compiled OpenCL design, invoke the env utility command.

• At the command prompt, invoke the aocl env <object_file_name> or theaocl env <executable_file_name> command,

where <object_file_name> is the name of the .aoco file of your OpenCL kernel,and the <executable_file_name> is the name of the .aocx file of your kernel.

Output for the example command aocl env vector_add.aocx:

INPUT_ARGS=-march=emulator -v device/vector_add.cl -o bin/vector_add.aocxBUILD_NUMBER=90ACL_VERSION=16.1.0OPERATING_SYSTEM=linuxPLATFORM_TYPE=s5_net

1.5 Managing an FPGA Board

The Intel FPGA SDK for OpenCL includes utility commands you can invoke to install,uninstall, diagnose, and program your FPGA board.

You can install multiple Custom Platforms simultaneously on the same system. To usethe SDK utilities, such as aocl diagnose with multiple Custom Platforms, you mustset the AOCL_BOARD_PACKAGE_ROOT environment variable to point to the locationof the Custom Platform subdirectory of the board on which you wish to run the utility.The Custom Platform subdirectory contains the board_env.xml file. To run the SDKutilities on a different Custom Platform, you must update theAOCL_BOARD_PACKAGE_ROOT environment variable to point to the location of theCustom Platform subdirectory of that specific board.

In a system with multiple Custom Platforms, ensure that the host program uses theAltera Client Driver (ACD) to discover the boards rather than linking to the CustomPlatforms' memory-mapped device (MMD) libraries directly. As long as ACD is correctlyset up for Custom Platform, ACD will find all the installed boards at runtime.

Installing an FPGA Board (install) on page 15To install your board into the host system, invoke the install utility command.



Uninstalling the FPGA Board (uninstall) on page 17To uninstall an FPGA board, invoke the uninstall utility command, uninstall theCustom Platform, and unset the relevant environment variables.

Querying the Device Name of Your FPGA Board (diagnose) on page 17When you query a list of accelerator boards, the OpenCL software produces a list ofinstalled devices on your machine in the order of their device names.

Running a Board Diagnostic Test (diagnose <device_name>) on page 18To perform a detailed diagnosis on a specific FPGA board, include <device_name>as an argument of the diagnose utility command.

Programming the FPGA Offline or without a Host (program <device_name>) on page18

To program an FPGA device offline or without a host, invoke the program utilitycommand.

Programming the Flash Memory (flash <device_name>) on page 18If supported, invoke the flash utility command to initialize the FPGA with aspecified startup configuration.

Related Links

• Installing an FPGA Board (install) on page 15To install your board into the host system, invoke the install utilitycommand.

• Linking Your Host Application to the Khronos ICD Loader Library on page 80The Intel FPGA SDK for OpenCL supports the OpenCL ICD extension from theKhronos Group.

1.5.1 Installing an FPGA Board (install)

Before creating an OpenCL application for an FPGA board, you must first downloadand install the Custom Platform from your board vendor. Most Custom Platforminstallers require administrator privileges. To install your board into the host system,invoke the install utility command.

The steps below outline the board installation procedure. Some Custom Platformsrequire additional installation tasks. Consult your board vendor's documentation forfurther information on board installation.

Attention: If you are installing the Cyclone V SoC Development Kit for use with the Cyclone VSoC Development Kit Reference Platform (c5soc), refer to Installing the Cyclone V SoCDevelopment Kit in the Intel FPGA SDK for OpenCL Cyclone V SoC Getting StartedGuide for more information.

1. Follow your board vendor's instructions to connect the FPGA board to your system.

2. Download the Custom Platform for your FPGA board from your board vendor'swebsite. To download an Intel FPGA SDK for OpenCL Reference Platform (forexample, the Stratix® V Network Reference Platform (s5_net)), refer to the IntelFPGA SDK for OpenCL FPGA Platforms page on the Altera website.

3. Install the Custom Platform in a directory that you own (that is, not a systemdirectory).

4. Set the user environment variable AOCL_BOARD_PACKAGE_ROOT to point to thelocation of the Custom Platform subdirectory containing the board_env.xml file.



For example, for s5_net, set AOCL_BOARD_PACKAGE_ROOT to point to the<path_to_s5_net>/s5_net directory.

5. Set the QUARTUS_ROOTDIR_OVERRIDE user environment variable to point to thecorrect Quartus Prime software installation directory.

If you have an Arria® 10 device, set QUARTUS_ROOTDIR_OVERRIDE to point tothe installation directory of the Quartus Prime Pro Edition software. Otherwise, setQUARTUS_ROOTDIR_OVERRIDE to point to the installation directory of theQuartus Prime Standard Edition software.

6. Add the paths to the Custom Platform libraries (for example, the memory-mapped(MMD) library) to the PATH (Windows) or LD_LIBRARY_PATH (Linux) environmentvariable setting.

For example, if you use s5_net, the Windows PATH environment variable setting is%AOCL_BOARD_PACKAGE_ROOT%\windows64\bin. The Linux LD_LIBRARY_PATHsetting is $AOCL_BOARD_PACKAGE_ROOT/linux64/lib.

The Intel FPGA SDK for OpenCL Getting Started Guide contains more informationon the init_opencl script. For information on setting user environment variablesand running the init_opencl script, refer to the Setting the Intel FPGA SDK forOpenCL User Environment Variables section.

7. Remember: You need administrative rights to install a board. To run a Windowscommand prompt as an administrator, click Start ➤ All Programs ➤Accessories. Under Accessories, right click Command Prompt, Inthe right-click menu, click Run as Administrator.

Invoke the command aocl install at a command prompt.

Invoking aocl install also installs a board driver that allows communicationbetween host applications and hardware kernel programs.

8. To query a list of FPGA devices installed in your machine, invoke the aocldiagnose command.The software generates an output that includes the <device_name>, which is anacl number that ranges from acl0 to acl31.

For more information on querying the <device_name> of your accelerator board,refer to the Querying the Device Name of Your FPGA Board section.

9. To verify the successful installation of the FPGA board, invoke the command aocldiagnose <device_name> to run any board vendor-recommended diagnostictest.

Related Links

• Installing the Cyclone V SoC Development Kit

• Querying the Device Name of Your FPGA Board (diagnose) on page 17When you query a list of accelerator boards, the OpenCL software produces alist of installed devices on your machine in the order of their device names.

• Setting the Intel FPGA SDK for OpenCL User Environment Variables (Windows)

• Setting the Intel FPGA SDK for OpenCL User Environment Variables (Linux)

• Intel FPGA SDK for OpenCL FPGA Platforms page






https://www.altera.com/products/design-software/embedded-software-developers/opencl/developer-zone.html#fpgaplatforms

1.5.2 Uninstalling the FPGA Board (uninstall)

To uninstall an FPGA board, invoke the uninstall utility command, uninstall theCustom Platform, and unset the relevant environment variables. You must uninstallthe existing FPGA board if you migrate your OpenCL application to another FPGAboard that belongs to a different Custom Platform.

To uninstall your FPGA board, perform the following tasks:

1. Following your board vendor's instructions to disconnect the board from yourmachine.

2. Invoke the aocl uninstall utility command to remove the current hostcomputer drivers (for example, PCIe® drivers). The Intel FPGA SDK for OpenCLuses these drivers to communicate with the FPGA board.

3. Uninstall the Custom Platform.

4. Unset the LD_LIBRARY_PATH (for Linux) or PATH (for Windows) environmentvariable.

5. Unset the AOCL_BOARD_PACKAGE_ROOT environment variable.

1.5.3 Querying the Device Name of Your FPGA Board (diagnose)

Some OpenCL software utility commands require you to specify the device name(<device_name>). The <device_name> refers to the acl number (e.g. acl0 to acl31)that corresponds to the FPGA device. When you query a list of accelerator boards, theOpenCL software produces a list of installed devices on your machine in the order oftheir device names.

• To query a list of installed devices on your machine, type aocl diagnose at acommand prompt.The software generates an output that resembles the example shown below:

aocl diagnose: Running diagnostic from ALTERAOCLSDKROOT/board/<board_name>/<platform>/libexec

Verified that the kernel mode driver is installed on the host machine.

Using board package from vendor: <board_vendor_name>Querying information for all supported devices that are installed on the host machine ...

device_name Status Information

acl0 Passed <descriptive_board_name> PCIe dev_id = <device_ID>, bus:slot.func = 02:00.00, at Gen 2 with 8 lanes. FPGA temperature=43.0 degrees C.

acl1 Passed <descriptive_board_name> PCIe dev_id = <device_ID>, bus:slot.func = 03:00.00, at Gen 2 with 8 lanes. FPGA temperature = 35.0 degrees C.

Found 2 active device(s) installed on the host machine, to perform a full diagnostic on a specific device, please run aocl diagnose <device_name>

DIAGNOSTIC_PASSED



Related Links

Probing the OpenCL FPGA Devices on page 84The host must identify the number of OpenCL FPGA devices installed into thesystem.

1.5.4 Running a Board Diagnostic Test (diagnose <device_name>)

To perform a detailed diagnosis on a specific FPGA board, include <device_name> asan argument of the diagnose utility command.

• At a command prompt, invoke the aocl diagnose <device_name>command, where <device_name> is the acl number (for example, acl0 to acl31)that corresponds to your FPGA device.

You can identify the <device_name> when you query the list of installed boards inyour system.

Consult your board vendor's documentation for more board-specific information onusing the diagnose utility command to run diagnostic tests on multiple FPGA boards.

1.5.5 Programming the FPGA Offline or without a Host (program<device_name>)

To program an FPGA device offline or without a host, invoke the program utilitycommand.

• At a command prompt, invoke the aocl program <device_name><your_kernel_filename>.aocx command

where:

<device_name> refers to the acl number (for example, acl0 to acl31) thatcorresponds to your FPGA device, and

<your_kernel_filename>.aocx is the executable file you use to program thehardware.

Note: To program an SoC such as the Cyclone V SoC, you must specify the full path of thedevice when invoking the program utility command. For example, aoclprogram /dev/<device_name> <your_kernel_filename>.aocx.

1.5.6 Programming the Flash Memory (flash <device_name>)

If supported, invoke the flash utility command to initialize the FPGA with a specifiedstartup configuration.

Note: For instructions on programming the micro SD flash card of the Cyclone V SoCDevelopment Kit, refer to the Writing an SD Card Image onto the Micro SD Flash Cardsection of the Intel FPGA SDK for OpenCL Cyclone V SoC Getting Started Guide.



• At a command prompt, invoke the aocl flash <device_name><your_kernel_filename>.aocx command

where:

<device_name> refers to the acl number (for example, acl0 to acl31) thatcorresponds to your FPGA device, and

<your_kernel_filename>.aocx is the executable file you use to program thehardware.

Related Links

• Writing an SD Card Image onto the Micro SD Flash Card on Windows

• Writing an SD Card Image onto the Micro SD Flash Card on Linux

1.6 Structuring Your OpenCL Kernel

Intel offers recommendations on how to structure your OpenCL kernel code. Considerimplementing these programming recommendations when you create a kernel ormodify a kernel written originally to target another architecture.

Guidelines for Naming the Kernel on page 20Intel recommends that you include only alphanumeric characters in your filenames.

Programming Strategies for Optimizing Data Processing Efficiency on page 20Optimize the data processing efficiency of your kernel by implementing strategiessuch as unrolling loops, setting work-group sizes, and specifying compute units andwork-items.

Programming Strategies for Optimizing Memory Access Efficiency on page 23Optimize the memory access efficiency of your kernel by implementing strategiessuch as specifying local memory pointer size and specifying global memory bufferlocation.

Implementing the Intel FPGA SDK for OpenCL Channels Extension on page 24The Intel FPGA SDK for OpenCL channels extension provides a mechanism forpassing data to kernels and synchronizing kernels with high efficiency and lowlatency.

Implementing OpenCL Pipes on page 42The Intel FPGA SDK for OpenCL provides preliminary support for OpenCL pipefunctions.

Using Predefined Preprocessor Macros in Conditional Compilation on page 58You may take advantage of predefined preprocessor macros that allow you toconditionally compile portions of your kernel code.

Declaring __constant Address Space Qualifiers on page 59There are several limitations and workarounds you must consider when you include__constant address space qualifiers in your kernel.

Including Structure Data Types as Arguments in OpenCL Kernels on page 60Convert each structure parameter (struct) to a pointer that points to a structure.

Inferring a Register on page 63In general, the offline compiler chooses registers if the access to a variable is fixedand does not require any dynamic indexes.

Enabling Double Precision Floating-Point Operations on page 65





The Intel FPGA SDK for OpenCL offers preliminary support for all double precisionfloating-point functions.

Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels on page 65Single work-item kernels that perform accumulation in a loop can leverage theIntel FPGA SDK for OpenCL Offline Compiler's single-cycle floating-pointaccumulator feature.

1.6.1 Guidelines for Naming the Kernel

Intel recommends that you include only alphanumeric characters in your file names.

• Begin a file name with an alphanumeric character.

If the file name of your OpenCL application begins with a nonalphanumericcharacter, compilation fails with the following error message:

Error: Quartus compilation FAILEDSee quartus_sh_compile.log for the output log.

• Do not differentiate file names using nonalphanumeric characters.

The Intel FPGA SDK for OpenCL Offline Compiler translates any nonalphanumericcharacter into an underscore ("_"). If you differentiate two file names by endingthem with different nonalphanumeric characters only (for example,myKernel#.cl and myKernel&.cl), the offline compiler translates both filenames to <your_kernel_filename>_.cl (for example, myKernel_.cl).

• For Windows system, ensure that the combined length of the kernel file name andits file path does not exceed 260 characters.

64-bit Windows 7 and Windows 8.1 has a 260-character limit on the length of afile path. If the combined length of the kernel file name and its file path exceeds260 characters, the offline compiler generates the following error message:

The filename or extension is too long.The system cannot find the path specified.

In addition to the compiler error message, the following error message appears inthe <your_kernel_filename>/quartus_sh_compile.log file:Error: Can’t copy <file_type> files: Can’t open<your_kernel_filename> for write: No such file or directory

For Windows 10, you have the option to to remove the 260-character limit. Formore information, refer to Microsoft's documentation.

• Do not name your .cl OpenCL kernel source file "kernel". Naming the source filekernel.cl causes the offline compiler to generate intermediate design files thathave the same names as certain internal files, which leads to an compilation error.

1.6.2 Programming Strategies for Optimizing Data Processing Efficiency

Optimize the data processing efficiency of your kernel by implementing strategies suchas unrolling loops, setting work-group sizes, and specifying compute units and work-items.



1.6.2.1 Unrolling a Loop

The Intel FPGA SDK for OpenCL Offline Compiler might unroll simple loops even if theyare not annotated by a pragma.To direct the offline compiler to unroll a loop, insert an unroll kernel pragma in thekernel code preceding a loop you wish to unroll.

Attention:

• Provide an unroll factor whenever possible. To specify an unroll factor N, insert the#pragma unroll <N> directive before a loop in your kernel code.

The offline compiler attempts to unroll the loop at most <N> times.

Consider the code fragment below. By assigning a value of 2 as an argument to#pragma unroll, you direct the offline compiler to unroll the loop twice.

#pragma unroll 2for(size_t k = 0; k < 4; k++){ mac += data_in[(gid * 4) + k] * coeff[k];}

• To unroll a loop fully, you may omit the unroll factor by simply inserting the#pragma unroll directive before a loop in your kernel code.

The offline compiler attempts to unroll the loop fully if it understands the tripcount. The offline compiler issues a warning if it cannot execute the unroll request.

1.6.2.2 Specifying Work-Group Sizes

Specify a maximum or required work-group size whenever possible. The Intel FPGASDK for OpenCL Offline Compiler relies on this specification to optimize hardwareusage of the OpenCL kernel without involving excess logic.

If you do not specify a max_work_group_size or a reqd_work_group_sizeattribute in your kernel, the work-group size assumes a default value depending oncompilation time and runtime constraints.

• If your kernel contains a barrier, the offline compiler sets a default maximumwork-group size of 256 work-items.

• If your kernel contains a barrier or refers to the local work-item ID, or if you querythe work-group size in your host code, the runtime defaults the work-group size toone work-item.

• If your kernel does not contain a barrier or refer to the local work-item ID, or ifyour host code does not query the work-group size, the runtime defaults the work-group size to the global NDRange size.

To specify the work-group size, modify your kernel code in the following manner:



• To specify the maximum number of work-items that the offline compiler mayallocate to a work-group in a kernel, insert the max_work_group_size(N)attribute in your kernel source code.

For example:

__attribute__((max_work_group_size(512)))__kernel void sum (__global const float * restrict a, __global const float * restrict b, __global float * restrict answer){ size_t gid = get_global_id(0); answer[gid] = a[gid] + b[gid];}

• To specify the required number of work-items that the offline compiler allocates toa work-group in a kernel, insert the reqd_work_group_size(X, Y, Z)attribute to your kernel source code.

For example:

__attribute__((reqd_work_group_size(64,1,1)))__kernel void sum (__global const float * restrict a, __global const float * restrict b, __global float * restrict answer){ size_t gid = get_global_id(0); answer[gid] = a[gid] + b[gid];}

The offline compiler allocates the exact amount of hardware resources to managethe work-items in a work-group.

1.6.2.3 Specifying Number of Compute Units

To increase the data-processing efficiency of an OpenCL kernel, you can instruct theIntel FPGA SDK for OpenCL Offline Compiler to generate multiple kernel computeunits. Each compute unit is capable of executing multiple work-groups simultaneously.

Caution: Multiplying the number of kernel compute units increases data throughput at theexpense of global memory bandwidth contention among compute units.

• To specify the number of compute units for a kernel, insert thenum_compute_units(N) attribute in the kernel source code.

For example, the code fragment below directs the offline compiler to instantiatetwo compute units in a kernel:

__attribute__((num_compute_units(2)))__kernel void test(__global const float * restrict a, __global const float * restrict b, __global float * restrict answer){ size_t gid = get_global_id(0); answer[gid] = a[gid] + b[gid];}

The offline compiler distributes work-groups across the specified number ofcompute units.



1.6.2.4 Specifying Number of SIMD Work-Items

To increase the data-processing efficiency of an OpenCL kernel, specify the number ofwork-items within a work-group that the Intel FPGA SDK for OpenCL Offline Compilerexecutes in a single instruction multiple data (SIMD) manner.

Important: Introduce the num_simd_work_items attribute in conjunction with thereqd_work_group_size attribute. The num_simd_work_items attribute youspecify must evenly divide the work-group size you specify for thereqd_work_group_size attribute.

• To specify the number of SIMD work-items in a work-group, insert thenum_simd_work_item(N) attribute in the kernel source code.

For example, the code fragment below assigns a fixed work-group size of 64 work-items to a kernel. It then consolidates the work-items within each work-group intofour SIMD vector lanes:

__attribute__((num_simd_work_items(4)))__attribute__((reqd_work_group_size(64,1,1)))__kernel void test(__global const float * restrict a, __global const float * restrict b, __global float * restrict answer){ size_t gid = get_global_id(0); answer[gid] = a[gid] + b[gid];}

The offline compiler replicates the kernel datapath according to the value youspecify for num_simd_work_items whenever possible.

1.6.3 Programming Strategies for Optimizing Memory Access Efficiency

Optimize the memory access efficiency of your kernel by implementing strategies suchas specifying local memory pointer size and specifying global memory buffer location.

1.6.3.1 Specifying Pointer Size in Local Memory

Optimize local memory hardware footprint (that is, size) by specifying a pointer size inbytes.

• To specify a pointer size other than the default size of 16 kilobytes (kB), includethe local_mem_size(N) attribute in the pointer declaration within your kernelsource code.

For example:

__kernel void myLocalMemoryPointer( __local float * A, __attribute__((local_mem_size(1024))) __local float * B, __attribute__((local_mem_size(32768))) __local float * C){ //statements}

In the myLocalMemoryPointer kernel, 16 kB of local memory (default) isallocated to pointer A, 1 kB is allocated to pointer B, and 32 kB is allocated topointer C.



1.6.3.2 Specifying Buffer Location in Global Memory

Specify the global memory type to which the host allocates a buffer.

1. Determine the names of the global memory types available on your FPGA board inthe following manners:

— Refer to the board vendor's documentation for more information.

— Find the names in the board_spec.xml file of your board Custom Platform.For each global memory type, the name is the unique string assigned to thename attribute of the global_mem element.

2. To instruct the host to allocate a buffer to a specific global memory type, insertthe buffer_location("<memory_type>") attribute, where <memory_type>is the name of the global memory type provided by your board vendor.

For example:

__kernel void foo(__global __attribute__((buffer_location("DDR"))) int *x, __global __attribute__((buffer_location("QDR"))) int *y)

If you do not specify the buffer_location attribute, the host allocates thebuffer to the default memory type automatically. To determine the default memorytype, consult the documentation provided by your board vendor. Alternatively, inthe board_spec.xml file of your Custom Platform, search for the memory typethat is defined first or has the attribute default=1 assigned to it.

Intel recommends that you define the buffer_location attribute in a preprocessormacro for ease of reuse, as shown below:

#define QDR\ __global\ __attribute__((buffer_location("QDR")))

#define DDR\ __global\ __attribute__((buffer_location("DDR")))

__kernel void foo (QDR uint * data, DDR uint * lup){ //statements}

Attention: If you assign a kernel argument to a non-default memory (for example, QDR uint *data and DDR uint * lup from the code above), you cannot declare that argumentusing the const keyword. In addition, you cannot perform atomic operations withpointers derived from that argument.

1.6.4 Implementing the Intel FPGA SDK for OpenCL Channels Extension

The Intel FPGA SDK for OpenCL channels extension provides a mechanism for passingdata to kernels and synchronizing kernels with high efficiency and low latency.

Attention: If you want to leverage the capabilities of channels but have the ability to run yourkernel program using other SDKs, implement OpenCL pipes instead.



Related Links

Implementing OpenCL Pipes on page 42The Intel FPGA SDK for OpenCL provides preliminary support for OpenCL pipefunctions.

1.6.4.1 Overview of the Intel FPGA SDK for OpenCL Channels Extension

The Intel FPGA SDK for OpenCL channels extension allows kernels to communicatedirectly with each other via FIFO buffers.

Implementation of channels decouples kernel execution from the host processor.Unlike the typical OpenCL execution model, the host does not need to coordinate datamovement across kernels.

Figure 5. Overview of Channels Implementation

FIFOFIFO

FIFOKernel 0

Kernel 1

Kernel 2

FIFOKernel N FIFO

RAM

I/O Channel

Host Processor

Initialize ( )

I/O Channel

FIFO

1.6.4.2 Channel Data Behavior

Data written to a channel remains in a channel as long as the kernel program remainsloaded on the FPGA device. In other words, data written to a channel persists acrossmultiple work-groups and NDRange invocations. However, data is not persistent acrossmultiple or different invocations of kernel programs.

Consider the following code example:

#pragma OPENCL EXTENSION cl_altera_channels : enablechannel int c0;

__kernel void producer(){ for(int i=0; i < 10; i++) { write_channel_altera(c0, i); }}

__kernel void consumer( __global uint * restrict dst ){ for(int i=0; i < 5; i++)



{ dst[i] = read_channel_altera(c0); }}

Figure 6. Channel Data FIFO Ordering

9 012345678Producer Consumer

The kernel producer writes ten elements ([0, 9]) to the channel. The kernelconsumer reads five elements from the channel per NDRange invocation. During thefirst invocation, the kernel consumer reads values 0 to 4 from the channel. Becausethe data persists across NDRange invocations, the second time you execute the kernelconsumer, it reads values 5 to 9.

For this example, to avoid a deadlock from occurring, you need to invoke the kernelconsumer twice for every invocation of the kernel producer. If you call consumerless than twice, producer stalls because the channel becomes full. If you callconsumer more than twice, consumer stalls because there is insufficient data in thechannel.

1.6.4.3 Multiple Work-Item Ordering for Channels

The OpenCL specification does not define a work-item ordering. The Intel FPGA SDKfor OpenCL enforces a work-item order to maintain the consistency in channel readand write operations.

Multiple work-item accesses to a channel can be useful in some scenarios. Forexample, they are useful when data words in the channel are independent, or whenthe channel is implemented for control logic. The main concern regarding multiplework-item accesses to a channel is the order in which the kernel writes data to andreads data from the channel. If possible, the SDK's channels extension processeswork-items read and write operations to the channel in a deterministic order. As such,the read and write operations remain consistent across kernel invocations.

Requirements for Deterministic Multiple Work-Item Ordering

To guarantee deterministic ordering, the SDK checks that the channel call is work-iteminvariant based on the following characteristics:

• All paths through the kernel must execute the channel call.

• If the first requirement is not satisfied, none of the branch conditions that reachthe channel call should execute in a work-item-dependent manner.

If the SDK cannot guarantee deterministic ordering of multiple work-item accesses toa channel, it warns you that the channels might not have well-defined ordering withnondeterministic execution. Primarily, the SDK fails to provide deterministic ordering ifyou have work-item-variant code on loop executions with channel calls, as illustratedbelow:

__kernel void ordering( __global int * restrict check, __global int * restrict data )



{ int condition = check[get_global_id(0)];

if(condition) { for(int i=0; i < N, i++) { process(data); write_channel_altera(req, data[i]); } } else { process(data); }}

1.6.4.3.1 Work-Item Serial Execution of Channels

Work-item serial execution refers to an ordered execution behavior where work-itemsequential IDs determine their execution order in the compute unit.

When you implement channels in a kernel, the Altera® Offline Compiler enforces thatkernel behavior is equivalent to having at most one work-group in flight. The AOC alsoensures that the kernel executes channels in work-item serial execution, where thekernel executes work-items with smaller IDs first. A work-item has the identifier (x,y, z, group), where x, y, z are the local 3D identifiers, and group is the work-group identifier.

The work-item ID (x0, y0, z0, group0) is considered to be smaller than the ID(x1, y1, z1, group1) if one of the following conditions is true:

• group0 < group1

• group0 = group1 and z0 < z1

• group0 = group1 and z0 = z1 and y0 < y1

• group0 = group1 and z0 = z1 and y0 = y1 and x0 < x1

Work-items with incremental IDs execute in a sequential order. For example, the work-item with an ID (x0, y0, z0, group0) executes the write channel call first. Then,the work-item with an ID (x1, y0, z0, group0) executes the call, and so on.Defining this order ensures that the system is verifiable with external models.

Channel Execution in Loop with Multiple Work-Items

When channels exist in the body of a loop with multiple work-items, as shown below,each loop iteration executes prior to subsequent iterations. This implies that loopiteration 0 of each work-item in a work-group executes before iteration 1 of eachwork-item in a work-group, and so on.

__kernel void ordering( __global int * data ){ write_channel_altera(req, data[get_global_id(0)]);}



1.6.4.4 Restrictions in the Implementation of Intel FPGA SDK for OpenCLChannels Extension

There are certain design restrictions to the implementation of channels in yourOpenCL application.

Single Call Site

Because the channel read and write operations do not function deterministically, for agiven kernel, you can only assign one call site per channel ID. For example, the IntelFPGA SDK for OpenCL Offline Compiler cannot compile the following code example:

in_data1 = read_channel_altera(channel1);in_data2 = read_channel_altera(channel2);in_data3 = read_channel_altera(channel1);

The second read_channel_altera call to channel1 causes compilation failurebecause it creates a second call site to channel1.

To gather multiple data from a given channel, divide the channel into multiplechannels, as shown below:


Because you can only assign a single call site per channel ID, you cannot unroll loopscontaining channels. Consider the following code:

#pragma unroll 4for (int i=0; i < 4; i++){ in_data = read_channel_altera(channel1);}

The offline compiler issues the following warning message during compilation:

Compiler Warning: Unroll is required but the loop cannot beunrolled.

Feedback and Feed-Forward Channels

Channels within a kernel can be either read_only or write_only. Performance of akernel that reads and writes to the same channel is poor.

Static Indexing

The Intel FPGA SDK for OpenCL channels extension does not support dynamicindexing into arrays of channel IDs.

Consider the following example:

#pragma OPENCL EXTENSION cl_altera_channels : enable

channel int ch[WORKGROUP_SIZE];

__kernel void consumer()



{

int gid = get_global_id(0); int value = read_channel_altera(ch[gid]);

//statements}

Compilation of this example kernel fails with the following error message:

Compiler Error: Indexing into channel array ch could not be resolved to all constant

To avoid this compilation error, index into arrays of channel IDs statically, as shownbelow:

#pragma OPENCL EXTENSION cl_altera_channels : enable channel int ch[WORKGROUP_SIZE]; __kernel void consumer(){ int gid = get_global_id(0); int value;

switch(gid) { case 0: value = read_channel_altera(ch[0]); break; case 1: value = read_channel_altera(ch[1]); break; case 2: value = read_channel_altera(ch[2]); break; case 3: value = read_channel_altera(ch[3]); break; //statements case WORKGROUP_SIZE-1:read_channel_altera(ch[WORKGROUP_SIZE-1]); break; }

//statements}

Kernel Vectorization Support

You cannot vectorize kernels that use channels; that is, do not include thenum_simd_work_items kernel attribute in your kernel code. Vectorizing a kernel thatuses channels creates multiple channel masters and requires arbitration, which theSDK's channels extension does not support.

Instruction-Level Parallelism on read_channel_altera andwrite_channel_altera Calls

If no data dependencies exist between read_channel_altera andwrite_channel_altera calls, the offline compiler attempts to execute theseinstructions in parallel. As a result, the offline compiler might execute theseread_channel_altera and write_channel_altera calls in an order that doesnot follow the sequence expressed in the OpenCL kernel code.



Consider the following code sequence:


Because there are no data dependencies between the read_channel_altera calls,the offline compiler can execute them in any order.

1.6.4.5 Enabling the Intel FPGA SDK for OpenCL Channels for OpenCL Kernel

To implement the Intel FPGA SDK for OpenCL channels extension, modify your OpenCLkernels to include channels-specific pragma and API calls.

Channel declarations are unique within a given OpenCL kernel program. Also, channelinstances are unique for every OpenCL kernel program device pair. If the runtimeloads a single OpenCL kernel program onto multiple devices, each device will have asingle copy of the channel. However, these channel copies are independent and do notshare data across the devices.

1.6.4.5.1 Declaring the Channels OPENCL EXTENSION pragma

To enable the Intel FPGA SDK for OpenCL channels extension, declare the OPENCLEXTENSION pragma for channels at the beginning of your kernel source code.

• To enable the SDK's channels extension, include the following line in your kernelsource code to declare the OPENCL EXTENSION pragma:


1.6.4.5.2 Declaring the Channel Handle

Use the channel variable to define the connectivity between kernels or betweenkernels and I/O.

To read from and write to a channel, the kernel must pass the channel variable toeach of the corresponding API call.

• Declare the channel handle as a file scope variable in the kernel source code in thefollowing convention: channel <type> <variable_name>

For example: channel int c;

• The Intel FPGA SDK for OpenCL channel extension supports simultaneous channelaccesses by multiple variables declared in a data structure. Declare a struct datastructure for a channel in the following manner:

typedef struct type_ { int a; int b;} type_t;

channel type_t foo;

1.6.4.5.3 Implementing Blocking Channel Write Extensions

The write_channel_altera API call allows you to send data across a channel.



Note: The write channel calls support single-call sites only. For a given channel, only onewrite channel call to it can exist in the entire kernel program.

• To implement a blocking channel write, include the followingwrite_channel_altera function signature:

void write_channel_altera (channel <type> channel_id, const<type> data);

Where:

channel_id identifies the buffer to which the channel connects, and it mustmatch the channel_id of the corresponding read channel(read_channel_altera).

data is the data that the channel write operation writes to the channel. Data<type> must match the <type> of the channel_id.

<type> defines a channel data width, which cannot be a constant. Follow theOpenCL conversion rules to ensure that data the kernel writes to a channel isconvertible to <type>.

The following code snippet demonstrates the implementation of thewrite_channel_altera API call:

//Enables the channels extension.#pragma OPENCL EXTENSION cl_altera_channels : enable

//Defines chan, the kernel file-scope channel variable.channel long chan;

/*Defines the kernel which reads eight bytes (size of long) from global memory, and passes this data to the channel.*/ __kernel void kernel_write_channel( __global const long * src ){ for(int i=0; i < N; i++) { //Writes the eight bytes to the channel. write_channel_altera(chan, src[i]); }}

Caution: When you send data across a write channel using the write_channel_altera APIcall, keep in mind that if the channel is full (that is, if the FIFO buffer is full of data),your kernel will stall. Use the Intel FPGA SDK for OpenCL Profiler to check for channelstalls.

Related Links

Profiling Your OpenCL Kernel on page 106The Intel FPGA SDK for OpenCL Profiler measures and reports performance datacollected during OpenCL kernel execution on the FPGA.

Implementing Nonblocking Channel Write ExtensionsPerform nonblocking channel writes to facilitate applications where data writeoperations might not occur. A nonblocking channel write extension returns a Booleanvalue that indicates whether data is written to the channel.



Consider a scenario where your application has one data producer with two identicalworkers. Assume the time each worker takes to process a message varies dependingon the contents of the data. In this case, there might be situations where one workeris busy while the other is free. A nonblocking write can facilitate work distribution suchthat both workers are busy.

• To implement a nonblocking channel write, include the followingwrite_channel_nb_altera function signature:

bool write_channel_nb_altera(channel <type> channel_id, const<type> data);

The following code snippet of the kernel producer facilitates work distribution usingthe nonblocking channel write extension:

#pragma OPENCL EXTENSION cl_altera_channels : enablechannel long worker0, worker1;__kernel void producer( __global const long * src ){ for(int i=0; i < N; i++) { bool success = false; do { success = write_channel_nb_altera(worker0, src[i]); if(!success) { success = write_channel_nb_altera(worker1, src[i]); } } while(!success); }}

1.6.4.5.4 Implementing Blocking Channel Read Extensions

The read_channel_altera API call allows you to receive data across a channel.

Note: The read channel calls support single-call sites only. For a given channel, only oneread channel call to it can exist in the entire kernel program.

• To implement a blocking channel read, include the followingread_channel_altera function signature:

<type> read_channel_altera(channel <type> channel_id);

Where:

channel_id identifies the buffer to which the channel connects, and it mustmatch the channel_id of the corresponding write channel(write_channel_altera).

<type> defines a channel data width, which cannot be a constant. Ensure that thevariable the kernel assigns to read the channel data is convertible from <type>.

The following code snippet demonstrates the implementation of theread_channel_altera API call:

//Enables the channel extension.#pragma OPENCL EXTENSION cl_altera_channels : enable;



//Defines chan, the kernel file-scope channel variable.channel long chan;

/*Defines the kernel, which reads eight bytes (size of long) from the channel and writes it back to global memory.*/__kernel void kernel_read_channel( __global long * dst );{ for(int i=0; i < N; i++) { //Reads the eight bytes from the channel. dst[i] = read_channel_altera(chan); }}

Caution: If the channel is empty (that is, if the FIFO buffer is empty), you cannot receive dataacross a read channel using the read_channel_altera API call. Doing so causesyour kernel to stall.

Implementing Nonblocking Channel Read ExtensionsPerform nonblocking reads to facilitate applications where data is not always available.The nonblocking reads signature is similar to blocking reads. However, it returns aninteger value that indicates whether a read operation takes place successfully.

• To implement a blocking channel write, include the followingread_channel_nb_altera function signature:

<type> read_channel_nb_altera(channel <type> channel_id, bool* valid);

The following code snippet demonstrates the use of the nonblocking channel readextension:

#pragma OPENCL EXTENSION cl_altera_channels : enablechannel long chan;

__kernel void kernel_read_channel( __global long * dst ){ int i=0; while(i < N) { bool valid0, valid1; long data0 = read_channel_nb_altera(chan, &valid0); long data1 = read_channel_nb_altera(chan, &valid1); if (valid0) { process(data0); } if (valid1) process(data1); { process(data1); } }}

1.6.4.5.5 Implementing I/O Channels Using the io Channels Attribute

Include an io attribute in your channel declaration to declare a special I/O channel tointerface with input or output features of an FPGA board.These features might include network interfaces, PCIe, cameras, or other data captureor processing devices or protocols.



The io("chan_id") attribute specifies the I/O feature of an accelerator board withwhich a channel interfaces, where chan_id is the name of the I/O interface listed inthe board_spec.xml file of your Custom Platform.

Because peripheral interface usage might differ for each device type, consult yourboard vendor's documentation when you implement I/O channels in your kernelprogram. Your OpenCL kernel code must be compatible with the type of datagenerated by the peripheral interfaces.

Cautions: • Implicit data dependencies might exist for channels that connect to the boarddirectly and communicate with peripheral devices via I/O channels. These implicitdata dependencies might lead to compilation issues because the Intel FPGA SDKfor OpenCL Offline Compiler cannot identify these dependencies.

• External I/O channels communicating with the same peripherals do not obey anysequential ordering. Ensure that the external device does not require sequentialordering because unexpected behavior might occur.

1. Consult the board_spec.xml file in your Custom Platform to identify the inputand output features available on your FPGA board.

For example, a board_spec.xml file might include the following information onI/O features:

<channels> <interface name="udp_0" port="udp0_out" type="streamsource" width="256" chan_id="eth0_in"/> <interface name="udp_0" port="udp0_in" type="streamsink" width="256" chan_id="eth0_out"/> <interface name="udp_0" port="udp1_out" type="streamsource" width="256" chan_id="eth1_in"/> <interface name="udp_0" port="udp1_in" type="streamsink" width="256" chan_id="eth1_out"/></channels>

The width attribute of an interface element specifies the width, in bits, of thedata type used by that channel. For the example above, both the uint and floatdata types are 32 bits wide. Other bigger or vectorized data types must match theappropriate bit width specified in the board_spec.xml file.

2. Implement the io channel attribute as demonstrated in the following codeexample. The io channel attribute names must match those of the I/O channels(chan_id) specified in the board_spec.xml file.

channel QUDPWord udp_in_IO __attribute__((depth(0))) __attribute__((io("eth0_in"))); channel QUDPWord udp_out_IO __attribute__((depth(0))) __attribute__((io("eth0_out")));

__kernel void io_in_kernel( __global ulong4 *mem_read, uchar read_from, int size ){ int index = 0; ulong4 data; int half_size = size >> 1; while (index < half_size) { if (read_from & 0x01) { data = read_channel_altera(udp_in_IO);



} else { data = mem_read[index]; } write_channel_altera(udp_in, data); index++; }}

__kernel void io_out_kernel( __global ulong2 *mem_write, uchar write_to, int size ){ int index = 0; ulong4 data; int half_size = size >> 1; while (index < half_size) { ulong4 data = read_channel_altera(udp_out); if (write_to & 0x01) { write_channel_altera(udp_out_IO, data); } else { //only write data portion ulong2 udp_data; udp_data.s0 = data.s0; udp_data.s1 = data.s1; mem_write[index] = udp_data; } index++; }}

Attention: Declare a unique io("chan_id") handle for each I/O channelspecified in the channels eXtensible Markup Language (XML) elementwithin the board_spec.xml file.

1.6.4.5.6 Implementing Buffered Channels Using the depth Channels Attribute

You may have buffered or unbuffered channels in your kernel program. If there areimbalances in channel read and write operations, create buffered channels to preventkernel stalls by including the depth attribute in your channel declaration. Bufferedchannels decouple the operation of concurrent work-items executing in differentkernels.

You may use a buffered channel to control data traffic, such as limiting throughput orsynchronizing accesses to shared memory. In an unbuffered channel, a write operationcannot proceed until the read operation reads a data value. In a buffered channel, awrite operation cannot proceed until the data value is copied to the buffer. If the bufferis full, the operation cannot proceed until the read operation reads a piece of data andremoves it from the channel.



• If you expect any temporary mismatch between the consumption rate and theproduction rate to the channel, set the buffer size using the depth channelattribute.

The following example demonstrates the use of the depth channel attribute inkernel code that implements the Intel FPGA SDK for OpenCL channels extension.The depth(N) attribute specifies the minimum depth of a buffered channel,where N is the number of data values.

#pragma OPENCL EXTENSION cl_altera_channels : enablechannel int c __attribute__((depth(10)));

__kernel void producer( __global int * in_data ){ for(int i=0; i < N; i++) { if(in_data[i]) { write_channel_altera(c, in_data[i]); } }}

__kernel void consumer( __global int * restrict check_data, __global int * restrict out_data ){ int last_val = 0;

for(int i=0; i< N, i++) { if(check_data[i]) { last_val = read_channel_altera(c); } out_data[i] = last_val; }}

In this example, the write operation can write ten data values to the channelwithout blocking. Once the channel is full, the write operation cannot proceed untilan associated read operation to the channel occurs.

Because the channel read and write calls are conditional statements, the channelmight experience an imbalance between read and write calls. You may add abuffer capacity to the channel to ensure that the producer and consumerkernels are decoupled. This step is particularly important if the producer kernelis writing data to the channel when the consumer kernel is not reading from it.

1.6.4.5.7 Enforcing the Order of Channel Calls

To enforce the order of channel calls, introduce memory fence or barrier functions inyour kernel program to control memory accesses. A memory fence function isnecessary to create a control flow dependence between the channel synchronizationcalls before and after the fence.

When the Intel FPGA SDK for OpenCL Offline Compiler generates a compute unit, itdoes not create instruction-level parallelism on all instructions that are independent ofeach other. As a result, channel read and write operations might not executeindependently of each other even if there is no control or data dependence betweenthem. When channel calls interact with each other, or when channels write data toexternal devices, deadlocks might occur.



For example, the code snippet below consists of a producer kernel and a consumerkernel. Channels c0 and c1 are unbuffered channels. The schedule of the channelread operations from c0 and c1 might occur in the reversed order as the channelwrite operations to c0 and c1. That is, the producer kernel writes to c0 but theconsumer kernel might read from c1 first. This rescheduling of channel calls mightcause a deadlock because the consumer kernel is reading from an empty channel.

__kernel void producer( __global const uint * src, const uint iterations ){ for(int i=0; i < iterations; i++) { write_channel_altera(c0, src[2*i]); write_channel_altera(c1, src[2*i+1]); }}

__kernel void consumer( __global uint * dst, const uint iterations ){ for(int i=0; i < iterations; i++) { /*During compilation, the AOC might reorder the way the consumer kernel writes to memory to optimize memory access. Therefore, c1 might be read before c0, which is the reverse of what appears in code.*/

dst[2*i+1] = read_channel_altera(c0); dst[2*i] = read_channel_altera(c1); }}



• To prevent deadlocks from occurring by enforcing the order of channel calls,include memory fence functions (mem_fence) in your kernel.

Inserting the mem_fence call with each kernel's channel flag forces the sequentialordering of the write and read channel calls. The code snippet below shows themodified producer and consumer kernels:


channel uint c0 __attribute__((depth(0)));channel uint c1 __attribute__((depth(0)));

__kernel void producer( __global const uint * src, const uint iterations ){ for(int i=0; i < iterations; i++) { write_channel_altera(c0, src[2*i]); mem_fence(CLK_CHANNEL_MEM_FENCE); write_channel_altera(c1, src[2*i+1]); }}

__kernel void consumer( __global uint * dst; const uint iterations ){ for(int i=0; i < iterations; i++) { dst[2*i+1] = read_channel_altera(c0); mem_fence(CLK_CHANNEL_MEM_FENCE); dst[2*i] = read_channel_altera(c1); }}

In this example, mem_fence in the producer kernel ensures that the channelwrite operation to c0 occurs before that to c1. Similarly, mem_fence in theconsumer kernel ensures that the channel read operation from c0 occurs beforethat from c1.

Defining Memory Consistency Across Kernels When Using ChannelsAccording to the OpenCL Specification version 1.0, memory behavior is undefinedunless a kernel completes execution. A kernel must finish executing before otherkernels can visualize any changes in memory behavior. However, kernels that usechannels can share data through common global memory buffers and synchronizedmemory accesses. To ensure that data written to a channel is visible to the readchannel after execution passes a memory fence, define memory consistency acrosskernels with respect to memory fences.



• To create a control flow dependency between the channel synchronization callsand the memory operations, add the CLK_GLOBAL_MEM_FENCE flag to themem_fence call.

For example:

__kernel void producer( __global const uint * src, const uint iterations ){ for(int i=0; i < iterations; i++) { write_channel_altera(c0, src[2*i]); mem_fence(CLK_CHANNEL_MEM_FENCE | CLK_GLOBAL_MEM_FENCE); write_channel_altera(c1, src[2*i+1]); }}

In this kernel, the mem_fence function ensures that the write operation to c0 andmemory access to src[2*i] occur before the write operation to c1 and memoryaccess to src[2*i+1]. This allows data written to c0 to be visible to the readchannel before data is written to c1.

1.6.4.6 Use Models of Intel FPGA SDK for OpenCL Channels Implementation

Concurrent execution can improve the effectiveness of channels implementation inyour OpenCL kernels.During concurrent execution, the host launches the kernels in parallel. The kernelsshare memory and can communicate with each other through channels whereapplicable.

The use models provide an overview on how to exploit concurrent execution safely andefficiently.

Feed-Forward Design Model

Implement the feed-forward design model to send data from one kernel to the nextwithout creating any cycles between them. Consider the following code example:

__kernel void producer( __global const uint * src, const uint iterations ){ for(int i=0; i < iterations; i++) { write_channel_altera(c0, src[2*i]); mem_fence(CLK_CHANNEL_MEM_FENCE); write_channel_altera(c1, src[2*i+1]); }}

__kernel void consumer( __global uint * dst, const uint iterations ){ for (int i=0;i<iterations;i++) { dst[2*i] = read_channel_altera(c0); mem_fence(CLK_CHANNEL_MEM_FENCE); dst[2*i+1] = read_channel_altera(c1); }}



The producer kernel writes data to channels c0 and c1. The consumer kernel readsdata from c0 and c1. The figure below illustrates the feed-forward data flow betweenthe two kernels:

Figure 7. Feed-Forward Data Flow

Producer Consumer

Buffer Management

In the feed-forward design model, data traverses between the producer andconsumer kernels one word at a time. To facilitate the transfer of large datamessages consisting of several words, you can implement a ping-pong buffer, which isa common design pattern found in applications for communication. The figure belowillustrates the interactions between kernels and a ping-pong buffer:

Figure 8. Feed-Forward Design Model with Buffer Management

Producer Consumer

Manager

Buffer

The manager kernel manages circular buffer allocation and deallocation between theproducer and consumer kernels. After the consumer kernel processes data, themanager receives memory regions that the consumer frees up and sends them tothe producer for reuse. The manager also sends to the producer kernel the initialset of free locations, or tokens, to which the producer can write data.

The following figure illustrates the sequence of events that take place during buffermanagement:



Figure 9. Kernels Interaction during Buffer Management

Producer Consumer

Manager

Buffer

Producer Consumer

Manager

Buffer

Producer Consumer

Manager

Buffer

Producer Consumer

Manager

Buffer

(1) (4)(3)(2)

1. The manager kernel sends a set of tokens to the producer kernel to indicateinitially which regions in memory are free for producer to use.

2. After manager allocates the memory region, producer writes data to that regionof the ping-pong buffer.

3. After producer completes the write operation, it sends a synchronization token tothe consumer kernel to indicate what memory region contains data forprocessing. The consumer kernel then reads data from that region of the ping-pong buffer.

Note: When consumer is performing the read operation, producer can write toother free memory locations for processing because of the concurrentexecution of the producer, consumer, and manager kernels.

4. After consumer completes the read operation, it releases the memory region andsends a token back to the manager kernel. The manager kernel then recyclesthat region for producer to use.

Implementation of Buffer Management for OpenCL Kernels

To ensure that the SDK implements buffer management properly, the ordering ofchannel read and write operations is important. Consider the following kernelexample:

__kernel void producer( __global const uint * restrict src, __global volatile uint * restrict shared_mem, const uint iterations ){ int base_offset; for (uint gID = 0; gID < iterations; gID++) { // Assume each block of memory is 256 words uint lID = 0x0ff & gID;

if(lID == 0) { base_offset = read_channel_altera(req); }

shared_mem[base_offset + lID] = src[gID];

// Make sure all memory operations are committed before // sending token to the consumer mem_fence(CLK_GLOBAL_MEM_FENCE | CLK_CHANNEL_MEM_FENCE);

if (lID == 255)



{ write_channel_altera(c, base_offset); } }}

In this kernel, because the following lines of code are independent, the Intel FPGASDK for OpenCL Offline Compiler can schedule them to execute concurrently:

shared_mem[base_offset + lID] = src[gID];

and

write_channel_altera(c, base_offset);

Writing data to base_offset and then writing base_offset to a channel might bemuch faster than writing data to global memory. The consumer kernel might thenread base_offset from the channel and use it as an index to read from globalmemory. Without synchronization, consumer might read data from producer beforeshared_mem[base_offset + lID] = src[gID]; finishes executing. As a result,consumer reads in invalid data. To avoid this scenario, the synchronization tokenmust occur after the producer kernel commits data to memory. In other words, aconsumer kernel cannot consume data from the producer kernel until producerstores its data in global memory successfully.

To preserve this ordering, include an OpenCL mem_fence token in your kernels. Themem_fence construct takes two flags: CLK_GLOBAL_MEM_FENCE andCLK_CHANNEL_MEM_FENCE. The mem_fence effectively creates a control flowdependence between operations that occur before and after the mem_fence call. TheCLK_GLOBAL_MEM_FENCE flag indicates that global memory operations must obey thecontrol flow. The CLK_CHANNEL_MEM_FENCE indicates that channel operations mustobey the control flow. As a result, the write_channel_altera call in the examplecannot start until the global memory operation is committed to the shared memorybuffer.

1.6.5 Implementing OpenCL Pipes

The Intel FPGA SDK for OpenCL provides preliminary support for OpenCL pipefunctions.OpenCL pipes are part of the OpenCL Specification version 2.0. They provide amechanism for passing data to kernels and synchronizing kernels with high efficiencyand low latency.

Implement pipes if it is important that your OpenCL kernel is compatible with otherSDKs.

Refer to the OpenCL Specification version 2.0 for OpenCL C programming languagespecification and general information about pipes.

The Intel FPGA SDK for OpenCL implementation of pipes does not encompass theentire pipes specification. As such, it is not fully conformant to the OpenCLSpecification version 2.0. The goal of the SDK's pipes implementation is to provide a



solution that works seamlessly on a different OpenCL 2.0-conformant device. Toenable pipes for Intel FPGA products, your design must satisfy certain additionalrequirements.

Related Links

OpenCL Specification version 2.0 (API)

1.6.5.1 Overview of the OpenCL Pipe Functions

OpenCL pipes allow kernels to communicate directly with each other via FIFO buffers.

Figure 10. Overview of a Pipe Network Implementation

FIFOFIFO

FIFOKernel 0

Kernel 1

Kernel 2

FIFOKernel N FIFO

RAM

I/O Pipe

Host Processor

Initialize ( )

I/O Pipe

FIFO

Implementation of pipes decouples kernel execution from the host processor. Thefoundation of the Intel FPGA SDK for OpenCL pipes support is the SDK's channelsextension. However, the syntax for pipe functions differs from the channels syntax.

Important: Unlike channels, pipes have a default nonblocking behavior.

For more information on blocking and nonblocking functions, refer to thecorresponding documentation on channels.

Related Links

• Implementing Blocking Channel Write Extensions on page 30The write_channel_altera API call allows you to send data across achannel.

• Implementing Nonblocking Channel Write Extensions on page 31Perform nonblocking channel writes to facilitate applications where data writeoperations might not occur.

• Implementing Nonblocking Channel Read Extensions on page 33Perform nonblocking reads to facilitate applications where data is not alwaysavailable.

• Implementing Blocking Channel Read Extensions on page 32



https://www.khronos.org/registry/cl/specs/opencl-2.0.pdf

The read_channel_altera API call allows you to receive data across achannel.

1.6.5.2 Pipe Data Behavior

Data written to a pipe remains in a pipe as long as the kernel program remains loadedon the FPGA device. In other words, data written to a pipe persists across multiplework-groups and NDRange invocations. However, data is not persistent across multipleor different invocations of kernel programs.


__kernel voidproducer (write_only pipe uint __attribute__((blocking)) c0){ for (uint i=0;i<10;i++) { write_pipe( c0, &i ); }}

__kernel voidconsumer (__global uint * restrict dst, read_only pipe uint __attribute__((blocking)) __attribute__((depth(10))) c0){ for (int i=0;i<5;i++) { read_pipe( c0, &dst[i] ); }}

A read operation to a pipe reads the least recent piece of data written to the pipe first.Pipes data maintains their FIFO ordering within the pipe.

Figure 11. Pipe Data FIFO Ordering

9 012345678Producer Consumer

The kernel producer writes ten elements ([0, 9]) to the pipe. The kernel consumerreads five elements from the pipe per NDRange invocation. During the first invocation,the kernel consumer reads values 0 to 4 from the pipe. Because the data persistsacross NDRange invocations, the second time you execute the kernel consumer, itreads values 5 to 9.

For this example, to avoid a deadlock from occurring, you need to invoke the kernelconsumer twice for every invocation of the kernel producer. If you call consumerless than twice, producer stalls because the pipe becomes full. If you call consumermore than twice, consumer stalls because there is insufficient data in the pipe.

1.6.5.3 Multiple Work-Item Ordering for Pipes

The OpenCL specification does not define a work-item ordering. The Intel FPGA SDKfor OpenCL enforces a work-item order to maintain the consistency in pipe read andwrite operations.



Multiple work-item accesses to a pipe can be useful in some scenarios. For example,they are useful when data words in the pipe are independent, or when the pipe isimplemented for control logic. The main concern regarding multiple work-itemaccesses to a pipe is the order in which the kernel writes data to and reads data fromthe pipe. If possible, the OpenCL pipes process work-items read and write operationsto a pipe in a deterministic order. As such, the read and write operations remainconsistent across kernel invocations.

Requirements for Deterministic Multiple Work-Item Ordering

To guarantee deterministic ordering, the SDK checks that the pipe call is work-iteminvariant based on the following characteristics:

• All paths through the kernel must execute the pipe call.

• If the first requirement is not satisfied, none of the branch conditions that reachthe pipe call should execute in a work-item-dependent manner.

If the SDK cannot guarantee deterministic ordering of multiple work-item accesses toa pipe, it warns you that the pipes might not have well-defined ordering withnondeterministic execution. Primarily, the SDK fails to provide deterministic ordering ifyou have work-item-variant code on loop executions with pipe calls, as illustratedbelow:

__kernel voidordering (__global int * check, global int * data, write_only pipe int __attribute__((blocking)) req){ int condition = check[get_global_id(0)];

if (condition) { for (int i=0;i<N;i++) { process(data); write_pipe( req, &data[i] ); } } else { process(data); }}

1.6.5.3.1 Work-Item Serial Execution of Pipes

Work-item serial execution refers to an ordered execution behavior where work-itemsequential IDs determine their execution order in the compute unit.

When you implement pipes in a kernel, the Intel FPGA SDK for OpenCL OfflineCompiler enforces that kernel behavior is equivalent to having at most one work-groupin flight. The offline compiler also ensures that the kernel executes pipes in work-itemserial execution, where the kernel executes work-items with smaller IDs first. A work-item has the identifier (x, y, z, group), where x, y, z are the local 3D identifiers,and group is the work-group identifier.

The work-item ID (x0, y0, z0, group0) is considered to be smaller than the ID(x1, y1, z1, group1) if one of the following conditions is true:



• group0 < group1

• group0 = group1 and z0 < z1

• group0 = group1 and z0 = z1 and y0 < y1

• group0 = group1 and z0 = z1 and y0 = y1 and x0 < x1

Work-items with incremental IDs execute in a sequential order. For example, the work-item with an ID (x0, y0, z0, group0) executes the write channel call first. Then,the work-item with an ID (x1, y0, z0, group0) executes the call, and so on.Defining this order ensures that the system is verifiable with external models.

Pipe Execution in Loop with Multiple Work-Items

When pipes exist in the body of a loop with multiple work-items, as shown below, eachloop iteration executes prior to subsequent iterations. This implies that loop iteration 0of each work-item in a work-group executes before iteration 1 of each work-item in awork-group, and so on.

__kernel voidordering (__global int * data, write_only pipe int __attribute__((blocking)) req){ write_pipe( req, &data[get_global_id(0)] );}

1.6.5.4 Restrictions in OpenCL Pipes Implementation

There are certain design restrictions to the implementation of pipes in your OpenCLapplication.

Default Behavior

By default, pipes exhibit nonblocking behavior. If you want the pipes in your kernel toexhibit blocking behavior, specify the blocking attribute(__attribute__((blocking))) when you declare the read and write pipes.

Emulation Support

The Intel FPGA SDK for OpenCL Emulator supports emulation of kernels that containpipes. The level of Emulator support aligns with the subset of OpenCL pipes supportthat is implemented for the FPGA hardware.

Pipes API Support

Currently, the SDK's implementation of pipes does not support all the built-in pipefunctions in the OpenCL Specification version 2.0. For a list of supported andunsupported pipe APIs, refer to OpenCL 2.0 C Programming Language Restrictions forPipes.



Single Call Site

Because the pipe read and write operations do not function deterministically, for agiven kernel, you can only assign one call site per pipe ID. For example, the IntelFPGA SDK for OpenCL Offline Compiler cannot compile the following code example:

read_pipe(pipe1, &in_data1);read_pipe(pipe2, &in_data2);read_pipe(pipe1, &in_data3);

The second read_pipe call to pipe1 causes compilation failure because it creates asecond call site to pipe1.

To gather multiple data from a given pipe, divide the pipe into multiple pipes, asshown below:

read_pipe(pipe1, &in_data1);read_pipe(pipe2, &in_data2);read_pipe(pipe3, &in_data3);

Because you can only assign a single call site per pipe ID, you cannot unroll loopscontaining pipes. Consider the following code:

#pragma unroll 4for (int i=0; i < 4; i++){ read_pipe(pipe1, &in_data1);}

The offline compiler issues the following warning message during compilation:

Compiler Warning: Unroll is required but the loop cannot beunrolled.

Feedback and Feed-Forward Pipes

Pipes within a kernel can be either read_only or write_only. Performance of akernel that reads and writes to the same pipe is poor.

Kernel Vectorization Support

You cannot vectorize kernels that use pipes; that is, do not include thenum_simd_work_items kernel attribute in your kernel code. Vectorizing a kernel thatuses pipes creates multiple pipe masters and requires arbitration, which OpenCL pipesspecification does not support.

Instruction-Level Parallelism on read_pipe and write_pipe Calls

If no data dependencies exist between read_pipe and write_pipe calls, the offlinecompiler attempts to execute these instructions in parallel. As a result, the offlinecompiler might execute these read_pipe and write_pipe calls in an order thatdoes not follow the sequence expressed in the OpenCL kernel code.



Consider the following code sequence:

in_data1 = read_pipe(pipe1);in_data2 = read_pipe(pipe2);in_data3 = read_pipe(pipe3);

Because there are no data dependencies between the read_pipe calls, the offlinecompiler can execute them in any order.

Related Links

OpenCL 2.0 C Programming Language Restrictions for Pipes on page 149The Intel FPGA SDK for OpenCL offers preliminary support of OpenCL pipes.

1.6.5.5 Enabling OpenCL Pipes for Kernels

To implement pipes, modify your OpenCL kernels to include pipes-specific API calls.

Pipes declarations are unique within a given OpenCL kernel program. Also, pipeinstances are unique for every OpenCL kernel program-device pair. If the runtimeloads a single OpenCL kernel program onto multiple devices, each device will have asingle copy of each pipe. However, these pipe copies are independent and do notshare data across the devices.

1.6.5.5.1 Ensuring Compatibility with Other OpenCL SDKs

Currently, Intel's implementation of OpenCL pipes is partially conformant to theOpenCL Specification version 2.0. If you port a kernel that implements pipes fromanother OpenCL SDK to the Intel FPGA SDK for OpenCL, you must modify the hostcode and the kernel code. The modifications do not affect subsequent portability ofyour application to other OpenCL SDKs.

Host Code Modification

Below is an example of a modified host application:

#include <stdio.h>#include <stdlib.h>#include <string.h>#include "CL/opencl.h"#define SIZE 1000

const char *kernel_source = "__kernel void pipe_writer(__global int *in," " write_only pipe int p_in)\n" "{\n" " int gid = get_global_id(0);\n" " write_pipe(p_in, &in[gid]);\n" "}\n" "__kernel void pipe_reader(__global int *out," " read_only pipe int p_out)\n" "{\n" " int gid = get_global_id(0);\n" " read_pipe(p_out, &out[gid]);\n" "}\n";

int main(){ int *input = (int *)malloc(sizeof(int) * SIZE); int *output = (int *)malloc(sizeof(int) * SIZE); memset(output, 0, sizeof(int) * SIZE);



for (int i = 0; i != SIZE; ++i) { input[i] = rand(); }

cl_int status; cl_platform_id platform; cl_uint num_platforms; status = clGetPlatformIDs(1, &platform, &num_platforms);

cl_device_id device; cl_uint num_devices; status = clGetDeviceIDs(platform, CL_DEVICE_TYPE_ALL, 1, &device, &num_devices);

cl_context context = clCreateContext(0, 1, &device, NULL, NULL, &status);

cl_command_queue queue = clCreateCommandQueue(context, device, 0, &status);

size_t len = strlen(kernel_source); cl_program program = clCreateProgramWithSource(context, 1, (const char **)&kernel_source, &len, &status);

status = clBuildProgram(program, num_devices, &device, "", NULL, NULL);

cl_kernel pipe_writer = clCreateKernel(program, "pipe_writer", &status); cl_kernel pipe_reader = clCreateKernel(program, "pipe_reader", &status);

cl_mem in_buffer = clCreateBuffer(context, CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR, sizeof(int) * SIZE, input, &status); cl_mem out_buffer = clCreateBuffer(context, CL_MEM_WRITE_ONLY, sizeof(int) * SIZE, NULL, &status);

cl_mem pipe = clCreatePipe(context, 0, sizeof(cl_int), SIZE, NULL, &status);

status = clSetKernelArg(pipe_writer, 0, sizeof(cl_mem), &in_buffer); status = clSetKernelArg(pipe_writer, 1, sizeof(cl_mem), &pipe); status = clSetKernelArg(pipe_reader, 0, sizeof(cl_mem), &out_buffer); status = clSetKernelArg(pipe_reader, 1, sizeof(cl_mem), &pipe);

size_t size = SIZE; cl_event sync; status = clEnqueueNDRangeKernel(queue, pipe_writer, 1, NULL, &size, &size, 0, NULL, &sync); status = clEnqueueNDRangeKernel(queue, pipe_reader, 1, NULL, &size, &size, 1, &sync,



NULL); status = clFinish(queue);

status = clEnqueueReadBuffer(queue, out_buffer, CL_TRUE, 0, sizeof(int) * SIZE, output, 0, NULL, NULL);

int golden = 0, result = 0; for (int i = 0; i != SIZE; ++i) { golden += input[i]; result += output[i]; }

int ret = 0; if (golden != result) { printf("FAILED!"); ret = 1; } else { printf("PASSED!"); } printf("\n");

return ret;}

Kernel Code Modification

If your kernel code runs on OpenCL SDKs that conforms to the OpenCL Specificationversion 2.0, you must modify it before running it on the Intel FPGA SDK for OpenCL.To modify the kernel code, perform the following modifications:

• Rename the pipe arguments so that they are the same in both kernels. Forexample, rename p_in and p_out to p.

• Specify the depth attribute for the pipe arguments. Assign a depth attributevalue that equals to the maximum number of packets that the pipe creates to holdin the host.

• Execute the kernel program in the offline compilation mode because the IntelFPGA SDK for OpenCL has an offline compiler.

The modified kernel code appears as follows:

#define SIZE 1000

__kernel void pipe_writer(__global int *in, write_only pipe int __attribute__((depth(SIZE))) p){ int gid = get_global_id(0); write_pipe(p, &in[gid]);}

__kernel void pipe_reader(__global int *out, read_only pipe int __attribute__((depth(SIZE))) p){



int gid = get_global_id(0); read_pipe(p, &out[gid]);}

1.6.5.5.2 Declaring the Pipe Handle

Use the pipe variable to define the static pipe connectivity between kernels orbetween kernels and I/O.

To read from and write to a pipe, the kernel must pass the pipe variable to each of thecorresponding API call.

• Declare the pipe handle as a file scope variable in the kernel source code in thefollowing convention: <access qualifier> pipe <type> <variable_name>

The <type> of the pipe may be any OpenCL built-in scalar or vector data typewith a scalar size of 1024 bits or less. It may also be any user-defined type that iscomprised of scalar or vector data type with a scalar size of 1024 bits or less.

Consider the following pipe handle declarations:

__kernel void first (pipe int c)

__kernel void second (write_only pipe int c)

The first example declares a read-only pipe handle of type int in the kernelfirst. The second example declares a write-only pipe in the kernel second. Thekernel first may only read from pipe c, and the kernel second may only writeto pipe c.

Important: The Intel FPGA SDK for OpenCL Offline Compiler statically infers theconnectivity of pipes in your system by matching the names of thepipe arguments. In the example above, the kernel first is connectedto the kernel second by the pipe c.

In an Intel OpenCL system, only one kernel may read to a pipe. Similarly, only onekernel may write to a pipe. If a non-I/O pipe does not have at least one correspondingreading operation and one writing operation, the offline compiler issues an error.

For more information in the Intel FPGA SDK for OpenCL I/O pipe implementation, referto Implementing I/O Pipes Using the io Attribute.

Related Links

Implementing I/O Pipes Using the io Attribute on page 54Include an io attribute in your OpenCL pipe declaration to declare a special I/Opipe to interface with input or output features of an FPGA board.

1.6.5.5.3 Implementing Pipe Writes

The write_pipe API call allows you to send data across a pipe.

Intel only supports the convenience version of the write_pipe function. By default,write_pipe calls are nonblocking. Pipe write operations are successful only if there iscapacity in the pipe to hold the incoming packet.

Attention: The write pipe calls support single-call sites only. For a given pipe, only one write pipecall to it can exist in the entire kernel program.



• To implement a pipe write, include the following write_pipe function signature:

int write_pipe (write_only pipe <type> pipe_id, const <type>*data);

Where:

pipe_id identifies the buffer to which the pipe connects, and it must match thepipe_id of the corresponding read pipe (read_pipe).

data is the data that the pipe write operation writes to the pipe. It is a pointer tothe packet type of the pipe. Note that writing to the pipe might lead to a global orlocal memory load, depending on the source address space of the data pointer.

<type> defines a pipe data width. The return value indicates whether the pipewrite operation is successful. If successful, the return value is 0. If pipe write isunsuccessful, the return value is -1.

The following code snippet demonstrates the implementation of the write_pipe APIcall:

/*Declares the writable nonblocking pipe, p, which contains packets of type int*/__kernel void kernel_write_pipe (__global const long *src, write_only pipe int p){ for (int i=0; i < N; i++) { //Performs the actual writing //Emulates blocking behavior via the use of a while loop while (write_pipe(p, &src[i]) < 0) { } }}

The while loop is unnecessary if you specify a blocking attribute. To facilitate betterhardware implementations, Intel provides facility for blocking write_pipe calls byspecifying the blocking attribute (that is, __attribute__((blocking))) on thepipe arugment declaration for the kernel. Blocking write_pipe calls always returnsuccess.

Caution: When you send data across a blocking write pipe using the write_pipe API call, keepin mind that if the pipe is full (that is, if the FIFO buffer is full of data), your kernel willstall. Use the Intel FPGA SDK for OpenCL Profiler to check for pipe stalls.

Related Links

Profiling Your OpenCL Kernel on page 106The Intel FPGA SDK for OpenCL Profiler measures and reports performance datacollected during OpenCL kernel execution on the FPGA.

1.6.5.5.4 Implementing Pipe Reads

The read_pipe API call allows you to receive data across a pipe.

Intel only supports the convenience version of the read_pipe function. By default,read_pipe calls are nonblocking.

Note: The read pipe calls support single-call sites only. For a given pipe, only one read pipecall to it can exist in the entire kernel program.



• To implement a pipe read, include the following read_pipe function signature:

int read_pipe (read_only_pipe <type> pipe_id, <type> *data);

Where:

pipe_id identifies the buffer to which the pipe connects, and it must match thepipe_id of the corresponding pipe write operation (write_pipe).

data is the data that the pipe read operation reads from the pipe. It is a pointerto the location of the data. Note that write_pipe call might lead to a global orlocal memory load, depending on the source address space of the data pointer.

<type> defines the packet size of the data.

The following code snippet demonstrates the implementation of the read_pipe APIcall:

/*Declares the read_only_pipe that contains packetsof type long.*//*Declares that read_pipe calls within the kernel will exhibitblocking behavior*/__kernel void kernel_read_pipe (__global long *dst, read_only pipe long __attribute__((blocking)) p){ for (int i=0; i < N; i++) { /*Reads from a long from the pipe and stores it into global memory at the specified location*/ read_pipe(p, &dst[i]); }}

To facilitate better hardware implementations, Intel provides facility for blockingwrite_pipe calls by specifying the blocking attribute (that is,__attribute__((blocking))) on the pipe arugment declaration for the kernel.Blocking write_pipe calls always return success.

Caution: If the pipe is empty (that is, if the FIFO buffer is empty), you cannot receive dataacross a blocking read pipe using the read_pipe API call. Doing so causes yourkernel to stall.

1.6.5.5.5 Implementing Buffered Pipes Using the depth Attribute

You may have buffered or unbuffered pipes in your kernel program. If there areimbalances in pipe read and write operations, create buffered pipes to prevent kernelstalls by including the depth attribute in your pipe declaration. Buffered pipesdecouple the operation of concurrent work-items executing in different kernels.

You may use a buffered pipe to control data traffic, such as limiting throughput orsynchronizing accesses to shared memory. In an unbuffered pipe, a write operationcan only proceed when the read operation is expecting to read data. Use unbufferedpipes in conjunction with blocking read and write behaviors in kernels that executeconcurrently. The unbuffered pipes provide self-synchronizing data transfersefficiently.

In a buffered pipe, a write operation can only proceed if there is capacity in the pipe tohold the incoming packet. A read operation can only proceed if there is at least onepacket in the pipe.



Use buffered pipes if pipe calls are predicated differently in the writer and readerkernels, and the kernels do not execute concurrently.

• If you expect any temporary mismatch between the consumption rate and theproduction rate to the pipe, set the buffer size using the depth attribute.

The following example demonstrates the use of the depth attribute in kernel codethat implements the OpenCL pipes. The depth(N) attribute specifies the minimumdepth of a buffered pipe, where N is the number of data values. If the read and writekernels specify different depths for a given buffered pipe, the Intel FPGA SDK forOpenCL Offline Compiler will use the larger depth of the two.

__kernel voidproducer (__global int *in_data, write_only pipe int __attribute__((blocking)) __attribute__((depth(10))) c){ for (i=0; i < N; i++) { if (in_data[i]) { write_pipe( c, &in_data[i] ); } }}

__kernel voidconsumer (__global int *check_data, __global int *out_data, read_only pipe int __attribute__((blocking)) c ) { int last_val = 0; for (i=0; i < N; i++) { if (check_data[i]) { read_pipe( c, &last_val ); } out_data[i] = last_val; }}

In this example, the write operation can write ten data values to the pipe successfully.After the pipe is full, the write kernel returns failure until a read kernel consumessome of the data in the pipe.

Because the pipe read and write calls are conditional statements, the pipe mightexperience an imbalance between read and write calls. You may add a buffer capacityto the pipe to ensure that the producer and consumer kernels are decoupled. Thisstep is particularly important if the producer kernel is writing data to the pipe whenthe consumer kernel is not reading from it.

1.6.5.5.6 Implementing I/O Pipes Using the io Attribute

Include an io attribute in your OpenCL pipe declaration to declare a special I/O pipeto interface with input or output features of an FPGA board.These features might include network interfaces, PCIe, cameras, or other data captureor processing devices or protocols.



In the Intel FPGA SDK for OpenCL channels extension, the io("chan_id") attributespecifies the I/O feature of an accelerator board with which a channel interfaces. Thechan_id argument is the name of the I/O interface listed in the board_spec.xml fileof your Custom Platform. The same I/O features can be used to identify I/O pipes.

Because peripheral interface usage might differ for each device type, consult yourboard vendor's documentation when you implement I/O pipes in your kernel program.Your OpenCL kernel code must be compatible with the type of data generated by theperipheral interfaces. If there is a difference in the byte ordering between the externalI/O pipes and the kernel, the Intel FPGA SDK for OpenCL Offline Compiler converts thebyte ordering seamlessly upon entry and exit.

Cautions: • Implicit data dependencies might exist for pipes that connect to the board directlyand communicate with peripheral devices via I/O pipes. These implicit datadependencies might lead to compilation issues because the offline compiler cannotidentify these dependencies.

• External I/O pipes communicating with the same peripherals do not obey anysequential ordering. Ensure that the external device does not require sequentialordering because unexpected behavior might occur.

1. Consult the board_spec.xml file in your Custom Platform to identify the inputand output features available on your FPGA board.

For example, a board_spec.xml file might include the following information onI/O features:

<channels> <interface name="udp_0" port="udp0_out" type="streamsource" width="256" chan_id="eth0_in"/> <interface name="udp_0" port="udp0_in" type="streamsink" width="256" chan_id="eth0_out"/> <interface name="udp_0" port="udp1_out" type="streamsource" width="256" chan_id="eth1_in"/> <interface name="udp_0" port="udp1_in" type="streamsink" width="256" chan_id="eth1_out"/></channels>

The width attribute of an interface element specifies the width, in bits, of thedata type used by that pipe. For the example above, both the uint and floatdata types are 32 bits wide. Other bigger or vectorized data types must match theappropriate bit width specified in the board_spec.xml file.

2. Implement the io attribute as demonstrated in the following code example. Theio attribute names must match those of the I/O channels (chan_id) specified inthe board_spec.xml file.

__kernel void test (pipe uint pkt __attribute__((io(“enet”))),; pipe float data __attribute__((io(“pcie”))));

Attention: Declare a unique io("chan_id") handle for each I/O pipe specifiedin the channels XML element within the board_spec.xml file.



1.6.5.5.7 Enforcing the Order of Pipe Calls

To enforce the order of pipe calls, introduce memory fence or barrier functions in yourkernel program to control memory accesses. A memory fence function is necessary tocreate a control flow dependence between the pipe synchronization calls before andafter the fence.

When the Intel FPGA SDK for OpenCL Offline Compiler generates a compute unit, itdoes not create instruction-level parallelism on all instructions that are independent ofeach other. As a result, pipe read and write operations might not executeindependently of each other even if there is no control or data dependence betweenthem. When pipe calls interact with each other, or when pipes write data to externaldevices, deadlocks might occur.

For example, the code snippet below consists of a producer kernel and a consumerkernel. Pipes c0 and c1 are unbuffered pipes. The schedule of the pipe readoperations from c0 and c1 might occur in the reversed order as the pipe writeoperations to c0 and c1. That is, the producer kernel writes to c0 but the consumerkernel might read from c1 first. This rescheduling of pipe calls might cause a deadlockbecause the consumer kernel is reading from an empty pipe.

__kernel voidproducer (__global const uint * restrict src, const uint iterations, write_only pipe uint __attribute__((blocking)) c0, write_only pipe uint __attribute__((blocking)) c1){ for (int i=0; i < iterations; i++) { write_pipe( c0, &src[2*i ] ); write_pipe( c1, &src[2*i+1] ); }}

__kernel voidconsumer (__global uint * restrict dst, const uint iterations, read_only pipe uint __attribute__((blocking)) c0, read_only pipe uint __attribute__((blocking)) c1){ for (int i=0; i < iterations; i++) { read_pipe( c0, &dst[2*i+1] ); read_pipe( c1, &dst[2*i] ); }}



• To prevent deadlocks from occurring by enforcing the order of pipe calls, includememory fence functions (mem_fence) in your kernel.

Inserting the mem_fence call with each kernel's pipe flag forces the sequentialordering of the write and read pipe calls. The code snippet below shows themodified producer and consumer kernels:

__kernel voidproducer (__global const uint * src, const uint iterations, write_only_pipe uint __attribute__((blocking)) c0, write_only_pipe uint __attribute__((blocking)) c1){ for(int i=0; i < iterations; i++) { write_pipe(c0, &src[2*i ]); mem_fence(CLK_CHANNEL_MEM_FENCE); write_pipe(c1, &src[2*i+1]); }}

__kernel voidconsumer (__global uint * dst; const uint iterations, read_only_pipe uint __attribute__((blocking)) c0, read_only_pipe uint __attribute__((blocking)) c1){ for(int i=0; i < iterations; i++) { read_pipe(c0, &dst[2*i ]); mem_fence(CLK_CHANNEL_MEM_FENCE); read_pipe(c1, &dst[2*i+1]); }}

In this example, mem_fence in the producer kernel ensures that the pipe writeoperation to c0 occurs before that to c1. Similarly, mem_fence in the consumerkernel ensures that the pipe read operation from c0 occurs before that from c1.

Defining Memory Consistency Across Kernels When Using PipesAccording to the OpenCL Specification version 2.0, memory behavior is undefinedunless a kernel completes execution. A kernel must finish executing before otherkernels can visualize any changes in memory behavior. However, kernels that usepipes can share data through common global memory buffers and synchronizedmemory accesses. To ensure that data written to a pipe is visible to the read pipe afterexecution passes a memory fence, define memory consistency across kernels withrespect to memory fences.



• To create a control flow dependency between the pipe synchronization calls andthe memory operations, add the CLK_GLOBAL_MEM_FENCE flag to the mem_fencecall.

For example:

__kernel voidproducer (__global const uint * restrict src, const uint iterations, write_only pipe uint __attribute__((blocking)) c0, write_only pipe uint __attribute__((blocking)) c1){ for (int i=0;i<iterations;i++) { write_pipe( c0, &src[2*i ] ); mem_fence( CLK_CHANNEL_MEM_FENCE | CLK_GLOBAL_MEM_FENCE ); write_pipe( c1, &src[2*i+1] ); }}

In this kernel, the mem_fence function ensures that the write operation to c0 andmemory access to src[2*i] occur before the write operation to c1 and memoryaccess to src[2*i+1]. This allows data written to c0 to be visible to the readpipe before data is written to c1.

1.6.6 Using Predefined Preprocessor Macros in Conditional Compilation

You may take advantage of predefined preprocessor macros that allow you toconditionally compile portions of your kernel code.

• To include device-specific (for example, FPGA_board_1) code in your kernelprogram, structure your kernel program in the following manner:

#if defined(AOCL_BOARD_FPGA_board_1) //FPGA_board_1-specific statements#else //FPGA_board_2-specific statements#endif

When you target your kernel compilation to a specific board, it sets the predefinedpreprocessor macro AOCL_BOARD_<board_name> to 1. If <board_name> isFPGA_board_1, the Intel FPGA SDK for OpenCL Offline Compiler will compile theFPGA_board_1-specific parameters and features.

• To introduce Intel FPGA SDK for OpenCL Offline Compiler-specific compilerfeatures and optimizations, structure your kernel program in the followingmanner:

#if defined(ALTERA_CL) //statements#else //statements#endif

Where ALTERA_CL is the Intel predefined preprocessor macro for the offlinecompiler.



Related Links

Defining Preprocessor Macros to Specify Kernel Parameters (-D <macro_name>) onpage 93

The Intel FPGA SDK for OpenCL Offline Compiler supports preprocessor macrosthat allow you to pass macro definitions and compile code on a conditional basis.

1.6.7 Declaring __constant Address Space Qualifiers

There are several limitations and workarounds you must consider when you include__constant address space qualifiers in your kernel.

Function Scope __constant Variables

The Intel FPGA SDK for OpenCL Offline Compiler does not support function scope__constant variables. Replace function scope __constant variables with file scopeconstant variables. You can also replace function scope __constant variables with__constant buffers that the host passes to the kernel.

File Scope __constant Variables

If the host always passes the same constant data to your kernel, consider declaringthat data as a constant preinitialized file scope array within the kernel file. Declarationof a constant preinitialized file scope array creates a ROM directly in the hardware tostore the data. This ROM is available to all work-items in the NDRange.

The offline compiler supports only scalar file scope constant data. For example, youmay set the __constant address space qualifier as follows:

__constant int my_array[8] = {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7};

__kernel void my_kernel (__global int * my_buffer){ size_t gid = get_global_id(0); my_buffer[gid] += my_array[gid % 8];}

In this case, the offline compiler sets the values for my_array in a ROM because thefile scope constant data does not change between kernel invocations.

Warning: Do not set your file scope __constant variables in the following manner because theoffline compiler does not support vector type __constant arrays declared at the filescope:

__constant int2 my_array[4] = {(0x0, 0x1), (0x2, 0x3); (0x4,0x5), (0x6, 0x7)};

Pointers to __constant Parameters from the Host

You can replace file scope constant data with a pointer to a __constant parameter inyour kernel code. You must then modify your host application in the following manner:



1. Create cl_mem memory objects associated with the pointers in global memory.

2. Load constant data into cl_mem objects with clEnqueueWriteBuffer prior tokernel execution.

3. Pass the cl_mem objects to the kernel as arguments with the clSetKernelArgfunction.

For simplicity, if a constant variable is of a complex type, use a typedef argument, asshown in the table below:

Table 1. Replacing File Scope __constant Variable with Pointer to __constantParameter

If your source code is structured as follows: Rewrite your code to resemble the following syntax:

__constant int Payoff[2][2] = {{ 1, 3}, {5, 3}};__kernel void original(__global int * A){ *A = Payoff[1][2]; // and so on}

__kernel void modified(__global int * A,__constant Payoff_type * PayoffPtr ){ *A = (PayoffPtr)[1][2]; // and so on}

Attention: Use the same type definition in both your host application and your kernel.

1.6.8 Including Structure Data Types as Arguments in OpenCL Kernels

Convert each structure parameter (struct) to a pointer that points to a structure.

The table below describes how you can convert structure parameters:

Table 2. Converting Structure Parameters to Pointers that Point to Structures

If your source code is structured as follows: Rewrite your code to resemble the following syntax:

struct Context{ float param1; float param2; int param3; uint param4;};

__kernel void algorithm(__global float * A,struct Context c){ if ( c.param3 ) { // statements }}

struct Context{ float param1; float param2; int param3; uint param4;};

__kernel void algorithm(__global float * A,__global struct Context * restrict c){ if ( c->param3 ) { // Dereference through a // pointer and so on }}

Attention: The __global struct declaration creates a new buffer to store the structure. Toprevent pointer aliasing, include a restrict qualifier in the declaration of the pointerto the structure.

1.6.8.1 Matching Data Layouts of Host and Kernel Structure Data Types

If you use structure data types (struct) as arguments in OpenCL kernels, match themember data types and align the data members between the host application and thekernel code.



To match member data types, use the cl_ version of the data type in your hostapplication that corresponds to the data type in the kernel code. The cl_ version ofthe data type is available in the opencl.h header file. For example, if you have adata member of type float4 in your kernel code, the corresponding data memberyou declare in the host application is cl_float4.

Align the structures and align the struct data members between the host and kernelapplications. Manage the alignments carefully because of the variability amongdifferent host compilers.

For example, if you have float 4 OpenCL data types in the struct, the alignments ofthese data items must satisfy the OpenCL specification (that is, 16-byte alignment forfloat4).

The following rules apply when the Intel FPGA SDK for OpenCL Offline Compilercompiles your OpenCL kernels:

1. Alignment of built-in scalar and vector types follow the rules outlined in Section6.1.5 of the OpenCL Specification version 1.0.

The offline compiler usually aligns a data type based on its size. However, thecompiler aligns a value of a three-element vector the same way it aligns a four-element vector.

2. An array has the same alignment as one of its elements.

3. A struct (or a union) has the same alignment as the maximum alignmentnecessary for any of its data members.

Consider the following example:

struct my_struct{ char data[3]; float4 f4; int index;};

The offline compiler aligns the struct elements above at 16-byte boundariesbecause of the float4 data type. As a result, both data and index also have16-byte alignment boundaries.

4. The offline compiler does not reorder data members of a struct.

5. Normally, the offline compiler inserts a minimum amount of data structurepadding between data members of a struct to satisfy the alignmentrequirements for each data member.

a. In your OpenCL kernel code, you may specify data packing (that is, noinsertion of data structure padding) by applying the packed attribute to thestruct declaration. If you impose data packing, ensure that the alignment ofdata members satisfies the OpenCL alignment requirements. The Intel FPGA



SDK for OpenCL does not enforce these alignment requirements. Ensure thatyour host compiler respects the kernel attribute and sets the appropriatealignments.

b. In your OpenCL kernel code, you may specify the amount of data structurepadding by applying the aligned(N) attribute to a data member, where N isthe amount of padding. The SDK does not enforce these alignmentrequirements. Ensure that your host compiler respects the kernel attribute andsets the appropriate alignments.

For Windows systems, some versions of the Microsoft Visual Studio compilerpack structure data types by default. If you do not want to apply data packing,specify an amount of data structure padding as shown below:

struct my_struct{ __declspec(align(16)) char data[3];

/*Note that cl_float4 is the only known float4 definition on the host*/ __declspec(align(16)) cl_float4 f4; __declspec(align(16)) int index;};

Tip: An alternative way of adding data structure padding is to insert dummystruct members of type char or array of char.

Related Links

• Modifying Host Program for Structure Parameter Conversion on page 75If you convert any structure parameters to pointers-to-constant structures inyour OpenCL kernel, you must modify your host application accordingly.

• OpenCL Specification version 1.0

1.6.8.2 Disabling Insertion of Data Structure Padding

You may instruct the Intel FPGA SDK for OpenCL Offline Compiler to disable automaticpadding insertion between members of a struct data structure.

• To disable automatic padding insertion, insert the packed attribute prior to thekernel source code for a struct data structure.

For example:

struct __attribute__((packed)) Context{ float param1; float param2; int param3; uint param4;};__kernel void algorithm(__global float * restrict A, __global struct Context * restrict c){ if ( c->param3 ) { // Dereference through a pointer and so on }}




For more information, refer to the Align a Struct with or without Padding section of theIntel FPGA SDK for OpenCL Best Practices Guide.

Related Links

Align a Struct with or without Padding

1.6.8.3 Specifying the Alignment of a Struct

You may instruct the Intel FPGA SDK for OpenCL Offline Compiler to set a specificalignment of a struct data structure.

• To specify the struct alignment, insert the aligned(N) attribute prior to thekernel source code for a struct data structure.

For example:

struct __attribute__((aligned(2))) Context{ float param1; float param2; int param3; uint param4;};__kernel void algorithm(__global float * A, __global struct Context * restrict c){ if ( c->param3 ) { // Dereference through a pointer and so on }}

For more information, refer to the Align a Struct with or without Padding section of theIntel FPGA SDK for OpenCL Best Practices Guide.

Related Links

Align a Struct with or without Padding

1.6.9 Inferring a Register

The Intel FPGA SDK for OpenCL Offline Compiler can implement data that is in theprivate address space in registers or in block RAMs. In general, the offline compilerchooses registers if the access to a variable is fixed and does not require any dynamicindexes. Accessing an array with a variable index usually forces the array into blockRAMs. Implementing private data as registers is beneficial for data access that occursin a single cycle (for example, feedback in a single work-item loop).

The offline compiler infers private arrays as registers either as single values or in apiecewise fashion. Piecewise implementation results in very efficient hardware;however, the offline compiler must be able to determine data accesses statically. Tofacilitate piecewise implementation, hardcode the access points into the array. You canalso facilitate register inference by unrolling loops that access the array.

If array accesses are not inferable statically, the offline compiler might infer the arrayas registers. However, the offline compiler limits the size of these arrays to 64 bytes inlength for single work-item kernels. There is effectively no size limit for kernels withmultiple work-items.






int array[SIZE];for (int j = 0; j < N; ++j){ for (int i = 0; i < SIZE - 1; ++i) { array[i] = array[i + 1]; }}

The indexing into array[i] is not inferable statically because the loop is not unrolled.If the size of array[SIZE] is less than or equal to 64 bytes for single work-itemkernels, the offline compiler implements array[SIZE] into registers as a singlevalue. If the size of array[SIZE] is greater than 64 bytes for single work-itemkernels, the offline compiler implements the entire array in block RAMs. For multiplework-item kernels, the offline compiler implements array[SIZE] into registers as asingle value as long as its size is less than 1 kilobyte (KB).

1.6.9.1 Inferring a Shift Register

The shift register design pattern is a very important design pattern for manyapplications. However, the implementation of a shift register design pattern mightseem counterintuitive at first.


channel int in, out;

#define SIZE 512//Shift register size must be statically determinable

__kernel void foo(){ int shift_reg[SIZE]; //The key is that the array size is a compile time constant

// Initialization loop #pragma unroll for (int i=0; i < SIZE; i++) { //All elements of the array should be initialized to the same value shift_reg[i] = 0; } while(1) { // Fully unrolling the shifting loop produces constant accesses #pragma unroll for (int j=0; j < SIZE–1; j++) { shift_reg[j] = shift_reg[j + 1]; } shift_reg[SIZE – 1] = read_channel_altera(in);

// Using fixed access points of the shift register int res = (shift_reg[0] + shift_reg[1]) / 2;

// ‘out’ channel will have running average of the input channel write_channel_altera(out, res); }}



In each clock cycle, the kernel shifts a new value into the array. By placing this shiftregister into a block RAM, the Intel FPGA SDK for OpenCL Offline Compiler canefficiently handle multiple access points into the array. The shift register designpattern is ideal for implementing filters (for example, image filters like a Sobel filter ortime-delay filters like a finite impulse response (FIR) filter).

When implementing a shift register in your kernel code, keep in mind the followingkey points:

1. Unroll the shifting loop so that it can access every element of the array.

2. All access points must have constant data accesses. For example, if you write acalculation in nested loops using multiple access points, unroll these loops toestablish the constant access points.

3. Initialize all elements of the array to the same value. Alternatively, you may leavethe elements uninitialized if you do not require a specific initial value.

4. If some accesses to a large array are not inferable statically, they force the offlinecompiler to create inefficient hardware. If these accesses are necessary, use__local memory instead of __private memory.

5. Do not shift a large shift register conditionally. The shifting must occur in very loopiteration that contains the shifting code to avoid creating inefficient hardware.

1.6.10 Enabling Double Precision Floating-Point Operations

The Intel FPGA SDK for OpenCL offers preliminary support for all double precisionfloating-point functions.

Before declaring any double precision floating-point data type in your OpenCL kernel,include the following OPENCL EXTENSION pragma in your kernel code:

#pragma OPENCL EXTENSION cl_khr_fp64 : enable

1.6.11 Single-Cycle Floating-Point Accumulator for Single Work-ItemKernels

Single work-item kernels that perform accumulation in a loop can leverage the IntelFPGA SDK for OpenCL Offline Compiler's single-cycle floating-point accumulatorfeature. The offline compiler searches for these kernel instances and attempts to mapan accumulation that executes in a loop into the accumulator structure.

The offline compiler supports an accumulator that adds or subtracts a value. Toleverage this feature, describe the accumulation in a way that allows the offlinecompiler to infer the accumulator.

Attention: • The accumulator is only available on Arria 10 devices.

• The accumulator must be part of a loop.

• The accumulator must have an initial value of 0.

• The accumulator cannot be conditional.



Below are examples of a description that results in the correct inference of theaccumulator by the offline compiler.


channel float4 RANDOM_STREAM;

__kernel void acc_test(__global float *a, int k) { // Simplest example of an accumulator. // In this loop, the accumulator acc is incremented by 5. int i; float acc = 0.0f; for (i = 0; i < k; i++) { acc+=5; } a[0] = acc;}

__kernel void acc_test2(__global float *a, int k) { // Extended example showing that an accumulator can be // conditionally incremented. The key here is to describe the increment // as conditional, not the accumulation itself. int i; float acc = 0.0f; for (i = 0; i < k; i++) { acc += ((i < 30) ? 5 : 0); } a[0] = acc;}

__kernel void acc_test3(__global float *a, int k) { // A more complex case where the accumulator is fed // by a dot product. int i; float acc = 0.0f; for (i = 0; i < k; i++ ){ float4 v = read_channel_altera(RANDOM_STREAM); float x1 = v.x; float x2 = v.y; float y1 = v.z; float y2 = v.w; acc += (x1*y1+x2*y2); } a[0] = acc;}

__kernel void loader(__global float *a, int k) { int i; float4 my_val = 0; for(i = 0; i < k; i++) { if ((i%4) == 0) write_channel_altera(RANDOM_STREAM, my_val); if ((i%4) == 0) my_val.x = a[i]; if ((i%4) == 1) my_val.y = a[i]; if ((i%4) == 2) my_val.z = a[i]; if ((i%4) == 3) my_val.w = a[i]; }}

1.6.11.1 Programming Strategies for Inferring the Accumulator

To leverage the single cycle floating-point accumulator feature, you can modify theaccumulator description in your kernel code to improve efficiency or work aroundprogramming restrictions.



Describing an Accumulator Using Multiple Loops

Consider a case where you want to describe an accumulator using multiple loops, withsome of the loops being unrolled:

float acc = 0.0f;for (i = 0; i < k; i++) { #pragma unroll for(j=0;j < 16; j++) acc += (x[i+j]*y[i+j]);}

In this situation, it is important to compile the kernel with the --fp-relaxed Intel FPGASDK for OpenCL Offline Compiler command option to enable the offline compiler torearrange the operations in a way that exposes the accumulation. If you do notcompile the kernel with --fp-relaxed, the resulting accumulator structure will havea high initiation interval (II). II is the launch frequency of a new loop iteration. Thehigher the II value, the longer the accumulator structure must wait before it canprocess the next loop iteration.

Modifying a Multi-Loop Accumulator Description

In cases where you cannot compile an accumulator description using the --fp-relaxed offline compiler command option, rewrite the code to expose theaccumulation.

For the code example above, rewrite it in the following manner:

float acc = 0.0f;for (i = 0; i < k; i++) { float my_dot = 0.0f; #pragma unroll for(j=0;j < 16; j++) my_dot += (x[i+j]*y[i+j]); acc += my_dot;}

Modifying an Accumulator Description Containing a Variable or Non-ZeroInitial Value

Consider a situation where you might want to apply an offset to a description of anaccumulator that begins with a non-zero value:

float acc = array[0];for (i = 0; i < k; i++) { acc += x[i];}

Because the accumulator hardware does not support variable or non-zero initial valuesin a description, you must rewrite the description.

float acc = 0.0f;for (i = 0; i < k; i++) { acc += x[i];}acc += array[0];



Rewriting the description in the above manner enables the kernel to use anaccumulator in a loop. The loop structure is then followed by an increment ofarray[0].

1.7 Designing Your Host Application

Intel offers guidelines on host requirements and procedures on structuring the hostapplication. If applicable, implement these design strategies when you create ormodify a host application for your OpenCL kernels.

Host Programming Requirements on page 68When designing your OpenCL host application for use with the Intel FPGA SDK forOpenCL, ensure that the application satisfies the following host programmingrequirements.

Allocating OpenCL Buffer for Manual Partitioning of Global Memory on page 69

Collecting Profile Data During Kernel Execution on page 72In cases where kernel execution finishes after the host application completes, youcan query the FPGA explicitly to collect profile data during kernel execution.

Accessing Custom Platform-Specific Functions on page 74To reference Custom Platform-specific user-accessible functions while linking to theACD, include the clGetBoardExtensionFunctionAddressAltera extension inyour host application.

Modifying Host Program for Structure Parameter Conversion on page 75If you convert any structure parameters to pointers-to-constant structures in yourOpenCL kernel, you must modify your host application accordingly.

Managing Host Application on page 76The Intel FPGA SDK for OpenCL includes utility commands you can invoke to obtaininformation on flags and libraries necessary for compiling and linking your hostapplication.

Allocating Shared Memory for OpenCL Kernels Targeting SoCs on page 87Intel recommends that OpenCL kernels that run on Intel SoCs access sharedmemory instead of the FPGA DDR memory.

1.7.1 Host Programming Requirements

When designing your OpenCL host application for use with the Intel FPGA SDK forOpenCL, ensure that the application satisfies the following host programmingrequirements.

1.7.1.1 Host Machine Memory Requirements

The machine that runs the host application must have enough host memory to supportseveral components simultaneously.

The host machine must support the following components:



• The host application and operating system.

• The working set for the host application.

• The maximum amount of OpenCL memory buffers that can be allocated at once.Every device-side cl_mem buffer is associated with a corresponding storage areain the host process. Therefore, the amount of host memory necessary might be aslarge as the amount of external memory supported by the FPGA.

1.7.1.2 Host Binary Requirement

When compiling the host application, target one of these architectures: x86-64 (64-bit) or ARM® 32-bit ARMV7-A for SoCs. The Intel FPGA SDK for OpenCL host runtimedoes not support x86-32 (32-bit) binaries.

1.7.1.3 Multiple Host Threads

The Intel FPGA SDK for OpenCL host library is thread-safe.

All OpenCL APIs are thread safe except the clSetKernelArg function.

It is safe to call clSetKernelArg from any host thread or as an reentrant as long asconcurrent calls to any combination of clSetKernelArg calls operate on differentcl_kernel objects.

Related Links

Multi-Threaded Host Application

1.7.1.4 Out-of-Order Command Queues

The OpenCL host runtime command queues do not support out-of-order commandexecution.

1.7.1.5 Requirement for Multiple Command Queues in Channels or PipesImplementation

Although the Intel FPGA SDK for OpenCL channels extension or OpenCL pipesimplementation allows multiple kernels to execute in parallel, channels or pipesfacilitate this concurrent behavior only when cl_command_queue objects are in order.To enable multiple command queues , instantiate a separate command for each kernelyou wish to run concurrently.

1.7.2 Allocating OpenCL Buffer for Manual Partitioning of Global Memory

Manual partitioning of global memory buffers allows you to control memory accessesacross buffers to maximize the memory bandwidth. Before you partition the memory,first you have to disable burst-interleaving during OpenCL kernel compilation. Then, inthe host application, you must specify the memory bank to which you allocate theOpenCL buffer.

By default, the Intel FPGA SDK for OpenCL Offline Compiler configures each globalmemory type in a burst-interleaved fashion. Usually, the burst-interleavingconfiguration leads to the best load balancing between the memory banks. However,there might be situations where it is more efficient to partition the memory into non-interleaved regions.




The figure below illustrates the differences between burst-interleaved and non-interleaved memory partitions.

0x7FFF_FFFFAddress

0x7FFF_FC000x7FFF_FBFF

0x7FFF_F800

0x0000_0FFF

0x0000_0C000x0000_0BFF

0x0000_08000x0000_07FF

0x0000_04000x0000_03FF

0x0000_0000

Bank 2

Bank 1

Bank 2

Bank 1

Bank 2

Bank 1

Bank 2

Bank 1

Address0x7FFF_FFFF

0x4000_00000x3FFF_FFFF

0x0000_0000

Burst-Interleaved Separate Partitions

To manually partition some or all of the available global memory types, perform thefollowing tasks:

1. Compile your OpenCL kernel using the --no-interleaving<global_memory_type> flag to configure the memory bank(s) of the specifiedmemory type as separate addresses.

For more information on the usage of the --no-interleaving<global_memory_type> flag, refer to the Disabling Burst-Interleaving of GlobalMemory (--no-interleaving <global_memory_type>) section.

2. Create an OpenCL buffer in your host application, and allocate the buffer to one ofthe banks using the CL_MEM_HETEROGENEOUS_ALTERA and CL_MEM_BANK flags.

— Specify CL_MEM_BANK_1_ALTERA to allocate the buffer to the lowest availablememory region.

— Specify CL_MEM_BANK_2_ALTERA to allocation memory to the second bank (ifavailable).

Attention: Allocate each buffer to a single memory bank only.

By default, the host allocates buffers into the main memory when you load kernelsinto the OpenCL runtime via the clCreateProgramWithBinary function. Duringkernel invocation, the host automatically relocates heterogeneous memory buffersthat are bound to kernel arguments to the main memory . To avoid the initial



allocation of heterogeneous memory buffers in the main memory, include theCL_MEM_HETEROGENEOUS_ALTERA flag when you call the clCreateBufferfunction, as shown below:

mem = clCreateBuffer(context, flags|CL_MEM_HETEROGENEOUS_ALTERA, memSize, NULL, &errNum);

For example, the following clCreateBuffer call allocates memory into thelowest available memory region of a nondefault memory bank:

mem = clCreateBuffer(context, (CL_MEM_HETEROGENEOUS_ALTERA|CL_MEM_BANK_1_ALTERA), memSize, NULL, &errNum);

The clCreateBuffer call allocates memory into a certain global memory typebased on what you specify in the kernel argument. If a memory (cl_mem) objectresiding in a memory type is set as a kernel argument that corresponds to adifferent memory technology, the host moves the memory object automaticallywhen it queues the kernel. Do not pass a buffer as kernel arguments thatassociate it with multiple memory technologies.

Attention: If the second bank is not available at runtime, the memory is allocated to the firstbank. If no global memory is available, the clCreateBuffer call fails with the errormessage CL_MEM_OBJECT_ALLOCATION_FAILURE.

For more information on optimizing heterogeneous global memory accesses, refer tothe Heterogeneous Memory Buffers and the Manual Partitioning of Global Memorysections of the Intel FPGA SDK for OpenCL Best Practices Guide.

Related Links

• Disabling Burst-Interleaving of Global Memory (--no-interleaving<global_memory_type>) on page 97

You can disable burst-interleaving for all global memory banks of the sametype and manage them manually by including the --no-interleaving<global_memory_type> option in your aoc command.

• Manual Partitioning of Global Memory

• Heterogeneous Memory Buffers

1.7.2.1 Creating a Pipe Object in Your Host Application

To implement OpenCL pipes in your kernel, you must create Intel FPGA SDK forOpenCL-specific pipe objects in your host application.

An SDK-specific pipe object is not a true OpenCL pipe object as described in theOpenCL Specification version 2.0. This implementation allows you to migrate awayfrom Intel FPGA products with a conformant solution. The SDK-specific pipe object is amemory object (cl_mem); however, the host does not allocate any memory for thepipe itself.





The following clCreatePipe host API creates a pipe object:

cl_mem clCreatePipe(cl_context context, cl_mem_flags flags, cl_uint pipe_packet_size, cl_uint pipe_max_packets, const cl_pipe_properties *properties, cl_int *errcode_ret)

For more information on the clCreatePipe host API function, refer to section 5.4.1of the OpenCL Specification version 2.0.

Below is an example syntax of the clCreatePipe host API function:

cl_int status;cl_mem c0_pipe = clCreatePipe(context, 0, sizeof(int), 1, NULL, &status);status = clSetKernelArg(kernel, 1, sizeof(cl_mem), &c0_pipe);

Caution: The SDK does not support dynamic channel assignment at runtime. The SDK staticallylinks the pipes during compilation.

Related Links


1.7.3 Collecting Profile Data During Kernel Execution

In cases where kernel execution finishes after the host application completes, you canquery the FPGA explicitly to collect profile data during kernel execution.

When you profile your OpenCL kernel during compilation, a profile.mon file isgenerated automatically. The profile data is then written to profile.mon after kernelexecution completes on the FPGA. However, if kernel execution completes after thehost application completes, no profiling information for that kernel invocation will beavailable in the profile.mon file. In this case, you can modify your host code toacquire profiling information during kernel execution.




• To query the FPGA to collect profile data while the kernel is running, call thefollowing host library call:

extern CL_API_ENTRY cl_int CL_API_CALL

clGetProfileInfoAltera(cl_event);

where cl_event is the kernel event. The kernel event you pass to this hostlibrary call must be the same one you pass to the clEnqueueNDRangeKernelcall.

Important: If kernel execution completes before the invocation ofclGetProfileInfoAltera, the function returns an event errormessage.

Caution: Invoking the clGetProfileInfoAltera function during kernelexecution disables the profile counters momentarily so that the Profilercan collect data from the FPGA. As a result, you will lose some profilinginformation during this interruption. If you call this function at veryshort intervals, the profile data might not accurately reflect the actualperformance behavior of the kernel.

Consider the following example host code:

int main(){ ... clEnqueueNDRangeKernel (queue, kernel, ..., NULL); ... clEnqueueNDRangeKernel (queue, kernel, .. , NULL); ...}

This host application runs on the assumption that a kernel launches twice andthen completes. In the profile.mon file, there will be two sets of profile data,one for each kernel invocation. To collect profile data while the kernel is running,modify the host code in the following manner:

int main(){ ... clEnqueueNDRangeKernel (queue, kernel, ..., &event);

//Get the profile data before the kernel completes clGetProfileInfoAltera (event);

//Wait until the kernel completes clFinish (queue);

... clEnqueueNDRangeKernel (queue, kernel, ..., NULL); ...}

The call to clGetProfileInfoAltera adds a new entry in the profile.monfile. The Profiler GUI then parses this entry in the report.

For more information on the Intel FPGA SDK for OpenCL Profiler, refer to the followingsections:



• Profile Your Kernel to Identify Performance Bottlenecks in the Intel FPGA SDK forOpenCL Best Practices Guide

• Profiling Your OpenCL Kernel

Related Links

• Profile Your Kernel to Identify Performance Bottlenecks

• Profiling Your OpenCL Kernel on page 106The Intel FPGA SDK for OpenCL Profiler measures and reports performancedata collected during OpenCL kernel execution on the FPGA.

1.7.4 Accessing Custom Platform-Specific Functions

You have the option to include in your application user-accessible functions that areavailable in your Custom Platform. However, when you link your host applicaiton to theAltera Client Driver (ACD), you cannot directly reference these Custom Platform-specific functions. To reference Custom Platform-specific user-accessible functionswhile linking to the ACD, include theclGetBoardExtensionFunctionAddressAltera extension in your hostapplication.

The clGetBoardExtensionFunctionAddressAltera extension specifies an APIthat retrieves a pointer to a user-accessible function from the Custom Platform.

Attention: For Linux systems, the clGetBoardExtensionFunctionAddressAltera functionworks with or without ACD. For Windows systems, the function only works inconjunction with ACD. Consult with your board vendor to determine if ACD issupported in your Custom Platform.

Definitions of the extension interfaces are available in the ALTERAOCLSDKROOT/host/include/CL/cl_ext.h file.




• To obtain a pointer to a user-accessible function in your Custom Platform, call thefollowing function in your host application:

void* clGetBoardExtensionFunctionAddressAltera ( const char* function_name, cl_device_id device );

Where:

function_name is the name of the user-accessible function that your CustomPlatform vendor provides,

and

device is the device ID returned by the clGetDeviceIDs function.

After locating the user-accessible function, theclGetBoardExtensionFunctionAddressAltera function returns a pointer tothe user-accessible function. If the function does not exist in the Custom Platform,clGetBoardExtensionFunctionAddressAltera returns NULL.

Attention: To access the clGetBoardExtensionFunctionAddressAltera APIvia the Installable Client Driver (ICD), ensure that the ICD extensionAPI clGetExtensionFunctionAddress retrieves the pointer to theclGetBoardExtensionFunctionAddressAltera API first.

The following code example shows how you can access the CustomPlatform-specific function via ICD:

typedef void* (*get_board_extension_function_address_fn_t) (const char* func_name, cl_device_id device);

get_board_extension_function_address_fn_t get_board_extension_function_address = (get_board_extension_function_address_fn_t) clGetExtensionFunctionAddress ("clGetBoardExtensionFunctionAddressAltera");

if (get_board_extension_function_address == NULL ) { printf ("Failed to get clGetBoardExtensionFunctionAddressAltera \n");}

void *board_extension_function_ptr = get_board_extension_function_address("function_name",device_id);

1.7.5 Modifying Host Program for Structure Parameter Conversion

If you convert any structure parameters to pointers-to-constant structures in yourOpenCL kernel, you must modify your host application accordingly.

Perform the following changes to your host application:

1. Allocate a cl_mem buffer to store the structure contents.



Attention: You need a separate cl_mem buffer for every kernel that uses adifferent structure value.

2. Set the structure kernel argument with a pointer to the structure buffer, not with apointer to the structure contents.

3. Populate the structure buffer contents before queuing the kernel. Perform one ofthe following steps to ensure that the structure buffer is populated before thekernel launches:

— Queue the structure buffer on the same command queue as the kernel queue.

— Synchronize separate kernel queues and structure buffer queues with anevent.

4. When your application no longer needs to call a kernel that uses the structurebuffer, release the cl_mem buffer.

Related Links

• Including Structure Data Types as Arguments in OpenCL Kernels on page 60Convert each structure parameter (struct) to a pointer that points to astructure.

• Matching Data Layouts of Host and Kernel Structure Data Types on page 60If you use structure data types (struct) as arguments in OpenCL kernels,match the member data types and align the data members between the hostapplication and the kernel code.

1.7.6 Managing Host Application

The Intel FPGA SDK for OpenCL includes utility commands you can invoke to obtaininformation on flags and libraries necessary for compiling and linking your hostapplication.

Attention: To cross-compile your host application to an SoC FPGA board, include the --armoption in your utility command.

Caution: For Linux systems, if you debug your host application using the GNU Project Debugger(GDB), invoke the following command prior to running the host application:

handle SIG44 nostop

Without this command, the GDB debugging process terminates with the followingerror message:

Program received signal SIG44, Real-time event 44.

1.7.6.1 Displaying Example Makefile Fragments (example-makefile or makefile)

To display example Makefile fragments for compiling and linking a host applicationagainst host runtime libraries available with the Intel FPGA SDK for OpenCL, invokethe example-makefile or makefile utility command.



• At a command prompt, invoke the aocl example-makefile or aoclmakefile utility command.The software displays an output similar to the following:

The following are example Makefile fragments for compiling and linkinga host program against the host runtime libraries included with theIntel FPGA SDK for OpenCL.

Example GNU makefile on Linux, with GCC toolchain:

AOCL_COMPILE_CONFIG=$(shell aocl compile-config) AOCL_LINK_CONFIG=$(shell aocl link-config)

host_prog : host_prog.o g++ -o host_prog host_prog.o $(AOCL_LINK_CONFIG)

host_prog.o : host_prog.cpp g++ -c host_prog.cpp $(AOCL_COMPILE_CONFIG)

Example GNU makefile on Windows, with Microsoft Visual C++ command line compiler:

AOCL_COMPILE_CONFIG=$(shell aocl compile-config) AOCL_LINK_CONFIG=$(shell aocl link-config)

host_prog.exe : host_prog.obj link -nologo /OUT:host_prog.exe host_prog.obj $(AOCL_LINK_CONFIG)

host_prog.obj : host_prog.cpp cl /MD /Fohost_prog.obj -c host_prog.cpp $(AOCL_COMPILE_CONFIG)

Example GNU makefile cross-compiling to ARM SoC from Linux or Windows, withLinaro GCC cross-compiler toolchain:

CROSS-COMPILER=arm-linux-gnueabihf- AOCL_COMPILE_CONFIG=$(shell aocl compile-config --arm) AOCL_LINK_CONFIG=$(shell aocl link-config --arm)

host_prog : host_prog.o $(CROSS-COMPILER)g++ -o host_prog host_prog.o $(AOCL_LINK_CONFIG)

host_prog.o : host_prog.cpp $(CROSS-COMPILER)g++ -c host_prog.cpp $(AOCL_COMPILE_CONFIG)

1.7.6.2 Compiling and Linking Your Host Application

The OpenCL host application uses standard OpenCL runtime APIs to manage deviceconfiguration, data buffers, kernel launches, and synchronization. The host applicationalso contains functions such as file I/O, or portions of the source code that do not runon an accelerator device. The Intel FPGA SDK for OpenCL includes utility commandsyou can invoke to obtain information on C header files describing the OpenCL APIs,and board-specific MMD and host runtime libraries with which you must link your hostapplication.

Important: For Windows systems, you must add the /MD flag to link the host runtime librariesagainst the multithreaded dynamic link library (DLL) version of the Microsoft CRuntime library. You must also compile your host application with the /MD compilationflag, or use the /NODEFAULTLIB linker option to override the selection of runtimelibrary.



Remember: Include the path to the ALTERAOCLSDKROOT/host/<OS_platform>/bin folder inyour library search path when you run your host application.

Displaying Flags for Compiling Host Application (compile-config) on page 78To display a list of flags necessary for compiling a host application, invoke thecompile-config utility command.

Displaying Paths to OpenCL Host Runtime and MMD Libraries (ldflags) on page 78To display the paths necessary for linking a host application to the OpenCL hostruntime and MMD libraries, invoke the ldflags utility command.

Listing OpenCL Host Runtime and MMD Libraries (ldlibs) on page 79To display the names of the OpenCL host runtime and MMD libraries necessary forlinking a host application, invoke the ldlibs utility command.

Displaying Information on OpenCL Host Runtime and MMD Libraries (link-config orlinkflags) on page 79

To display a list of flags necessary for linking a host application with OpenCL hostruntime and MMD libraries, invoke the link-config or linkflags utilitycommand.

1.7.6.2.1 Displaying Flags for Compiling Host Application (compile-config)

To display a list of flags necessary for compiling a host application, invoke thecompile-config utility command.

1. At a command prompt, invoke the aocl compile-config utility command.The software displays the path to the folder or directory in which the OpenCL APIheader files reside. For example:

• For Windows systems, the path is -I%ALTERAOCLSDKROOT%/host/include

• For Linux systems, the path is -I$ALTERAOCLSDKROOT/host/include

where ALTERAOCLSDKROOT points to the location of the software installation.

2. Add this path to your C preprocessor.

Attention: In your host source, include the opencl.h OpenCL header file, located in theALTERAOCLSDKROOT/host/include/CL folder or directory.

1.7.6.2.2 Displaying Paths to OpenCL Host Runtime and MMD Libraries (ldflags)

To display the paths necessary for linking a host application to the OpenCL hostruntime and MMD libraries, invoke the ldflags utility command.

• At a command prompt, invoke the aocl ldflags utility command.The software displays the paths for linking your host application with the followinglibraries:

1. The OpenCL host runtime libraries that provide OpenCL platform and runtimeAPIs. The OpenCL host runtime libraries are available in theALTERAOCLSDKROOT/host/<OS_platform>/lib directory.

2. The path to the Custom Platform-specific MMD libraries. The MMD libraries areavailable in the <board_family_name>/<OS_platform>/lib directory ofyour Custom Platform.



1.7.6.2.3 Listing OpenCL Host Runtime and MMD Libraries (ldlibs)

To display the names of the OpenCL host runtime and MMD libraries necessary forlinking a host application, invoke the ldlibs utility command.

• At a command prompt, invoke the aocl ldlibs utility command.The software lists the OpenCL host runtime libraries residing in theALTERAOCLSDKROOT/host/<OS_platform>/lib directory. It also lists theCustom Platform-specific MMD libraries residing in the /<board_family_name>/<OS_platform>/lib directory of your Custom Platform.

— For Windows systems, the output might resemble the following example:

alterahalmmd.lib<board_vendor_name>_<board_family_name>_mmd.[lib|so|a|dll]alteracl.libacl_emulator_kernel_rt.libpkg_editor.liblibelf.libacl_hostxml.lib

— For Linux systems, the output might resemble the following example:

-lalteracl-ldl-lacl_emulator_kernel_rt-lalterahalmmd-l<board_vendor_name>_<board_family_name>_mmd-lelf-lrt-lstdc++

1.7.6.2.4 Displaying Information on OpenCL Host Runtime and MMD Libraries (link-configor linkflags)

To display a list of flags necessary for linking a host application with OpenCL hostruntime and MMD libraries, invoke the link-config or linkflags utility command.

This utility command combines the functions of the ldflags and ldlibs utilitycommands.

1. At a command prompt, invoke the aocl link-config or aocl linkflagscommand.The software displays the link options for linking your host application with thefollowing libraries:

a. The path to and the names of OpenCL host runtime libraries that provideOpenCL platform and runtime APIs. The OpenCL host runtime libraries areavailable in the ALTERAOCLSDKROOT/host/<OS_platform>/lib directory .

b. The path to and the names of the Custom Platform-specific MMD libraries. TheMMD libraries are available in the <board_family_name>/<OS_platform>/lib directory of your Custom Platform.



• For Windows systems, the link options might resemble the following exampleoutput:

/libpath:%ALTERAOCLSDKROOT%/board/<board_name>/windows64/lib/libpath:%ALTERAOCLSDKROOT%/host/windows64/libalterahalmmd.lib<board_vendor_name>_<board_family_name>_mmd.[lib|so|a|dll]alteracl.libacl_emulator_kernel_rt.libpkg_editor.liblibelf.libacl_hostxml.lib

• For Linux systems, the link options might resemble the following exampleoutput:

-L/$ALTERAOCLSDKROOT/board/<board_name>/linux64/lib-L/$ALTERAOCLSDKROOT/host/linux64/lib-lalterac-ldl-lacl_emulator_kernel_rt-lalterahalmmd-l<board_vendor_name>_<board_family_name>_mmd-lelf-lrt-lstdc++

1.7.6.3 Linking Your Host Application to the Khronos ICD Loader Library

The Intel FPGA SDK for OpenCL supports the OpenCL ICD extension from the KhronosGroup. The OpenCL ICD extension allows you to have multiple OpenCLimplementations on your system. With the OpenCL ICD Loader Library, you maychoose from a list of installed platforms and execute OpenCL API calls that are specificto your OpenCL implementation of choice.

In addition to the SDK's host runtime libraries, Intel supplies a version of the ICDLoader Library that supports the OpenCL Specification version 1.0 and theimplemented APIs from the OpenCL Specification versions 1.1, 1.2, and 2.0. To use anICD library from another vendor, consult the vendor's documentation on how to link totheir ICD library.

Linking to the ICD Loader Library on Windows on page 80To link your Windows OpenCL host application to the ICD Loader Library, modifythe Makefile and set up the Altera Client Driver.

Linking to the ICD Loader Library on Linux on page 81To link your Linux OpenCL host application to the ICD Loader Library, modify theMakefile. For Cyclone V SoC boards, you also have to create an Altera.icdfile.

1.7.6.3.1 Linking to the ICD Loader Library on Windows

To link your Windows OpenCL host application to the ICD Loader Library, modify theMakefile and set up the Altera Client Driver.

Attention: For Windows systems, you must use the ICD in conjunction with the ACD. If thecustom platform from your board vendor does not currently support ACD, you can setit up manually.



1. Prior to linking your host application to any Intel FPGA SDK for OpenCL hostruntime libraries, link it to the OpenCL library by modifying the Makefile.

A modified Makefile might include the following lines:

AOCL_COMPILE_CONFIG=$(shell aocl compile-config)AOCL_LDFLAGS=$(shell aocl ldflags)AOCL_LDLIBS=$(shell aocl ldlibs)

host_prog.exe : host_prog.obj link -nologo /OUT:host_prog.exe host_prog.obj $(AOCL_ LDFLAGS) OpenCL.lib

host_prog.obj : host_prog.cpp cl /MD /Fohost_prog.obj -c host_prog.cpp $(AOCL_COMPILE_CONFIG)

2. If you need to manually set up ACD support for your Custom Platform, performthe following tasks:

a. Consult with your board vendor to identify the libraries that the ACD requires.Alternatively, you may invoke the aocl ldlibs command and identify thelibraries that your OpenCL application requires.

b. Specify the libraries in the registry key HKEY_LOCAL_MACHINE\SOFTWARE\Altera\OpenCL\Boards. Specify the value name to be thepath to the library, and specify the data to be a DWORD that is set to 0.

Attention: If your board vendor provides multiple libraries, you might need toload them in a particular order. Consult with your board vendor todetermine the correct order to load the libraries. List the librariesin the registry in their loading order.

To enumerate board vendor-specific ICDs, the ICD Loader scans the values in theHKEY_LOCAL_MACHINE\SOFTWARE\Altera\OpenCL\Boards registry key. Foreach DWORD value that is set to 0, the ACD Loader opens the corresponding DLL thatis specified in the value name.

Consider the following registry key value:

[HKEY_LOCAL_MACHINE\SOFTWARE\Altera\OpenCL\Boards] "c:\board_vendor a\my_board_mmd.dll"=dword:00000000

The ICD Loader scans this value, and then the ACD Loader opens the librarymy_board_mmd.dll from the board_vendor a folder.

Attention: If your host application fails to run while it is linking to the ICD, ensure that theHKEY_LOCAL_MACHINE\SOFTWARE\Khronos\OpenCL\Vendors registry keycontains the following value:

[HKEY_LOCAL_MACHINE\SOFTWARE\Khronos\OpenCL\Vendors]"alteracl_icd.dll"=dword:00000000

1.7.6.3.2 Linking to the ICD Loader Library on Linux

To link your Linux OpenCL host application to the ICD Loader Library, modify theMakefile. For Cyclone V SoC boards, you also have to create an Altera.icd file.

1. Prior to linking your host application to any Intel FPGA SDK for OpenCL hostruntime libraries, link it to the OpenCL library by modifying the Makefile.



A modified Makefile might include the following lines:

AOCL_LDFLAGS=$(shell aocl ldflags)AOCL_LDLIBS=$(shell aocl ldlibs)

host_prog : host_prog.og++ -o host_prog host_prog.o $(AOCL_LDFLAGS) -lOpenCL $(AOCL_LDLIBS)

2. For Cyclone V SoC boards, when you build the SD flash card image for yourCustom Platform, create an Altera.icd file containing the textlibalteracl.so. Store the Altera.icd file in the /etc/OpenCL/vendorsdirectory of your Custom Platform.

Refer to Building an SD Flash Card Image section of the Intel FPGA SDK forOpenCL Cyclone V SoC Development Kit Reference Platform Porting Guide formore information.

Attention: If your host application fails to run while linking to the ICD, ensure that the file /etc/OpenCL/vendors/Altera.icd matches the file found in the directory thatALTERAOCLSDKROOT specifies. The environment variable ALTERAOCLSDKROOT pointsto the location of the SDK installation. If the files do not match, or if it is missingfrom /etc/OpenCL/vendors, copy the Altera.icd file from ALTERAOCLSDKROOTto /etc/OpenCL/vendors.

Related Links

Building an SD Flash Card Image

1.7.6.4 Programming an FPGA via the Host

The Intel FPGA SDK for OpenCL Offline Compiler is an offline compiler that compileskernels independently of the host application. To load the kernels into the OpenCLruntime, include the clCreateProgramWithBinary function in your hostapplication.

Caution: If your host system consists of multiple processors, only one processor can access theFPGA at a given time. Consider an example where there are two host applications,corresponding to two processors, attempting to launch kernels onto the same FPGA atthe same time. The second host application wil receive an error message indicatingthat the device is busy. The second host application cannot run until the first hostapplication releases the OpenCL context.

1. Compile your OpenCL kernel with the offline compiler to create the .aocx file.

2. Include the clCreateProgramWithBinary function in your host application tocreate the cl_program OpenCL program objects from the .aocx file.

3. Include the clBuildProgram function in your host application to create theprogram executable for the specified device.

Below is an example host code on using clCreateProgramWithBinary toprogram an FPGA device:

size_t lengths[1];unsigned char* binaries[1] ={NULL};cl_int status[1];cl_int error;cl_program program;




const char options[] = "";

FILE *fp = fopen("program.aocx","rb");fseek(fp,0,SEEK_END);lengths[0] = ftell(fp);binaries[0] = (unsigned char*)malloc(sizeof(unsigned char)*lengths[0]);rewind(fp);fread(binaries[0],lengths[0],1,fp);fclose(fp);

program = clCreateProgramWithBinary(context, 1, device_list, lengths, (const unsigned char **)binaries, status, &error);clBuildProgram(program,1,device_list,options,NULL,NULL);

If the clBuildProgram function executes successfully, it returns CL_SUCCESS.

4. Create kernel objects from the program executable using theclCreateKernelsInProgram or clCreateKernel function.

5. Include the kernel execution function to instruct the host runtime to execute thescheduled kernel(s) on the FPGA.

— To enqueue a command to execute an NDRange kernel, useclEnqueueNDRangeKernel.

— To enqueue a single work-item kernel, use clEnqueueTask.

Attention: Intel recommends that you release an event object when it is not inuse. The SDK keeps an event object live until you explicitly instruct itto release the event object. Keeping an unused event object livecauses unnecessary memory usage.

To release an event object, call the clReleaseEvent function.

You can load multiple FPGA programs into memory, which the host then uses toreprogram the FPGA as required.

For more information on these OpenCL host runtime API calls, refer to the OpenCLSpecification version 1.0.

Related Links

OpenCL Specification version 1.0

1.7.6.4.1 Programming Multiple FPGA Devices

If you install multiple FPGA devices in your system, you can direct the host runtime toprogram a specific FPGA device by modifying your host code.

Important: By default, you may only program multiple FPGA devices from the same CustomPlatform because the AOCL_BOARD_PACKAGE_ROOT environment variable points tothe location of a single Custom Platform.

Linking your host application to ACD allows you to target multiple FPGA devices fromdifferent Custom Platforms. However, this feature has limited support for CustomPlatforms that are compatible with SDK versions prior to 16.1.

You can present up to 32 FPGA devices to your system in the following manner:




• Multiple FPGA accelerator boards, each consisting of a single FPGA.

• Multiple FPGAs on a single accelerator board that connects to the host system viaa PCIe switch.

• Combinations of the above.

The host runtime can load kernels onto each and every one of the FPGA devices. TheFPGA devices can then operate in a parallel fashion.

1. Probing the OpenCL FPGA Devices on page 84The host must identify the number of OpenCL FPGA devices installed into thesystem.

2. Querying Device Information on page 85You can direct the host to query information on your OpenCL FPGA devices.

3. Loading Kernels for Multiple FPGA Devices on page 85If your system contains multiple FPGA devices, you can create specificcl_program objects for each FPGA and load them into the OpenCL runtime.

Related Links

Accessing Custom Platform-Specific Functions on page 74To reference Custom Platform-specific user-accessible functions while linking to theACD, include the clGetBoardExtensionFunctionAddressAltera extension inyour host application.

Probing the OpenCL FPGA DevicesThe host must identify the number of OpenCL FPGA devices installed into the system.

1. To query a list of FPGA devices installed in your machine, invoke the aocldiagnose command.

2. To direct the host to identify the number of OpenCL FPGA devices, add thefollowing lines of code to your host application:

//Get the platformciErrNum = clGetPlatformID(&cpPlatform);

//Get the devicesciErrNum = clGetDeviceIDs(cpPlatform, CL_DEVICE_TYPE_ALL, 0, NULL, &ciDeviceCount);cdDevices = (cl_device_id * )malloc(ciDeviceCount * sizeof(cl_device_id));ciErrNum = clGetDeviceIDs(cpPlatform, CL_DEVICE_TYPE_ALL, ciDeviceCount, cdDevices, NULL);

For example, on a system with two OpenCL FPGA devices, ciDeviceCount has avalue of 2, and cdDevices contains a list of two device IDs (cl_device_id).

Related Links

Querying the Device Name of Your FPGA Board (diagnose) on page 17When you query a list of accelerator boards, the OpenCL software produces a list ofinstalled devices on your machine in the order of their device names.



Querying Device InformationYou can direct the host to query information on your OpenCL FPGA devices.

• To direct the host to output a list of OpenCL FPGA devices installed into yoursystem, add the following lines of code to your host application:

char buf[1024];for (unsigned i = 0; i < ciDeviceCount; i++);{ clGetDeviceInfo(cdDevices[i], CL_DEVICE_NAME, 1023, buf, 0); printf("Device %d: '%s'\n", i, buf);}

When you query the device information, the host will list your FPGA devices in thefollowing manner: Device <N>: <board_name>: <name_of_FPGA_board>

Where:

• <N> is the device number.

• <board_name> is the board designation you use to target your FPGA device whenyou invoke the aoc command.

• <name_of_FPGA_board> is the advertised name of the FPGA board.

For example, if you have two identical FPGA boards on your system, the hostgenerates an output that resembles the following:

Device 0: board_1: Stratix V FPGA BoardDevice 1: board_1: Stratix V FPGA Board

Note: The clGetDeviceInfo function returns the board type (for example, board_1) thatthe Intel FPGA SDK for OpenCL Offline Compiler lists on-screen when you invoke theaoc --list-boards command. If your accelerator board contains more than oneFPGA, each device is treated as a "board" and is given a unique name.

Related Links

Listing the Available FPGA Boards in Your Custom Platform (--list-boards) on page 13To list the FPGA boards available in your Custom Platform, include the --list-boards option in the aoc command.

Loading Kernels for Multiple FPGA DevicesIf your system contains multiple FPGA devices, you can create specific cl_programobjects for each FPGA and load them into the OpenCL runtime.

The following host code demonstrates the usage of theclCreateProgramWithBinary and createMultiDeviceProgram functions toprogram multiple FPGA devices:

cl_program createMultiDeviceProgram(cl_context context, const cl_device_id *device_list, cl_uint num_devices, const char *aocx_name);

// Utility function for loading file into Binary String//unsigned char* load_file(const char* filename, size_t *size_ret){



FILE *fp = fopen(aocx_name,"rb"); fseek(fp,0,SEEK_END); size_t len = ftell(fp); char *result = (unsigned char*)malloc(sizeof(unsigned char)*len); rewind(fp); fread(result,len,1,fp); fclose(fp); *size_ret = len; return result;}

//Create a Program that is compiled for the devices in the "device_list"//cl_program createMultiDeviceProgram(cl_context context, const cl_device_id *device_list, cl_uint num_devices, const char *aocx_name){ printf("creating multi device program %s for %d devices\n", aocx_name, num_devices); const unsigned char **binaries = (const unsigned char**)malloc(num_devices*sizeof(unsigned char*)); size_t *lengths=(size_t*)malloc(num_devices*sizeof(size_t)); cl_int err; for(cl_uint i=0; i<num_devices; i++) { binaries[i] = load_file(aocx_name,&lengths[i]); if (!binaries[i]) { printf("couldn't load %s\n", aocx_name); exit(-1); } }

cl_program p = clCreateProgramWithBinary(context, num_devices, device_list, lengths, binaries, NULL, &err); free(lengths); free(binaries); if (err != CL_SUCCESS) { printf("Program Create Error\n"); } return p;}

// main program

main () { // Normal OpenCL setup }program = createMultiDeviceProgram(context, device_list, num_devices, "program.aocx");clBuildProgram(program,num_devices,device_list,options,NULL,NULL);

1.7.6.5 Termination of the Runtime Environment and Error Recovery

In the event that the host application terminates unexpectedly, you must restart theruntime environment and reprogram the FPGA.



The runtime environment is a library that is compiled as part of the host application.When the host application terminates, the runtime environment will also terminatealong with any tracking activity that it performs. If you restart the host application, anew runtime environment and its associated tracking activities will reinitialize. Theinitialization functions reset the kernel's hardware state.

In same cases, unexpected termination of the host application causes theconfiguration of certain hardware (for example, PCIe hard IP) to be incomplete. Torestore the configuration of these hardware, the host needs to reprogram the FPGA.

If you use a Custom Platform that implements customized hardware blocks, be awarethat restarting the host application and resetting these blocks might have designimplications:

• When the host application calls the clGetPlatformIDs function, all kernels andchannels will be reset for all available devices.

• When the host application calls the clGetPlatformIDs function, it resets FIFObuffers and channels as it resets the device.

• The host application initializes memory buffers via the clCreateBuffer andclEnqueueWriteBuffer function calls. You cannot access the contents ofbuffers from a previous host execution within a new host execution.

1.7.7 Allocating Shared Memory for OpenCL Kernels Targeting SoCs

Intel recommends that OpenCL kernels that run on Intel SoCs access shared memoryinstead of the FPGA DDR memory. FPGA DDR memory is accessible to kernels withvery high bandwidths. However, read and write operations from the ARM CPU to FPGADDR memory are very slow because they do not use direct memory access (DMA).Reserve FPGA DDR memory only for passing temporary data between kernels orwithin a single kernel for testing purposes.

Notes: 1. Mark the shared buffers between kernels as volatile to ensure that buffermodification by one kernel is visible to the other kernel.

2. To access shared memory, you only need to modify the host code. Modifications tothe kernel code are unnecessary.

3. You cannot use the library function malloc or the operator new to allocatephysically shared memory. Also, the CL_MEM_USE_HOST_PTR flag does not workwith shared memory.

In DDR memory, shared memory must be physically contiguous. The FPGA cannotconsume virtually contiguous memory without a scatter-gather direct memoryaccess (SG-DMA) controller core. The malloc function and the new operator arefor accessing memory that is virtually contiguous.

4. CPU caching is disabled for the shared memory.

The ARM CPU and the FPGA can access the shared memory simultaneously. You do notneed to include the clEnqueueReadBuffer and clEnqueueWriteBuffer calls inyour host code to make data visible to either the FPGA or the CPU.



• To allocate and access shared memory, structure your host code in a similarmanner as the following example:

cl_mem src = clCreateBuffer(…, CL_MEM_ALLOC_HOST_PTR, size, …);int *src_ptr = (int*)clEnqueueMapBuffer (…, src, size, …);*src_ptr = input_value; //host writes to ptr directlyclSetKernelArg (…, src);clEnqueueNDRangeKernel(…);clFinish();printf (“Result = %d\n”, *dst_ptr); //result is available immediatelyclEnqueueUnmapMemObject(…, src, src_ptr, …);clReleaseMemObject(src); // actually frees physical memory

You can include the CONFIG_CMA_SIZE_MBYTES kernel configuration option tocontrol the maximum total amount of shared memory available for allocation. Inpractice, the total amount of allocated shared memory is smaller than the value ofCONFIG_CMA_SIZE_MBYTES.

Important: 1. If your target board has multiple DDR memory banks, theclCreateBuffer(..., CL_MEM_READ_WRITE, ...) functionallocates memory to the nonshared DDR memory banks. However,if the FPGA has access to a single DDR bank that is sharedmemory, then clCreateBuffer(...,CL_MEM_READ_WRITE, ...) allocates to shared memory, similarto using the CL_MEM_ALLOC_HOST_PTR flag.

2. The shared memory that you request with theclCreateBuffer(..., CL_MEM_ALLOC_HOST_PTR,size, ...) function is allocated in the Linux OpenCL kerneldriver, and it relies on the contiguous memory allocator (CMA)feature of the Linux kernel. For detailed information on enablingand configuring the CMA, refer to the Recompiling the Linux Kerneland the OpenCL Linux Kernel Driver section of the Intel FPGA SDKfor OpenCL Cyclone V SoC Development Kit Reference PlatformPorting Guide.

• To transfer data from shared hard processor system (HPS) DDR to FPGA DDRefficiently, include a kernel that performs the memcpy function, as shown below.

__attribute__((num_simd_work_items(8)))mem_stream(__global uint * src, __global uint * dst){ size_t gid = get_global_id(0); dst[gid] = src[gid];}

Attention: Allocate the src pointer in the HPS DDR as shared memory using theCL_MEM_ALLOC_HOST_PTR flag.

• If the host allocates constant memory to shared HPS DDR system and thenmodifies it after kernel execution, the modifications might not take effect. As aresult, subsequent kernel executions might use outdated data. To prevent kernelexecution from using outdated constant memory, perform one of the followingtasks:

a. Do not modify constant memory after its initialization.

b. Create multiple constant memory buffers if you require multiple __constantdata sets.

c. If available, allocate constant memory to the FPGA DDR on your acceleratorboard.



Related Links

Recompiling the Linux Kernel and the OpenCL Linux Kernel Driver

1.8 Compiling Your OpenCL Kernel

The Intel FPGA SDK for OpenCL offers a list of compiler options that allows you tocustomize the kernel compilation process. An Intel FPGA SDK for OpenCL OfflineCompiler command consists of the aoc command, compiler option(s) and settings,and kernel filenames. You can invoke an aoc command to direct the compiler to targeta specific FPGA board, generate reports, or implement optimization techniques.

Before you compile an OpenCL kernel, ensure that the environment variableAOCL_BOARD_PACKAGE_ROOT points to the location of the appropriate CustomPlatform. Also, verify that the QUARTUS_ROOTDIR_OVERRIDE environment variablepoints to the correct edition of the Quartus Prime software.

If these environment variables do not have the correct settings, follow the instructionsin the Setting the Intel FPGA SDK for OpenCL User Environment Variables section ofthe Intel FPGA SDK for OpenCL Getting Started Guide to modify the settings.

Attention: If you use the Stratix V Network Reference Platform, you must acquire and install thePLDA QuickUDP intellectual property (IP) core license. Refer to the PLDA website formore information. If you use a Custom Platform that includes the QuickUDP IP core,refer to your board vendor's documentation for more information on the acquisitionand installation of the QuickUDP IP license.

Caution: Improper installation of the QuickUDP IP license causes kernel compilation to fail withthe following error message:

Error (292014): Can't find valid feature line for core PLDAQUICKTCP (73E1_AE12) in current license.

Note that the error has no actual dependency on the TCP Hardware Stack QuickTCP IPfrom PLDA.

Related Links



1.8.1 Compiling Your Kernel to Create Hardware Configuration File

You can compile an OpenCL kernel and create the hardware configuration file (that is,the .aocx file) in a single step.

Intel recommends that you use this one-step compilation strategy under the followingcircumstances:

• After you optimize your kernel via the Intel FPGA SDK for OpenCL design flow, andyou are now ready to create the .aocx file for deployment onto the FPGA.

• You have one or more simple kernels that do not require any optimization.



https://documentation.altera.com/#/link/ewa1403875738903/mwh1391806417857/en-us



• To compile the kernel and generate the .aocx file in one step, invoke the aoc<your_kernel_filename1>.cl [<your_kernel_filename2>.cl ...]command.

Where [<your_kernel_filename2>.cl ...] are the optional space-delimited filenames of kernels that you can compile in addition to<your_kernel_filename1>.cl.

The Intel FPGA SDK for OpenCL Offline Compiler groups the .cl files into a temporaryfile. It then compiles this file to generate the .aocx file. You must specify the order ofthe kernels in this temporary file on the command line.

1.8.2 Compiling Your Kernel without Building Hardware (-c)

To direct the Intel FPGA SDK for OpenCL Offline Compiler to compile your OpenCLkernel and generate a Quartus Prime hardware design project without creating ahardware configuration file, include the -c option in your aoc command.

• At a command prompt, invoke the aoc -c <your_kernel_filename1>.cl[<your_kernel_filename2>.cl ...] command.

Where [<your_kernel_filename2>.cl ...] are the optional space-delimited filenames of kernels that you can compile in addition to<your_kernel_filename1>.cl.

When you invoke the aoc command with the -c flag, the offline compiler compilesthe kernel and creates the following files and directories:

— The .aoco file. The offline compiler creates the .aoco file in a matter ofseconds to minutes. If you compile multiple kernels, their information inthe .aoco file appears in the order in which you list them on the commandline.

— A <your_kernel_filename> folder or subdirectory. It contains intermediatefiles that the SDK uses to build the hardware configuration file necessary forFPGA programming.

1.8.3 Specifying the Location of Header Files (-I <directory>)

To add a directory to the list of directories that the Intel FPGA SDK for OpenCL OfflineCompiler searches for header files during kernel compilation, include the -I<directory> option in your aoc command.

If the header files are in the same directory as your kernel, you do not need to includethe -I <directory> option in your aoc command. The offline compilerautomatically searches the current folder or directory for header files.



• At a command prompt, invoke the aoc -I <directory><your_kernel_filename>.cl command.

Caution: For Windows systems, ensure that your include path does not containany trailing slashes. The offline compiler considers a trailing forwardslash (/) or backward slash (\) as illegal.

The offline compiler generates an error message if you invoke the aoccommand in the following manner:

aoc -I <drive>\<folder>\ ... \<subfolder>\<your_kernel_filename>.cl

or

aoc -I <drive>/<folder>/ ... /<subfolder>/<your_kernel_filename>.cl

The correct way to specify the include path is as follows:

aoc -I <drive>\<folder>\ ... \<subfolder><your_kernel_filename>.cl

or

aoc -I <drive>/<folder>/ ... /<subfolder><your_kernel_filename>.cl

1.8.4 Specifying the Name of an Intel FPGA SDK for OpenCL OfflineCompiler Output File (-o <filename>)

To specify the name of a .aoco file or a .aocx file, include the -o <filename>option in your aoc command.

• If you implement the multistep compilation flow, specify the names of the outputfiles in the following manner:

a. To specify the name of the .aoco file that the offline compiler creates duringan intermediate compilation step, invoke the aoc -c -o<your_object_filename>.aoco <your kernel_filename>.clcommand.

b. To specify the name of the .aocx file that the offline compiler creates duringthe final compilation step, invoke the aoc -o<your_executable_filename>.aocx <your_object_filename>.aococommand.

• If you implement the one-step compilation flow, specify the name of the .aocxfile by invoking the aoc -o <your_executable_filename>.aocx<your_kernel_filename>.cl command.

1.8.5 Compiling a Kernel for a Specific FPGA Board (--board<board_name>)

To compile your OpenCL kernel for a specific FPGA board, include the --board<board_name> option in the aoc command.



To compile a kernel for a specific board in your Custom Platform, you must first set theenvironment variable AOCL_BOARD_PACKAGE_ROOT to point to the location of yourCustom Platform.

Attention: If you want to program multiple FPGA devices, you may select board types that areavailable in the same Custom Platform because AOCL_BOARD_PACKAGE_ROOT onlypoints to the location of one Custom Platform.

When you compile your kernel by including the --board <board_name> option inthe aoc command, the Intel FPGA SDK for OpenCL Offline Compiler defines thepreprocessor macro AOCL_BOARD_<board_name> to be 1, which allows you tocompile device-optimized code in your kernel.

1. To obtain the names of the available FPGA boards in your Custom Platform, invokethe aoc --list-boards command.

For example, the offline compiler generates the following output:

Board List:FPGA_board_1

where FPGA_board_1 is the <board_name>.

2. To compile your OpenCL kernel for FPGA_board_1, invoke the aoc --boardFPGA_board_1 <your_kernel_filename>.cl command.The offline compiler defines the preprocessor macro AOCL_BOARD_FPGA_board_1to be 1 and compiles kernel code that targets FPGA_board_1.

Tips: To readily identify compiled kernel files that target a specific FPGA board, Intelrecommends that you rename the kernel binaries by including the -o option in theaoc command.

To target your kernel to FPGA_board_1 in the one-step compilation flow, invoke thefollowing command:

aoc --board FPGA_board_1 <your_kernel_filename>.cl -o<your_executable_filename>_FPGA_board_1.aocx

To target your kernel to FPGA_board_1 in the multistep compilation flow, perform thefollowing tasks:

1. Invoke the following command to generate the .aoco file:

aoc -c --board FPGA_board_1 <your_kernel_filename>.cl -o<my_object_filename>_FPGA_board_1.aoco

2. Invoke the following command to generate the .aocx file:

aoc --board FPGA_board_1<your_object_filename>_FPGA_board_1.aoco -o<your_executable_filename>_FPGA_board_1.aocx

If you have an accelerator board consisting of two FPGAs, each FPGA device has anequivalent "board" name (for example, board_fpga_1 and board_fpga_2). To target akernel_1.cl to board_fpga_1 and a kernel_2.cl to board_fpga_2, invoke thefollowing commands:



aoc --board board_fpga1 kernel_1.cl

aoc --board board_fpga2 kernel_2.cl

Related Links

Specifying the Name of an Intel FPGA SDK for OpenCL Offline Compiler Output File (-o<filename>) on page 91

To specify the name of a .aoco file or a .aocx file, include the -o <filename>option in your aoc command.

1.8.6 Resolving Hardware Generation Fitting Errors during KernelCompilation (--high-effort)

Sometimes, OpenCL kernel compilation fails during the hardware generation stagebecause the design fails to meet fitting constraints. In this case, recompile the kernelusing the --high-effort option of the aoc command.

When kernel compilation fails because of a fitting constraint problem, the Intel FPGASDK for OpenCL Offline Compiler displays the following error message:

Error: Kernel fit error, recommend using --high-effort.Error: Cannot fit kernel(s) on device

• To overcome this problem, recompile your kernel by invoking the followingcommand:

aoc --high-effort <your_kernel_filename>.cl

After you invoke the command, the offline compiler displays the followingmessage:

High-effort hardware generation selected, compile time may increase significantly.

The offline compiler will make three attempts to recompile your kernel and generatehardware. Modify your kernel if compilation still fails after the --high-effortattempt.

1.8.7 Defining Preprocessor Macros to Specify Kernel Parameters (-D<macro_name>)

The Intel FPGA SDK for OpenCL Offline Compiler supports preprocessor macros thatallow you to pass macro definitions and compile code on a conditional basis.



• To pass a preprocessor macro definition to the offline compiler, invoke the aoc -D <macro_name> <kernel_filename>.cl command.

• To override the existing value of a defined preprocessor macro, invoke the aoc -D <marco_name>=<value> <kernel_filename>.cl command.

Consider the following code snippet for the kernel sum:

#ifndef UNROLL_FACTOR #define UNROLL_FACTOR 1#endif

__kernel void sum (__global const int * restrict x, __global int * restrict sum){ int accum = 0;

#pragma unroll UNROLL_FACTOR for(size_t i = 0; i < 4; i++) { accum += x[i + get_global_id(0) * 4]; } sum[get_global_id(0)] = accum;}

To override the UNROLL_FACTOR of 1 and set it to 4, invoke the aoc -DUNROLL_FACTOR=4 sum.cl command. Invoking this command is equivalent toreplacing the line #define UNROLL_FACTOR 1 with #define UNROLL_FACTOR4 in the sum kernel source code.

• To use preprocessor macros to control how the offline compiler optimizes yourkernel without modifying your kernel source code, invoke the aoc -o<hardware_filename>.aocx -D <macro_name>=<value><kernel_filename>.cl

Where:

-o is the offline compiler option you use to specify the name of the .aocx file thatthe offline compiler generates.

<hardware_filename> is the name of the .aocx file that the offline compilergenerates using the preprocessor macro value you specify.

Tip: To preserve the results from both compilations on your file system, compileyour kernels as separate binaries by using the -o flag of the aoc command.

For example, if you want to compile the same kernel multiple times with requiredwork-group sizes of 64 and 128, you can define a WORK_GROUP_SIZEpreprocessor macro for the kernel attribute reqd_work_group_size, as shownbelow:

__attribute__((reqd_work_group_size(WORK_GROUP_SIZE,1,1)))__kernel void myKernel(...)for (size_t i = 0; i < 1024; i++){ // statements}

Compile the kernel multiple times by typing the following commands:

aoc –o myKernel_64.aocx –D WORK_GROUP_SIZE=64 myKernel.cl

aoc –o myKernel_128.aocx –D WORK_GROUP_SIZE=128 myKernel.cl



1.8.8 Generating Compilation Progress Report (-v)

To direct the Intel FPGA SDK for OpenCL Offline Compiler to report on the progress ofa compilation, include the -v option in your aoc command.

• To direct the offline compiler to report on the progress of a full compilation, invokethe aoc -v <your_kernel_filename>.cl command.

The offline compiler generates a compilation progress report similar to thefollowing example:

aoc: Environment checks are completed successfully.You are now compiling the full flow!!aoc: Selected target board s5_netaoc: Running OpenCL parser....aoc: OpenCL parser completed successfully.aoc: Compiling....aoc: Linking with IP library ...aoc: First stage compilation completed successfully.aoc: Setting up project for CvP revision flow....aoc: Hardware generation completed successfully.

• To direct the offline compiler to report on the progress of an intermediatecompilation step that does not build hardware, invoke the aoc -c -v<your_kernel_filename>.cl command.


aoc: Environment checks are completed successfully.aoc: Selected target board s5_netaoc: Running OpenCL parser....aoc: OpenCL parser completed successfully.aoc: Compiling....aoc: Linking with IP library ...aoc: First stage compilation completed successfully.aoc: To compile this project, run "aoc <your_kernel_filename>.aoco"

• To direct the offline compiler to report on the progress of a compilation foremulation, invoke the aoc -march=emulator -v<your_kernel_filename>.cl command.


aoc: Environment checks are completed successfully.You are now compiling the full flow!!aoc: Selected target board s5_netaoc: Running OpenCL parser....exaoc: OpenCL parser completed successfully.aoc: Compiling for Emulation ....aoc: Emulator Compilation completed successfully.Emulator flow is successful.

Related Links

• Compiling Your Kernel without Building Hardware (-c) on page 90To direct the Intel FPGA SDK for OpenCL Offline Compiler to compile yourOpenCL kernel and generate a Quartus Prime hardware design project withoutcreating a hardware configuration file, include the -c option in your aoccommand.



• Emulating and Debugging Your OpenCL Kernel on page 99The Intel FPGA SDK for OpenCL Emulator assesses the functionality of yourkernel.

1.8.9 Displaying the Estimated Resource Usage Summary On-Screen (--report)

By default, the Intel FPGA SDK for OpenCL Offline Compiler estimates hardwareresource usage during compilation . The offline compiler factors in the usage ofexternal interfaces such as PCIe, memory controller, and DMA engine in itscalculations. During kernel compilation, the offline compiler generates an estimatedresource usage summary in the <your_kernel_filename>.log file within the<your_kernel_filename> directory. To review the estimated resource usagesummary on-screen, include the --report option in the aoc command.

You can review the estimated resource usage summary without performing a fullcompilation. To review the summary on-screen prior to generating the hardwareconfiguration file, include the -c option in your aoc command.

• At a command prompt, invoke the aoc -c <your_kernel_filename>.cl --report command.The offline compiler generates an output similar to the following example:

+--------------------------------------------------------------------+; Estimated Resource Usage Summary ;+----------------------------------------+---------------------------+; Resource + Usage ;+----------------------------------------+---------------------------+; Logic utilization ; 35% ;; ALUTs ; 22% ;; Dedicated logic registers ; 15% ;; Memory blocks ; 29% ;; DSP blocks ; 0% ;+----------------------------------------+---------------------------;

Related Links

Compiling Your Kernel without Building Hardware (-c) on page 90To direct the Intel FPGA SDK for OpenCL Offline Compiler to compile your OpenCLkernel and generate a Quartus Prime hardware design project without creating ahardware configuration file, include the -c option in your aoc command.

1.8.10 Suppressing Warning Messages from the Intel FPGA SDK forOpenCL Offline Compiler (-W)

To suppress all warning messages, include the -W option in your aoc command.

• At a command prompt, invoke the aoc -W <your_kernel_filename>.clcommand.

1.8.11 Converting Warning Messages from the Intel FPGA SDK for OpenCLOffline Compiler into Error Messages (-Werror)

To convert all warning messages into error messages, include the -Werror option inyour aoc command.



• At a command prompt, invoke the aoc -Werror<your_kernel_filename>.cl command.

1.8.12 Removing Debug Data from Compiler Reports and Source Codefrom the .aocx File (-g0)

By default, the Intel FPGA SDK for OpenCL Offline Compiler includes sourceinformation in compiler reports and embeds the source code into the .aocx binarywhen it compiles the .cl or .aoco file. Include the -g0 option in the aoc commandto remove source information from the compiler reports and to remove source codeand customer IP information from the .aocx file.

• To remove source information in reports and remove source code and customer IPinformation from the .aocx file, invoke the aoc -g0<your_kernel_filename>.cl command.

1.8.13 Disabling Burst-Interleaving of Global Memory (--no-interleaving<global_memory_type>)

The Intel FPGA SDK for OpenCL Offline Compiler cannot burst-interleave globalmemory across different memory types. You can disable burst-interleaving for allglobal memory banks of the same type and manage them manually by including the--no-interleaving <global_memory_type> option in your aoc command.Manual partitioning of memory buffers overrides the default burst-interleavedconfiguration of global memory.

Caution: The --no-interleaving option requires a global memory type parameter. If you donot specify a memory type, the offline compiler issues an error message.



• To direct the offline compiler to disable burst-interleaving for the default globalmemory, invoke the aoc <your_kernel_filename>.cl --no-interleaving default command.

Your accelerator board might include multiple global memory types. To identify thedefault global memory type, refer to board vendor's documentation for yourCustom Platform.

• For a heterogeneous memory system, to direct the offline compiler to disableburst-interleaving of a specific global memory type, perform the following tasks:

a. Consult the board_spec.xml file of your Custom Platform for the names ofthe available global memory types (for example, DDR and quad data rate(QDR)).

b. To disable burst-interleaving for one of the memory types (for example, DDR),invoke the aoc <your_kernel_filename>.cl --no-interleaving DDR command.The offline compiler enables manual partitioning for the DDR memory bank,and configures the other memory bank in a burst-interleaved fashion.

c. To disable burst-interleaving for more than one type of global memory buffers,include a --no-interleaving <global_memory_type> option for eachglobal memory type.

For example, to disable burst-interleaving for both DDR and QDR, invoke theaoc <your_kernel_filename>.cl --no-interleaving DDR --no-interleaving QDR command.

Caution: Do not pass a buffer as kernel arguments that associate it with multiple memorytechnologies.

1.8.14 Configuring Constant Memory Cache Size (--const-cache-bytes<N>)

Include the --const-cache-bytes <N> flag in your aoc command to direct theIntel FPGA SDK for OpenCL Offline Compiler to configure the constant memory cachesize (rounded up to the closest power of 2).

The default constant cache size is 16 kB.

• To configure the constant memory cache size, invoke the aoc --const-cache-bytes <N> <your_kernel_filename>.cl command, where <N> isthe cache size in bytes.

For example, to configure a 32 kB cache during compilation of the OpenCL kernelmyKernel.cl, invoke the aoc --const-cache-bytes 32768myKernel.cl command.

Note: This argument has no effect if none of the kernels uses the __constantaddress space.

1.8.15 Relaxing the Order of Floating-Point Operations (--fp-relaxed)

Include the --fp-relaxed option in your aoc command to direct the Intel FPGA SDKfor OpenCL Offline Compiler to relax the order of arithmetic floating-point operationsusing a balanced tree hardware implementation.



Implementing a balanced tree structure leads to more efficient hardware at theexpense of numerical variation in results.

Caution: To implement this optimization control, your program must be able to tolerate smallvariations in the floating-point results.

• To direct the offline compiler to execute a balanced tree hardware implementation,invoke the aoc --fp-relaxed <your_kernel_filename>.cl command.

1.8.16 Reducing Floating-Point Rounding Operations (--fpc)

Include the --fpc option in your aoc command to direct the Intel FPGA SDK forOpenCL Offline Compiler to remove intermediary floating-point rounding operationsand conversions whenever possible, and to carry additional bits to maintain precision.

Implementing this optimization control also changes the rounding mode. It roundstowards zero only at the end of a chain of floating-point arithmetic operations (that is,multiplications, additions, and subtractions).

• To direct the offline compiler to reduce the number of rounding operations, invokethe aoc --fpc <your_kernel_filename>.cl command.

1.9 Emulating and Debugging Your OpenCL Kernel

The Intel FPGA SDK for OpenCL Emulator assesses the functionality of your kernel.

The Intel FPGA SDK for OpenCL Emulator generates a .aocx file that executes onx86-64 Windows or Linux host. This feature allows you to emulate the functionality ofyour kernel and iterate on your design without executing it on the actual FPGA eachtime. For Linux platform, you can also use the Emulator to perform functional debug.

Caution: Emulation does not support cross-compilation to ARM processor. To run emulation on adesign that targets an SoC, emulate on a non-SoC board (for example,ALTERAOCLSDKROOT/board/s5_ref). When you are satisfied with the emulationresults, you may target your design on an SoC board for subsequent optimizationsteps.

1. Modifying Channels Kernel Code for Emulation on page 100To emulate applications with a channel that reads or writes to an I/O channel,modify your kernel to add a read or write channel that replaces the I/O channel,and make the source code that uses it is conditional.

2. Compiling a Kernel for Emulation (-march=emulator) on page 101To compile an OpenCL kernel for emulation, include the -march=emulatoroption in your aoc command.

3. Emulating Your OpenCL Kernel on page 103To emulate your OpenCL kernel, run the emulation .aocx file on the platformon which you build your kernel.

4. Debugging Your OpenCL Kernel on Linux on page 104For Linux systems, you can direct the Intel FPGA SDK for OpenCL Emulator torun your OpenCL kernel in the debugger and debug it functionally as part of thehost application.

5. Limitations of the Intel FPGA SDK for OpenCL Emulator on page 105The Intel FPGA SDK for OpenCL Emulator feature has some limitations.



1.9.1 Modifying Channels Kernel Code for Emulation

The Emulator emulates kernel-to-kernel channels. It does not support the emulationof I/O channels that interface with input or output features of your FPGA board. Toemulate applications with a channel that reads or writes to an I/O channel, modifyyour kernel to add a read or write channel that replaces the I/O channel, and makethe source code that uses it is conditional.

The Intel FPGA SDK for OpenCL does not set the EMULATOR macro definition. Youmust set it manually either from the command line or in the source code.

Consider the following kernel example:

channel unlong4 inchannel __attribute__((io("eth0_in")));

__kernel void send (int size){ for (unsigned i=0; i < size; i++) { ulong4 data = read_channel_altera(inchannel); //statements }}

To enable the Emulator to emulate a kernel with a channel that interfaces with an I/Ochannel, perform the following tasks:

1. Modify the kernel code in one of the following manner:

— Add a matching write_channel_altera call such as the one shown below.

#ifdef EMULATOR

__kernel void io_in (__global char * restrict arr, int size){ for (unsigned i=0; i<size; i++) { ulong4 data = arr[i]; //arr[i] being an alternate data source write_channel_altera(inchannel, data); }}#endif

— Replace the I/O channel access with a memory access, as shown below:

__kernel void send (int size){ for (unsigned i=0; i < size; i++) { #ifndef EMULATOR

ulong4 data = read_channel_altera(inchannel);

#else ulong4 data = arr[i]; //arr[i] being an alternate data source

#endif //statements }}

2. Modify the host application to create and start this conditional kernel duringemulation.



Related Links

Implementing I/O Channels Using the io Channels Attribute on page 33Include an io attribute in your channel declaration to declare a special I/O channelto interface with input or output features of an FPGA board.

1.9.1.1 Emulating a Kernel that Passes Pipes or Channels by Reference

The Intel FPGA SDK for OpenCL Emulator supports a kernel that passes pipes orchannels by reference.

For example, you may emulate a kernel that has the following structure:

void my_function (pipe uint * pipe_ref, __global uint * dst, int i){ read_pipe (*pipe_ref, &dst[i]);}

__kernel voidconsumer (__global uint * restrict dst, read_only pipe uint __attribute__((blocking)) c0){ for (int i=0;i<5;i++) { my_function( &c0, dst, i ); }}

1.9.2 Compiling a Kernel for Emulation (-march=emulator)

To compile an OpenCL kernel for emulation, include the -march=emulator option inyour aoc command.



• Before you perform kernel emulation, perform the following tasks:

— Install a Custom Platform from your board vendor for your FPGA acceleratorboards.

— Verify that the environment variable AOCL_BOARD_PACKAGE_ROOT points tothe location of the Custom Platform. Alternatively, if your kernel targets aboard from an Intel FPGA SDK for OpenCL Reference Platform, setAOCL_BOARD_PACKAGE_ROOT to the path of the Reference Platform (forexample, ALTERAOCLSDKROOT/board/<Reference_Platform_name>).

— Verify that the environment variable QUARTUS_ROOTDIR_OVERRIDE points tothe correct edition of the Quartus Prime software.

• For non-Arria 10 devices, QUARTUS_ROOTDIR_OVERRIDE points to theinstallation directory of the Quartus Prime Standard Edition software.

• For Arria 10 devices, QUARTUS_ROOTDIR_OVERRIDE points to theinstallation directory of the Quartus Prime Pro Edition software.

• To emulate your kernels on Windows systems, you need the Microsoft linker andadditional compilation time libraries. Verify that the PATH environment variablesetting includes all the paths described in the Setting the Intel FPGA SDK forOpenCL User Environment Variables section of the Intel FPGA SDK for OpenCLGetting Started Guide.

The PATH environment variable setting must include the path to the LINK.EXE filein Microsoft Visual Studio.

• Ensure that your LIB environment variable setting includes the path to theMicrosoft compilation time libraries.

The compilation time libraries are available with Microsoft Visual Studio.

• Verify that the LD_LIBRARY_PATH environment variable setting includes all thepaths described in the Setting the Intel FPGA SDK for OpenCL User EnvironmentVariables section in the Intel FPGA SDK for OpenCL Getting Started Guide.

• To create kernel programs that are executable on x86-64 host systems, invoke theaoc -march=emulator <your_kernel_filename>.cl command.

• To compile a kernel for emulation that targets a specific board, invoke the aoc -march=emulator --board <board_name><your_kernel_filename>.cl command.

• For Linux systems, the Intel FPGA SDK for OpenCL Offline Compiler offerssymbolic debug support for the debugger.

The offline compiler's debug support allows you to pinpoint the origins offunctional errors in your kernel source code.

Related Links

• Compiling a Kernel for a Specific FPGA Board (--board <board_name>) on page91

To compile your OpenCL kernel for a specific FPGA board, include the --board <board_name> option in the aoc command.







1.9.3 Emulating Your OpenCL Kernel

To emulate your OpenCL kernel, run the emulation .aocx file on the platform onwhich you build your kernel.

To emulate your kernel, perform the following steps:

1. Run the utility command aocl linkflags to find out which libraries arenecessary for building a host application. The software lists the libraries for bothemulation and regular kernel compilation flows.

2. Build a host application and link it to the libraries from Step 1.

Attention: To emulate multiple devices alongside other OpenCL SDKs, link yourhost application to the Khronos ICD Loader Library before linking it tothe host runtime libraries. Link the host application to the ICD LoaderLibrary by modifiying the Makefile for the host application. Refer toLinking Your Host Application to the Khronos ICD Loader Library formore information.

3. If necessary, move the <your_kernel_filename>.aocx file to a location wherethe host can find easily, preferably the current working directory.

4. To run the host application for emulation:

— For Windows, first define the number of emulated devices by invoking the setCL_CONTEXT_EMULATOR_DEVICE_ALTERA=<number_of_devices>command and then run the host application.

After you run the host application, invoke setCL_CONTEXT_EMULATOR_DEVICE_ALTERA= to unset the variable.

— For Linux, invoke the envCL_CONTEXT_EMULATOR_DEVICE_ALTERA=<number_of_devices><host_application_filename> command.

This command specifies the number of identical emulation devices that theEmulator needs to provide.

5. If you change your host or kernel program and you want to test it, only recompilethe modified host or kernel program and then rerun emulation.

Each invocation of the emulated kernel creates a shared library copy called<process_ID>-libkernel.so in a default temporary directory, where<process_ID> is a unique numerical value assigned to each emulation run. You mayoverride the default directory by setting the TMP or TEMP environment variable onWindows, or setting TMPDIR on Linux.

Related Links

• Displaying Information on OpenCL Host Runtime and MMD Libraries (link-config orlinkflags) on page 79

To display a list of flags necessary for linking a host application with OpenCLhost runtime and MMD libraries, invoke the link-config or linkflagsutility command.

• Linking Your Host Application to the Khronos ICD Loader Library on page 80The Intel FPGA SDK for OpenCL supports the OpenCL ICD extension from theKhronos Group.



1.9.4 Debugging Your OpenCL Kernel on Linux

For Linux systems, you can direct the Intel FPGA SDK for OpenCL Emulator to runyour OpenCL kernel in the debugger and debug it functionally as part of the hostapplication. The debugging feature allows you to debug the host and the kernelseamlessly. You can step through your code, set breakpoints, and examine and setvariables.

Prior to debugging your kernel, you must perform the following tasks:

1. During program execution, the debugger cannot step from the host code to thekernel code. You must set a breakpoint before the actual kernel invocation byadding these lines:

a. break <your_kernel>

This line sets a breakpoint before the kernel.

b. continue

If you have not begun debugging your host, then type start instead.

2. The kernel is loaded as a shared library immediately before the host loads thekernels. The debugger does not recognize the kernel names until the host actuallyloads the kernel functions. As a result, the debugger will generate the followingwarning for the breakpoint you set before the execution of the first kernel:

Function "<your_kernel>" not defined.

Make breakpoint pending on future shared library load? (y or[n])

Answer y. After initial program execution, the debugger will recognize the functionand variable names, and line number references for the duration of the session.

Caution: The Emulator uses the OpenCL runtime to report some error details. For emulation,the runtime uses a default print out callback when you initialize a context via theclCreateContext function.

Note: Kernel debugging is independent of host debugging. Debug your host code in existingtools such as Microsoft Visual Studio Debugger for Windows and GDB for Linux.

To compile your OpenCL kernel for debugging, perform the following steps:

1. To generate a .aocx file for debugging that targets a specific accelerator board,invoke the aoc -march=emulator <your_kernel_filename>.cl --board <board_name> command.



Attention: Specify the name of your FPGA board when you run your hostapplication. To verify the name of the target board for which youcompile your kernel, invoke the aoc -march=emulator -v<your_kernel_filename>.cl command. The Intel FPGA SDK forOpenCL Offline Compiler will display the name of the target FPGAboard.

2. Run the utility command aocl linkflags to find out the additional librariesnecessary to build a host application that supports kernel debugging.

3. Build a host application and link it to the libraries from Step 2.

4. Ensure that the <your_kernel_filename>.aocx file is in a location where thehost can find it, preferably the current working directory.

5. To run the application, invoke the command envCL_CONTEXT_EMULATOR_DEVICE_ALTERA=<number_of_devices> gdb --args <your_host_program_name>, where <number_of_devices> is thenumber of identical emulation devices that the Emulator needs to provide.

6. If you change your host or kernel program and you want to test it, only recompilethe modified host or kernel program and then rerun the debugger.

Related Links



• Generating Compilation Progress Report (-v) on page 95To direct the Intel FPGA SDK for OpenCL Offline Compiler to report on theprogress of a compilation, include the -v option in your aoc command.

• Displaying Information on OpenCL Host Runtime and MMD Libraries (link-config orlinkflags) on page 79

To display a list of flags necessary for linking a host application with OpenCLhost runtime and MMD libraries, invoke the link-config or linkflagsutility command.

1.9.5 Limitations of the Intel FPGA SDK for OpenCL Emulator

The Intel FPGA SDK for OpenCL Emulator feature has some limitations.

1. Execution model

The Emulator supports the same compilation modes as the FPGA variant. As aresult, you must call the clCreateProgramBinary function to createcl_program objects for emulation.

2. Concurrent execution

Modeling of concurrent kernel executions has limitations. During execution, theEmulator does not actually run interacting work-items in parallel. Therefore, someconcurrent execution behaviors, such as different kernels accessing globalmemory without a barrier for synchronization, might generate inconsistentemulation results between executions.

3. Kernel performance



The .aocx file that you generate for emulation does not include anyoptimizations. Therefore, it might execute at a significantly slower speed thanwhat an optimized kernel might achieve. In addition, because the Emulator doesnot implement actual parallel execution, the execution time multiplies with thenumber of work-items that the kernel executes.

4. The Emulator executes the host runtime and the kernels in the same addressspace. Certain pointer or array usages in your host application might cause thekernel program to fail, and vice versa. Example usages include indexing externalallocated memory and writing to random pointers. You may use memory leakdetection tools such as Valgrind to analyze your program. However, the host mightencounter a fatal error caused by out-of-bounds write operations in your kernel,and vice versa.

5. Emulation of channel behavior has limitations, especially for conditional channeloperations where the kernel does not call the channel operation in every loopiteration. In these cases, the Emulator might execute channel operations in adifferent order than on the hardware.

1.10 Reviewing Your Kernel's report.html File

Attention: The analyze-area Intel FPGA SDK for OpenCL utility option has been deprecated. Toview your kernel's estimated area usage, refer to the report.html file.

For reference information on the deprecated area report, refer to the Review YourKernel's Area Report to Identify Inefficiencies in Resource Usage section in version16.0 of the Altera SDK for OpenCL Best Practices Guide.

After compiling your OpenCL kernel, the Intel FPGA SDK for OpenCL Offline Compilerautomatically generates an HTML report that analyzes various aspects of your kernel,such as area, loop structure, memory usage, and kernel pipeline.To launch the HTML report, open the report.html file in the<your_kernel_filename>/reports directory.

For more information on the HTML report, refer to the Review Your Kernel'sreport.html File section in the Intel FPGA SDK for OpenCL Best Practices Guide.

Related Links

• Review Your Kernel's report.html File

• Altera SDK for OpenCL Best Practices Guide version 16.0

1.11 Profiling Your OpenCL Kernel

The Intel FPGA SDK for OpenCL Profiler measures and reports performance datacollected during OpenCL kernel execution on the FPGA. The SDK's Profiler relies onperformance counters to gather kernel performance data. You can then reviewperformance data in the Profiler GUI.

1. Instrumenting the Kernel Pipeline with Performance Counters (--profile) on page107

To instrument the OpenCL kernel pipeline with performance counters, includethe --profile option of the aoc command when you compile your kernel.

2. Launching the Intel FPGA SDK for OpenCL Profiler GUI (report) on page 107



https://documentation.altera.com/#/link/mwh1391807516407/yyl1476199406907/en-us

https://www.altera.com/en_US/pdfs/literature/hb/opencl-sdk/archives/ug-aocl-best-practices-guide-16.0.pdf

You can use the Intel FPGA SDK for OpenCL Profiler report utility command tolaunch the Profiler GUI.

1.11.1 Instrumenting the Kernel Pipeline with Performance Counters (--profile)

To instrument the OpenCL kernel pipeline with performance counters, include the --profile option of the aoc command when you compile your kernel.

Attention: Instrumenting the Verilog code with performance counters increases hardwareresource utilization (that is, increases FPGA area usage) and typically decreasesperformance.

• To instrument the Verilog code in the <your_kernel_filename>.aocx file withperformance counters, invoke the aoc --profile<your_kernel_filename>.cl command.

Attention: When profiling multiple, different kernels, do not use the same kernelnames across different .aocx files. If the kernel names are the same,the profile data will be wrong for these kernels.

• Run your host application from a local disk to execute the<your_kernel_filename>.aocx file on your FPGA. During kernel execution,the performance counters throughout the kernel pipeline collects profileinformation. The host saves the information in a profile.mon monitordescription file in your current working directory.

Caution: Because of slow network disk accesses, running the host applicationfrom a networked directory might introduce delays between kernelexecutions. These delays might increase the overall execution time ofthe host application. In addition, they might introduce delays betweenkernel launches while the runtime stores profile output data to disk.

1.11.2 Launching the Intel FPGA SDK for OpenCL Profiler GUI (report)

You can use the Intel FPGA SDK for OpenCL Profiler report utility command to launchthe Profiler GUI. The Profiler GUI allows you to view kernel performance data statisticsthat the SDK's Profiler collects during kernel execution.

The SDK's Profiler stores performance data in a profile.mon file in your currentworking directory.

• To launch the Profiler GUI, invoke the aocl report<your_kernel_filename>.aocx profile.mon utility command.

1.12 Conclusion

You have now familiarized yourself with the Intel FPGA SDK for OpenCL design flowand the tools available to help you achieve your design goals. For more information onthe support statuses of the OpenCL APIs and programming language, refer toAppendix A: Support Statuses of OpenCL Features.

For in-depth information on optimizing your OpenCL kernel to maximize performance,refer to the Intel FPGA SDK for OpenCL Best Practices Guide.



Related Links

Intel FPGA SDK for OpenCL Best Practices Guide

1.13 Document Revision History

Table 3. Document Revision History of the Intel FPGA SDK for OpenCL ProgrammingGuide

Date Version Changes

October 2016 2016.10.31 • Rebranded the Altera SDK for OpenCL to Intel FPGA SDK for OpenCL.• Rebranded the Altera Offline Compiler to Intel FPGA SDK for OpenCL

Offline Compiler.• Deprecated and removed support for big-endian system, resulting in the

following documentation changes:— Removed the topic Compiling a Kernel for a Big-Endian System (--big-

endian).— Removed big-endian (64-bit) from the list of architectures that the

host application can target.• Added the topic Displaying the Compilation Environment of an OpenCL

Binary to introduce the aoc env command.• Removed Adding Source References to Optimization Reports (-g) because

the the offline compiler automatically includes source information in thecompiler reports and enables symbolic debug during emulation on an x86Linux machine.

• Added the topic Removing Debug Data from Compiler Reports and SourceCode from the .aocx File (-g0) to introduce the -g0 aoc command option.

• In Limitations of the Intel FPGA SDK for OpenCL Emulator, removed thelimitation "The Emulator does not support half data type".

• In Linking Your Host Application to the Khronos ICD Loader Library,provided an update that the Intel-supplied ICD Loader Library supportsOpenCL Specification version 1.0 as well as implemented APIs from theOpenCL Specification versions 1.1, 1.2, and 2.0.

• In Managing an FPGA Board, provided the following updates:— Noted that the SDK supports installation of multiple Custom Platforms.

To use the SDK utilities on each board in a multi-board installation, theAOCL_BOARD_PACKAGE_ROOT environment variable setting mustcorrespond to the Custom Platform subdirectory of the associatedboard.

— Noted that in a system with multiple Custom Platforms, the hostprogram should use ACD to discover the boards instead of directlylinking to the MMD libraries.

• Added the topic Reviewing Your Kernel's report.html File and includeddeprecation notice for the analyze-area utility option. As a result ofintroducing the HTML report, removed the following topics:— Reviewing Your Kernel's Resource Usage Information in the Area

Report— Accessing the Area Report— Layout of the Area Report

continued...





• In Multistep Design Flow, updated the design steps and the figure TheMultistep Intel FPGA SDK for OpenCL Design Flow to replace area reportwith the HTML report, and remove information on enabling -g.

• In Inferring a Register, corrected the text following the code snippet thatexplained how the offline compiler decide on the implementation of thearray in hardware.

• In Linking to the ICD Loader Library on Windows, updated the text toimprove clarity.

May 2016 2016.05.02 • Added a schematic diagram of the AOCL programming model in the AlteraSDK for OpenCL FPGA Programming Flow section.

• Moved the figure The AOCL FPGA Programming Flow to the Altera OfflineCompiler Kernel Compilation Flows section.

• Updated the figure The Multistep AOCL Design Flow and associated text toinclude the Review Area Report step.

• Added information on the single-cycle floating-point accumulator featurefor single work-item kernels. Refer to the Single-Cycle Floating-PointAccumulator for Single Work-Item Kernels section for more information.

• Added information in the Emulating Your OpenCL Kernel section on multi-device support for emulation alongside other OpenCL SDKs using ICD.

• Included information on the enhanced area report feature:— Added the option to invoke the analyze-area AOCL utility command

to generate an HTML area report.— Included a topic that describes the layout of the HTML area report.

• In Linking to the ICD Loader Library on Windows, removed $(AOCL_LDLIBS) from the code example for the modified Makefile.

• In the Multiple Work-Item Ordering sections for channels and pipes,modified the characteristics that the AOCL uses to check whether thechannel or pipe call is work-item invariant.

November 2015 2015.11.02 • Added the option to invoke the aoc command with no argument to accessthe Altera Offline Compiler help menu.

• Updated the Mutliple Host Threads section to specify that the OpenCLhost runtime is thread-safe.

• Updated the following figure and sections to reflect multiple kernel sourcefile support:— The figure The AOCL FPGA Programming Flow in the AOCL FPGA

Programming Flow section— The Compiling Your Kernel to Create Hardware Configuration File

section— The Compiling Your Kernel without Building Hardware (-c) section

• In Multiple Work-Item Ordering for Channels, removed misleading text.• Updated the Overview of Channels Implementation figure.• Updated the the following sections on OpenCL pipes:

— Overview of a Pipe Network Implementation figure in Overview of theOpenCL Pipe Functions

— Emulation support in Restrictions in OpenCL Pipes Implementationsection

— Replaced erroneous code with the correct syntax— Added link to Implementing I/O Pipes Using the io Attribute in

Declaring the Pipe Handle• Added a reminder in Programming an FPGA via the Host that you should

release an event object after use to prevent excessive memory usage.

continued...




May 2015 15.0.0 • In Guidelines for Naming the Kernel, added entry that advised againstnaming an OpenCL kernel kernel.cl.

• In Instrumenting the Kernel Pipeline with Performance Counters (--profile), specified that you should run the host application from a localdisk to avoid potential delays caused by slow network disk accesses.

• In Emulating and Debugging Your OpenCL Kernel, modified Caution noteto indicate that you must emulate a design targeting an SoC on a non-SoC board.

• In Emulating Your OpenCL Kernel, updated command to run the hostapplication and added instruction for overriding default temporarydirectory containing <process_ID>-libkernel.so.

• Introduced the --high-effort aoc command flag in ResolvingHardware Generation Fitting Errors during Kernel Compilation.

• In Enabling Double Precision Floating-Point Operations, introduced theOPENCL EXTENSION pragma for enabling double precision floating-pointoperations.

• Introduced OpenCL pipes support. Refer to Implementing OpenCL Pipes(and subsequent subtopics) and Creating a Pipe Object in Your HostApplication for more information.

• In AOCL Channels Extension: Restrictions, added code examples todemonstrate how to statically index into arrays of channel IDs.

• In Multiple Host Threads, added recommendation for synchronizingOpenCL host function calls in a multi-threaded host application.

• Introduced ICD and ACD support. Refer to Linking Your Host Applicationto the Khronos ICD Loader Library for more information.

• Introduced clGetBoardExtenstionFunctionAddressAltera forreferencing user-accessible functions. Refer to Accessing CustomPlatform-Specific Functions for more information.

December 2014 14.1.0 • Reorganized information flow. Information is now presented based on thetasks you might perform using the Altera SDK for OpenCL (AOCL) or theAltera RTE for OpenCL.

• Removed information pertaining to the --util <N> and -O3 AlteraOffline Compiler (AOC) options.

• Added the following information on PLDA QuickUDP IP core licensing inCompiling Your OpenCL Kernel:1. A PLDA QuickUDP IP core license is required for the Stratix V Network

Reference Platform or a Custom Platform that uses the QuickUDP IPcore.

2. Improper installation of the QuickUDP IP core licence causescompilation to fail with an error message that refers to the QuickTCPIP core.

• Added reminder that conditionally shifting a large shift register is notrecommended.

• Removed the Emulating Systems with Multiple Devices section. A newenvCL_CONTEXT_EMULATOR_DEVICE_ALTERA=<number_of_devices>command is now available for emulating multiple devices.

• Removed language support limitation from the Limitations of the AOCLEmulator section.

June 2014 14.0.0 • Removed the --estimate-throughput and --sw-dimm-partitionAOC options

• Added the -march=emulator, -g, --big-endian, and --profileAOC options

• --no-interleaving needs <global_memory_type> argument• -fp-relaxed=true is now --fp-relaxed• -fpc=true is now --fpc• For non-SoC devices, aocl diagnostic is now aocl diagnose

and aocl diagnose <device_name>

continued...




• program and flash need <device_name> arguments• Added Identifying the Device Name of Your FPGA Board• Added AOCL Profiler Utility• Added AOCL Channels Extension and associated subsections• Added Attributes for Channels• Added Match Data Layouts of Host and Kernel Structure Data Types• Added Register Inference and Shift Register Inference• Added Channels and Multiple Command Queues• Added Shared Memory Accesses for OpenCL Kernels Running on SoCs• Added Collecting Profile Data During Kernel Execution• Added Emulate and Debug Your OpenCL Kernel and associated

subsections• Updated AOC Kernel Compilation Flows• Updated -v• Updated Host Binary Requirement• Combined Partitioning Global Memory Accesses and Partitioning

Heterogeneous Global Memory Accesses into the section PartitioningGlobal Memory Accesses

• Updated AOC Allocation Limits in Appendix A• Removed max_unroll_loops, max_share_resources,

num_share_resources, and task kernel attributes• Added packed, and aligned(<N>) kernel attributes

December 2013 13.1.1 • Removed the section -W and -Werror, and replaced it with two sections: -W and -Werror.

• Updated the following contents to reflect multiple devices support:— The figure The AOCL FPGA Programming Flow.— --list-boards section.— -board <board_name> section.— AOCL Utilities for Managing an FPGA Board section.— Added the subsection Programming Multiple FPGA Devices under FPGA

Programming.• The following contents were added to reflect heterogeneous global

memory support:— --no-interleaving section.— buffer_location kernel attribute under Kernel Pragmas and

Attributes.— Partitioning Heterogeneous Global Memory Accesses section.

• Modified support status designations in Appendix: Support Statuses ofOpenCL Features.

• Removed information on OpenCL programming language restrictions fromthe section OpenCL Programming Language Implementation, andpresented the information in a new section titled OpenCL ProgrammingLanguage Restrictions.

November 2013 13.1.0 • Reorganized information flow.• Updated and renamed Intel FPGA SDK for OpenCL Compilation Flow to

AOCL FPGA Programming Flow.• Added figures One-Step AOC Compilation Flow and Two-Step AOC

Compilation Flow.• Updated the section Contents of the AOCL Version 13.1.

continued...




• Removed the following sections:— OpenCL Kernel Source File Compilation.— Using the Altera Offline Kernel Compiler.— Setting Up Your FPGA Board.— Targeting a Specific FPGA Board.— Running Your OpenCL Application.— Consolidating Your Kernel Source Files.— Aligned Memory Allocation.— Programming the FPGA Hardware.— Programming the Flash Memory of an FPGA.

• Updated and renamed Compiling the OpenCL Kernel Source File to AOCCompilation Flows.

• Renamed Passing File Scope Structures to OpenCL Kernels to UseStructure Arguments in OpenCL Kernels.

• Updated and renamed Augmenting Your OpenCL Kernel by SpecifyingKernel Attributes and Pragmas to Kernel Pragmas and Attributes.

• Renamed Loading Kernels onto an FPGA to FPGA Programming.• Consolidated Compiling and Linking Your Host Program, Host Program

Compilation Settings, and Library Paths and Links into a single section.• Inserted the section Preprocessor Macros.• Renamed Optimizing Global Memory Accesses to Partitioning Global

Memory Accesses.

June 2013 13.0 SP1.0 • Added the section Setting Up Your FPGA Board.• Removed the subsection Specifying a Target FPGA Board under Kernel

Programming Considerations.• Inserted the subsections Targeting a Specific FPGA Board and Generating

Compilation Reports under Compiling the OpenCL Kernel Source File.• Renamed File Scope __constant Address Space Qualifier to __constant

Address Space Qualifiers, and inserted the following subsections:— Function Scope __constant Variables.— File Scope __constant Variables.— Points to __constant Parameters from the Host.

• Inserted the subsection Passing File Scope Structures to OpenCL Kernelsunder Kernel Programming Considerations.

• Renamed Modifying Your OpenCL Kernel by Specifying Kernel Attributesand Pragmas to Augmenting Your OpenCL Kernel by Specifying KernelAttributes and Pragmas.

• Updated content for the unroll pragma directive in the sectionAugmenting Your OpenCL Kernel by Specifying Kernel Attributes andPragmas.

• Inserted the subsections Out-of-Order Command Queues and ModifyingHost Program for Structure Parameter Conversion under HostProgramming Considerations.

• Updated the sections Loading Kernels onto an FPGA UsingclClreateProgramWithBinary and Aligned Memory Allocation.

• Updated flash programming instructions.• Renamed Optional Extensions in Appendix B to Atomic Functions, and

updated its content.• Removed Platform Layer and Runtime Implementation from Appendix B.

continued...




May 2013 13.0.1 • Explicit memory fence functions are now supported; the entry is removedfrom the table OpenCL Programming Language Implementation.

• Updated the section Programming the Flash Memory of an FPGA.• Added the section Modifying Your OpenCL Kernel by Specifying Kernel

Attributes and Pragmas to introduce kernel attributes and pragmas thatcan be implemented to optimize kernel performance.

• Added the section Optimizing Global Memory Accesses to discuss datapartitioning.

• Removed the section Programming the FPGA with the aocl programCommand from Appendix A.

May 2013 13.0.0 • Updated compilation flow.• Updated kernel compiler commands.• Included Altera SDK for OpenCL Utility commands.• Added the section OpenCL Programming Considerations.• Updated flash programming procedure and moved it to Appendix A.• Included a new clCreateProgramWithBinary FPGA hardware

programming flow.• Moved the hostless clCreateProgramWithBinary hardware

programming flow to Appendix A under the title Programming the FPGAwith the aocl program Command.

• Moved updated information on allocation limits and OpenCL languagesupport to Appendix B.

November 2012 12.1.0 Initial release.



2 Intel FPGA SDK for OpenCL Advanced FeaturesThe Intel FPGA SDK for OpenCL provides advanced features you can use to controlcertain aspects of the design architecture and the Intel FPGA SDK for OpenCL OfflineCompiler's behavior.

2.1 OpenCL Library

An OpenCL library is a single file that contains multiple functions. Each function iscomprised of data processing logic that works at any clock frequency. You can createan OpenCL library in OpenCL or RTL. You can then include this library file and use thefunctions inside your OpenCL kernels.

Figure 12. Overview of Intel FPGA SDK for OpenCL's Library Support

OpenCL

Verilog

VHDL OpenCL Kernel

OpenCL LibraryIntel FPGA SDK for OpenCL

Offline CompilerOffline Compiler

Executable File (.aocx)

You may use a previously-created library or create your own library. To use an OpenCLlibrary, you do not require in-depth knowledge in hardware design or in theimplementation of library components. To create an OpenCL library, you need tocreate the following files and components:

Table 4. Necessary Files and Components for Creating an OpenCL Library

File or Component Description

RTL Components

RTL source files Verilog, System Verilog, or VHDL files that define the RTLcomponent.Additional files such as Quartus Prime IP File (.qip),Synopsys Design Constraints File (.sdc), and Tcl Script File(.tcl) are not allowed.

continued...

2 Intel FPGA SDK for OpenCL Advanced Features






File or Component Description

eXtensible Markup Language File (.xml) Describes the properties of the RTL component. The IntelFPGA SDK for OpenCL Offline Compiler uses theseproperties to integrate the RTL component into the OpenCLpipeline.

Header file (.h) A C-style header file that declares the signatures offunction(s) that are implement by the RTL component.

OpenCL emulation model file (.cl) Provides C model for the RTL component that is used onlyfor emulation. Full hardware compilations use the RTLsource files.

OpenCL Functions

OpenCL source files (.cl) Contains definitions of the OpenCL functions. Thesefunctions are used during emulation and full hardwarecompilations.

Header file (.h) A C-style header file that declares the signatures offunction(s) that are defined in the OpenCL source files.

Understanding RTL Modules and the OpenCL Pipeline on page 116This section provides an overview of how the Intel FPGA SDK for OpenCL OfflineCompiler integrates RTL modules into the Intel FPGA SDK for OpenCL pipelinearchitecture.

Packaging an OpenCL Helper Function File for an OpenCL Library on page 125Before creating an OpenCL library file, package each OpenCL source file with helperfunctions into a .aoco file.

Packaging an RTL Component for an OpenCL Library on page 125Before creating an OpenCL library file, package each RTL component into a .aocofile.

Verifying the RTL Modules on page 128The creator of an OpenCL library is responsible for verifying the RTL modules withinthe library, both as stand-alone entities and as part of an OpenCL system.

Packaging Multiple Object Files into a Library File on page 129After creating the .aoco files that you want to include into an OpenCL library,package them into a library file by invoking the Intel FPGA SDK for OpenCLlibrary utility command option.

Specifying an OpenCL Library when Compiling an OpenCL Kernel on page 129To use an OpenCL library in an OpenCL kernel, specify the library file name anddirectory when you compile the kernel.

Using an OpenCL Library that Works with Simple Functions (Example 1) on page 130Intel provides an OpenCL library design example of a simple kernel that uses alibrary containing RTL implementations of three double-precision functions: sqrt,rsqrt, and divide.

Using an OpenCL Library that Works with External Memory (Example 2) on page 131Intel provides an OpenCL library design example of a simple kernel that uses alibrary containing two RTL modules that communicate with global memory.

OpenCL Library Command-Line Options on page 132Both the Intel FPGA SDK for OpenCL Offline Compiler's set of commands and theSDK utility include options you can invoke to perform OpenCL library-related tasks.

Related Links

OpenCL Library Command-Line Options on page 132



Both the Intel FPGA SDK for OpenCL Offline Compiler's set of commands and theSDK utility include options you can invoke to perform OpenCL library-related tasks.

2.1.1 Understanding RTL Modules and the OpenCL Pipeline

The OpenCL library feature allows you to use RTL modules, written in Verilog,SystemVerilog, or VHDL, inside OpenCL kernels. This section provides an overview ofhow the Intel FPGA SDK for OpenCL Offline Compiler integrates RTL modules into theIntel FPGA SDK for OpenCL pipeline architecture.

You might want to use RTL modules under the following circumstances:

• You want to use optimized and verified RTL modules in OpenCL kernels withoutrewriting the modules as OpenCL functions.

• You want to implement OpenCL kernel functionality that you cannot expresseffectively in OpenCL.

Overview: Intel FPGA SDK for OpenCL Pipeline Approach

The following figure depicts the architecture of an Intel FPGA SDK for OpenCLpipeline:

Figure 13. Parallel Execution Model of AOCL Pipeline StagesThe operations on the right represent the SDK's pipeline implementation of theOpenCL kernel code on the left. Each yellow box is an operation or data value found inthe pipeline. The number associated with each operation represents the number ofthreads in the pipeline.

Load A Load B

Add

Store C

gid

gid

gid

2

1

0

2 2

3

1

Add

oready

iready

ivalid

ovalid

void kernel pe(global int* A, global int* B, global int* C){

int gid = get_global_id(0); int a = A[gid]; int b = B[gid]; C[gid] = a + b;}

Assume each level of operation is one stage in the pipeline. At each stage, the IntelFPGA SDK for OpenCL Offline Compiler executes all operations in parallel by thethread existing at that stage. For example, thread 2 executes Load A, Load B, andcopies the current global ID (via gid) to the next pipeline stage. Similar to thepipelined execution on instructions in reduced instruction set computing (RISC)processors, the SDK's pipeline stages also execute in parallel. The threads willadvance to the next pipeline stage only after all the stages have completed execution.



Some operations are capable of stalling the Intel FPGA SDK for OpenCL pipeline.Examples of such operations include variable latency operations like memory load andstore operations. To support stalls, ready and valid signals need to propagatethroughout the pipeline so that the offline compiler can schedule the pipeline stages.However, ready signals are not necessary if all operations have fixed latency. In thesecases, the offline compiler optimizes the pipeline to statically schedule the operations,which significantly reduces the logic necessary for pipeline implementation.

Integration of an RTL Module into the Intel FPGA SDK for OpenCL Pipeline

When you specify an OpenCL library during kernel compilation, the offline compilerintegrates the RTL module within the library into the overall pipeline.

Figure 14. Integration of an RTL Module into an Intel FPGA SDK for OpenCL PipelineThis figure depicts the integration of the RTL module myMod into the pipeline depictedin Figure 13 on page 116.

Load A Load B

myMod

Store C

gid

gid

gid

4

3

0

4 4

5

3

myMod

oready

iready

ivalid

ovalid

extern int myMod(int, int);void kernel pe(global int* A, global int* B, global int* C){

int gid = get_global_id(0); int a = A[gid]; int b = B[gid]; C[gid] = myMod(a, b);}

2

1

gid2

gid1

3 cycles

The RTL module depicted in Figure 14 on page 117 has a balanced latency where thethreads of the RTL module match the number of pipeline stages. A balanced latencyallows the threads of the RTL module to execute without stalling the SDK's pipeline.

Setting the latency of the RTL module in the RTL specification file allows the offlinecompiler to balance the pipeline latency. RTL supports Avalon® Streaming (Avalon-ST)interfaces; therefore, the latency of the RTL module can be variable (that is, notfixed). However, the variability in the latency should be small in order to maximizeperformance. In addition, specify the latency in the <RTL module descriptionfile name>.xml specification file so that the RTL module experiences a goodapproximation of the actual latency in steady state.

2.1.1.1 Stall-Free RTL

The Intel FPGA SDK for OpenCL Offline Compiler can optimize hardware resourceusage and performance by removing stall logic around an RTL module with fixedlatency.



An RTL module that has a variable latency and uses Avalon-ST input and outputsignals can wait until input data is ready. Conversely, the Intel FPGA SDK for OpenCLpipeline can stall until it receives valid output data from the RTL module. For an RTLmodule with a fixed latency, you can remove an RTL stall by modifying the <RTLmodule description file name>.xml specification file, as described below.

To instruct the offline compiler to remove stall logic around the RTL module, ifappropriate, set the IS_STALL_FREE attribute under the FUNCTION element to"yes". This modification informs the offline compiler that the RTL module producesvalid data every EXPECTED_LATENCY cycle(s). EXPECTED_LATENCY is an attributeyou specify in the .xml file under the FUNCTION element. Specify a value forEXPECTED_LATENCY such that the latency equals the number of pipeline stages in themodule. An inaccurate EXPECTED_LATENCY value will cause the RTL module to be outof sync with the rest of the pipeline.

Note: The offline compiler expects an RTL module with fixed or variable latency to haveproper Avalon-ST input and output parameters (that is, ivalid, ovalid, iready,and oready). For an RTL module with fixed latency, the output signals (that is,ovalid and oready) can have constant high values, and the input ready signal (thatis, iready) can be ignored.

A stall-free RTL module might receive an invalid input signal (that is, ivalid is low).In this case, the module ignores the input and produces invalid data on the output.For a stall-free RTL module without an internal state, it might be easier to propagatethe invalid input through the module. However, for an RTL module with an internalstate, you must handle an ivalid=0 input carefully.

2.1.1.2 RTL Reset and Clock Signals

Resets and clocks of RTL modules are connected to the same clock and reset driversas the rest of the OpenCL pipeline.

Because of the common clock and reset drivers, an RTL module runs in the same clockdomain as the OpenCL kernel. The module is reset only when the OpenCL kernel isfirst loaded onto the FPGA, either via Intel FPGA SDK for OpenCL program utility orthe clCreateProgramwithBinary host function. In particular, if the host restarts akernel via successive clEnqueueNDRangeKernel or clEnqueueTask invocations,the associated RTL modules will not reset in between these restarts.

The following steps outline the process of setting the kernel clock frequency:

1. The Quartus Prime software's Fitter applies an aggressive constraint on the kernelclock.

2. The Quartus Prime software's TimeQuest Timing Analyzer performs static timinganalysis to determine the frequency that the Fitter actually achieves.

3. The phase-locked loop (PLL) that drives the kernel clock sets the frequencydetermined in Step 2 to be the kernel clock frequency.

2.1.1.3 XML Syntax of an RTL Module

This section provides the syntax of a simple XML specification file for an RTL modulethat implements double-precision square root function. The RTL module isimplemented in VHDL with a Verilog wrapper.



The following XML specification file is for an RTL module named my_fp_sqrt_double(line 2.5) that implements an OpenCL helper function named my_sqrtfd (line 2).

1: <RTL_SPEC> 2: <FUNCTION name="my_sqrtfd"2.5: module="my_fp_sqrt_double"> 3: <ATTRIBUTES>3.5: <PARAMETER name="WIDTH" value="32"/> 4: <IS_STALL_FREE value="yes"/> 5: <IS_FIXED_LATENCY value="yes"/> 6: <EXPECTED_LATENCY value="31"/> 7: <CAPACITY value="1"/> 8: <HAS_SIDE_EFFECTS value="no"/> 9: <ALLOW_MERGING value="yes"/> 10: </ATTRIBUTES> 11: <INTERFACE> 12: <AVALON port="clock" type="clock"/> 13: <AVALON port="resetn" type="resetn"/> 14: <AVALON port="ivalid" type="ivalid"/> 15: <AVALON port="iready" type="iready"/> 16: <AVALON port="ovalid" type="ovalid"/> 17: <AVALON port="oready" type="oready"/> 18: <INPUT port="datain" width="64"/> 19: <OUTPUT port="dataout" width="64"/> 20: </INTERFACE> 21: <C_MODEL> 22: <FILE name="c_model.cl" /> 23: </C_MODEL> 24: <REQUIREMENTS> 25: <FILE name="my_fp_sqrt_double_s5.v" /> 26: <FILE name="fp_sqrt_double_s5.vhd" /> 27: </REQUIREMENTS> 28: </FUNCTION> 29: </RTL_SPEC>

Table 5. Elements and Attributes in the XML Specification File

XML Element Description

RTL_SPEC Top-level element in the XML specification file. There can only be one such top-level element in the file. In this example, the name RTL_SPEC is historic andcarries no file-specific meaning.

FUNCTION Element that defines the OpenCL function that the RTL module implements. Thename attribute within the FUNCTION element specifies the function's name.You may have multiple FUNCTION elements, each declaring a different functionthat you can call from the OpenCL kernel. The same RTL module can implementmultiple functions by specifying different parameters.

ATTRIBUTES Element containing other XML elements that describe various characteristics(for example, latency) of the RTL module. The example RTL module takes onePARAMETER setting named WIDTH, which has a value of 32. Refer to Table 6 onpage 120 for more details other ATTRIBUTES-specific elements.Note: If you create multiple OpenCL helper functions for different modules, or

use the same RTL module with different PARAMETER settings, you mustcreate a separate FUNCTION element for each function.

INTERFACE Element containing other XML elements that describe the RTL module'sinterface. The example XML specification file shows the Avalon-ST interfacesignals that every RTL module must provide (that is, clock, resetn, ivalid,

continued...




iready, ovalid, and oready). The signal names must match the onesspecified in the .xml file. An error will occur during library creation if a signalname is inconsistent.

C_MODEL Element specifying one or more files that implement OpenCL C model for thefunction. The model is used only during emulation. However, the C_MODELelement and the associated file(s) must be present when you create the libraryfile.

REQUIREMENTS Element specifying one or more RTL resource files (thatis, .v, .sv, .vhd, .hex, and .mif). The specified paths to these files arerelative to the location of the XML specification file. Each RTL resource filebecomes part of the associated Qsys component that corresponds to the entireOpenCL system.Note: The Intel FPGA SDK for OpenCL library feature does not support .qip

files. An Intel FPGA SDK for OpenCL Offline Compiler error will occur ifyou compile an OpenCL kernel while using a library that includes anunsupported resource file type.

2.1.1.3.1 XML Elements for ATTRIBUTES

In the XML specification file of the RTL module within an Intel FPGA SDK for OpenCLlibrary, there are XML elements under ATTRIBUTES that you can specify to set themodule's characteristics.

Table 6. XML Elements Associated with the ATTRIBUTES Element in the XMLSpecification File of an RTL Module

Attention: Except for IS_STALL_FREE and EXPECTED_LATENCY, all elements have safe values. If youare unsure which value you should specify for an attribute, set it to the safe value. Compilingyour kernel with a library that uses safe values will result in functional hardware. However,the hardware might be larger than the actual size.


IS_STALL_FREE Instructs the Intel FPGA SDK for OpenCL Offline Compiler to remove all stalllogic around the RTL module.Set IS_STALL_FREE to "yes" to indicate that the module neither generatesstalls internally nor can it properly handle incoming stalls. The module simplyignores its stall input. If you set IS_STALL_FREE to "no", the module mustproperly handle all stall and valid signals.Note: If you set IS_STALL_FREE to "yes", you must also set

IS_FIXED_LATENCY to "yes". Also, if the RTL module has an internalstate, it must properly handle ivalid=0 inputs.

An incorrect IS_STALL_FREE setting will lead to incorrect results in hardware.

IS_FIXED_LATENCY Indicates whether the RTL module has a fixed latency.Set IS_FIXED_LATENCY to "yes" if the RTL module always takes known anumber of clock cycles to compute its output. The value you assign to theEXPECTED_LATENCY element specifies the number of clock cycles.The safe value for IS_FIXED_LATENCY is "no".Note: For a given module, you may set IS_FIXED_LATENCY to "yes" and

IS_STALL_FREE to "no". Such a module produces its output in a fixednumber of clock cycles and handles stall signals properly.

EXPECTED_LATENCY Specifies the expected latency of the RTL module.If you set IS_FIXED_LATENCY to "yes", the EXPECTED_LATENCY valueindicates the number of pipeline stages inside the module. In this case, youmust set this value to be the exact latency of the module. Otherwise, the offlinecompiler will generate incorrect hardware.

continued...




For a module with variable latency, the offline compiler balances the pipelinearound this module to the EXPECTED_LATENCY value that you specify. Thespecified value and the actual latency might differ, which might affect thenumber of stalls inside the pipeline. However, the resulting hardware will becorrect.

CAPACITY Specifies the number of multiple inputs that this module can processsimultaneously. You must specify a value for CAPACITY if you also setIS_STALL_FREE="no" and IS_FIXED_LATENCY="no". Otherwise, you do notneed to specify a value for CAPACITY.If CAPACITY is strictly less than EXPECTED_LATENCY, the offline compiler willautomatically insert capacity-balancing FIFO buffers after this module whennecessary.The safe value for CAPACITY is 1.

HAS_SIDE_EFFECTS Indicates whether the RTL module has side effects. Modules that have internalstates or communicate with external memories are examples of modules withside effects.Set HAS_SIDE_EFFECTS to "yes" to indicate that the module has side effects.Specifying HAS_SIDE_EFFECTS to "yes" ensures that optimization efforts donot remove calls to modules with side effects.Stall-free modules with side effects (that is, IS_STALL_FREE="yes" andHAS_SIDE_EFFECTS="yes") must properly handle ivalid=0 input casesbecause the module might receive invalid data occasionally.The safe value for HAS_SIDE_EFFECTS is "yes".

ALLOW_MERGING Instructs the offline compiler to merge multiple instances of the RTL module.Set ALLOW_MERGING to "yes" to allow merging of multiple instances of themodule. Intel recommends setting ALLOW_MERGING to "yes".The safe value for ALLOW_MERGING is "no".Note: Marking the module with HAS_SIDE_EFFECTS="yes" does not prevent

merging.

2.1.1.3.2 XML Elements for INTERFACE

In the XML specification file of the RTL module within an Intel FPGA SDK for OpenCLlibrary, there are XML elements under INTERFACE that you can define to specifyaspects of the RTL module's interface (for example, Avalon-ST interface).

Table 7. Mandatory XML Elements Associated with the INTERFACE Eement in the XMLSpecification File of an RTL Module


INPUT Specifies the input parameter of the RTL module.INPUT attributes:• port—Specifies the port name of the RTL module.• width—Specifies the width of the port in bits.

AOCL only supports widths that correspond to OpenCL data types (that is, 8(uchar), 16, 32, 64, 128, 256, 512, and 1024 bits (long16)).Note: Size of a type3 vector is 4 x sizeof(type), giving the impression that

valid sizes of 24, 48, 96, and 192 bits are unsupported.The input parameters are concatenated to form the input stream.Aggregate data structures such as structs and arrays are not supported asinput parameters.

OUTPUT Specifies the output parameter of the RTL module.OUTPUT attributes:

continued...




• port—Specifies the port name of the RTL module.• width—Specifies the width of the port in bits.

The SDK only supports widths that correspond to OpenCL data types (thatis, 8 (uchar), 16, 32, 64, 128, 256, 512, and 1024 bits (long16)).Note: Size of type3 vector is 4 x sizeof(type), giving the impression that

valid sizes of 24, 48, 96, and 192 bits are unsupported.The return value from the input stream is sent out via the output parameter onthe output stream.Aggregate data structures such as structs and arrays are not supported asinput parameters.

If your RTL module communicates with external memory, you need to includeadditional XML elements:

<MEM_INPUT port="m_input_A" access="readonly"/><MEM_INPUT port="m_input_sum" access ="readwrite"/><AVALON_MEM port="avm_port0" width="512" burstwidth="5" optype="read" buffer_location=""/>

Table 8. Additional XML Elements to Support External Memory Access


MEM_INPUT Describes a pointer input to the RTL module.MEM_INPUT attributes:• port—Specifies the name of the pointer input.• access—Specifies to the Intel FPGA SDK for OpenCL Offline Compiler how

the RTL module will use this pointer. Valid access values are readonly andreadwrite. If the RTL module only writes with this pointer, assignreadwrite to access.

Because all pointers to external memory must be 64 bits, there is no widthattribute associated with MEM_INPUT.

AVALON_MEM Declares the Avalon-MM interface for your RTL module.AVALON_MEM attributes:• port—Specifies the root of the corresponding port names in the RTL

module. For example, if port has a value of avm_port0_, the names of allAvalon-MM interface ports for the RTL module will start with avm_port0_.

• width—Specifies the data width, which must match the correspondingwidth value in the accelerator board's board_spec.xml file. Within theboard_spec.xml file, the width value is specified in the interfaceelement under global_mem.For more information, refer to the global_mem section under XML Elements,Attributes, and Parameters in the board_spec.xml File in the Intel FPGA SDKfor OpenCL Custom Platform Toolkit User Guide.

• burstwidth—Specifies the number of bits required to represent burst size.Use burstwidth = log(maxburst) +1 to calculate the burst size, wheremaxburst is the corresponding maximum burst size specified in theboard_spec.xml file. For example, if maxburst=16, burstwidth=5.

• optype—Specifies either the Avalon-MM port is reading (read) or writing(write) from external memory. You can only assign either read or writeto optype.

• buffer_location—Supports heterogeneous memory. Leave this attributeblank because the heterogeneous memory compilation flow is currentlyuntested.



For the AVALON_MEM element defined in the code example above, the correspondingRTL module ports are as follows:

output avm_port0_enable,input [511:0] avm_port0_readdata,input avm_port0_readdatavalid,input avm_port0_waitrequest,output [31:0] avm_port0_address,output avm_port0_read,output avm_port0_write,input avm_port0_writeack,output [511:0] avm_port0_writedata,output [63:0] avm_port0_byteenable,output [4:0] avm_port0_burstcount,

There is no assumed correspondence between pointers that you specify withMEM_INPUT and the Avalon-MM interfaces that you specify with AVALON_MEM. An RTLmodule can use a single pointer to address zero to multiple Avalon-MM interfaces.

Related Links

XML Elements, Attributes, and Parameters in the board_spec.xml File: global_mem

2.1.1.4 Interaction between RTL Module and External Memory

Implement code to allow your RTL module to interact with external memory only if theinteraction is necessary. For operations like reading from and writing to externalmemory on every kernel invocation, instruct the OpenCL kernel to perform theoperation. To do so, you can create an OpenCL helper function for the OpenCL kernelin the same Intel FPGA SDK for OpenCL library as the RTL module.

The following examples demonstrate how to structure code in an RTL module for easyintegration into an OpenCL library:

Table 9. Example Code in an RTL Module that Interacts with External Memory

Complex RTL Module Simplified RTL Module

// my_rtl_fn does:// out_ptr[idx] = fn(in_ptr[idx])my_rtl_fn (in_ptr, out_ptr,idx);

int in_value = in_ptr[idx];// my_rtl_fn now does: out = fn(in)int out_value = my_rtl_fn (in_value);out_ptr[idx] = out_value;

The complex RTL module on the left reads a value from external memory, performs ascalar function on the value, and then writes the value back to global memory. Suchan RTL module is difficult to describe when you integrate it into an OpenCL library. Inaddition, this RTL module is harder to verify and causes very conservative pointeranalysis in the Intel FPGA SDK for OpenCL Offline Compiler.

The simplified RTL module on the right provides the same overall functionality as thecomplex RTL module. However, the simplified RTL module only performs a scalar-to-scalar calculation without connecting to global memory. Integrating this simplified RTLmodule into the OpenCL library makes it much easier for the offline compiler toanalyze the resulting OpenCL kernel.

There are times when an RTL module requires an Avalon-MM port to communicatewith external memory. This Avalon-MM port connects to the same arbitration networkto which all other global load and store units in the OpenCL kernels connect.




If an RTL module receives a memory pointer as an argument, the offline compilerenforces the following memory model:

• If an RTL module writes to a pointer, nothing else in the OpenCL kernel can readfrom or write to this pointer.

• If an RTL module reads from a pointer, the rest of the OpenCL kernel and otherRTL modules may also read from this pointer.

• You may set the access field of the MEM_INPUT attribute to specify how the RTLmodule uses the memory pointer. Ensure that you set the value for accesscorrectly because there is no way to verify the value.

2.1.1.5 Order of Threads Entering an RTL Module

Do not assume that threads entering an RTL module follow a defined order. Inaddition, an RTL module can reorder threads. As a result, thread 0 does notnecessarily enter the module before thread 1.

2.1.1.6 OpenCL C Model of an RTL Module

Each RTL module within an OpenCL library must have an OpenCL C model. TheOpenCL C model verifies the overall OpenCL system during emulation.

Example OpenCL C model file for a square root function:

double my_sqrtfd (double a){ return sqrt(a);}

Intel recommends that you emulate your OpenCL system. If you decide not toemulate your OpenCL system, create an empty function with a name that matches thefunction name you specified in the XML specification file.

Related Links

XML Syntax of an RTL Module on page 118This section provides the syntax of a simple XML specification file for an RTLmodule that implements double-precision square root function.

2.1.1.7 Potential Incompatibility between RTL Modules and PartialReconfiguration

When creating an OpenCL library using RTL modules, you might encounter PartialReconfiguration (PR)-related issues.

Consider a situation where you create and verify your library on a device that does notsupport PR. If a library user then uses the library's RTL module inside a PR region, themodule might not function correctly after PR.

To ensure that the RTL modules function correctly on a device that uses PR:

• The RTL modules do not use memory logic array blocks (MLABs) with initializedcontent.

• The RTL modules do not make any assumptions regarding the power-up values ofany logic.



2.1.2 Packaging an OpenCL Helper Function File for an OpenCL Library

Before creating an OpenCL library file, package each OpenCL source file with helperfunctions into a .aoco file. Unlike RTL modules, you do not need to create an XMLspecification file.

In general, you do not need to create a library to share helper functions written inOpenCL. You can distribute a helper function in source form (for example,<shared_file>.cl) and then insert the line #include "<shared_file>.cl" inthe OpenCL kernel source code.

Consider creating a library under the following circumstances:

• The helper functions are in multiple files and you want to simplify distribution.

• You do not want to expose the helper functions' source code.

The helper functions are stored as LLVM IR, an assembly-like language, withoutcomments inside the associated library.

Hardware generation is not necessary for the creation of a .aoco file. Compile theOpenCL source file using the -c offline compiler command option.

Note: A library can only include OpenCL helper functions. The Intel FPGA SDK for OpenCLOffline Compiler will issue an error message if the library contains OpenCL kernels.

• To package an OpenCL source file into a .aoco file, invoke the followingcommand: aoc -c -shared <OpenCL_source_file_name>.cl -o<OpenCL_object_file_name>.aoco

where the -shared offline compiler command option instructs the compiler tocreate a .aoco file that is suitable for inclusion into an OpenCL library.

Related Links

• Packaging Multiple Object Files into a Library File on page 129After creating the .aoco files that you want to include into an OpenCL library,package them into a library file by invoking the Intel FPGA SDK for OpenCLlibrary utility command option.

• Specifying an OpenCL Library when Compiling an OpenCL Kernel on page 129To use an OpenCL library in an OpenCL kernel, specify the library file name anddirectory when you compile the kernel.

2.1.3 Packaging an RTL Component for an OpenCL Library

Before creating an OpenCL library file, package each RTL component into a .aoco file.

Hardware generation is not necessary for the creation of a .aoco file. Compile theOpenCL source file using the -c Intel FPGA SDK for OpenCL Offline Compilercommand option.

• To package an RTL component into a .aoco file, invoke the following command:aoc -c <RTL component description file name>.xml -o <RTLobject file name>.aoco



Related Links

• Packaging Multiple Object Files into a Library File on page 129After creating the .aoco files that you want to include into an OpenCL library,package them into a library file by invoking the Intel FPGA SDK for OpenCLlibrary utility command option.

• Verifying the RTL Modules on page 128The creator of an OpenCL library is responsible for verifying the RTL moduleswithin the library, both as stand-alone entities and as part of an OpenCLsystem.

• Specifying an OpenCL Library when Compiling an OpenCL Kernel on page 129To use an OpenCL library in an OpenCL kernel, specify the library file name anddirectory when you compile the kernel.

2.1.3.1 Restrictions and Limitations in RTL Support for the Intel FPGA SDK forOpenCL Library Feature

The Intel FPGA SDK for OpenCL supports the use of RTL modules in an OpenCL librarywith some restrictions and limitations.

When creating your RTL module, ensure that it operates within the followingrestrictions:

• An RTL module must contain one Avalon-ST interface. In particular, a single readyor valid logic must control all the inputs.

You have the option to provide the necessary Avalon-ST ports but declare the RTLmodule as stall-free. In this case, you do not have to implement proper stallbehavior because the Intel FPGA SDK for OpenCL Offline Compiler creates awrapper for your module. Refer to XML Syntax of an RTL Module and Using anOpenCL Library that Works with Simple Functions (Example 1) for more syntaxand usage information, respectively.

Note: You must handle ivalid signals properly if your RTL module has aninternal state. Refer to Stall-Free RTL for more information.

• The RTL module must work correctly with exactly one clock, regardless of clockfrequency.

• Data input and output sizes must match valid OpenCL data types, from 8 bits forchar to 1024 bits for long16.

For example, if you work with 24-bit values inside an RTL module, declare inputsto be 32 bits and declare function signature in the SDK's library header file toaccept the uint data type. Then, inside the RTL module, accept the 32-bit inputbut discard the top 8 bits.

• RTL modules cannot connect to external I/O signals. All input and output signalsmust come from an OpenCL kernel.

• An RTL module must have a clock port, a resetn port, and Avalon-ST input andoutput ports (that is, ivalid, ovalid, iready, oready). Name the ports asspecified here.

• RTL modules that communicate with external memory must have Avalon Memory-Mapped (Avalon-MM) port parameters that match the corresponding CustomPlatform parameters. The offline compiler does not perform any width or burstadaptation.



• RTL modules that communicate with external memory must behave as follows:

— They cannot burst across the burst boundary.

— They cannot make requests every clock cycle and stall the hardware bymonopolizing the arbitration logic. An RTL module must pause its requestsregularly to allow other load or store units to execute their operations.

• RTL modules cannot act as stand-alone OpenCL kernels. RTL modules can only behelper functions and be integrated into an OpenCL kernel during kernelcompilation.

• Every function call that corresponds to RTL module instantiation is completelyindependent of other instantiations. There is no hardware sharing.

• Do not incorporate kernel code (that is, functions marked as kernel) intoa .aoclib library file. Incorporating kernel code into the library file causes theoffline compiler to issue an error message. You may incorporate helper functionsinto the library file.

• An RTL component must receive all its inputs at the same time. A single ivalidinput signifies that all inputs contain valid data.

• The SDK does not support I/O RTL modules.

• You can only set RTL module parameters in the <RTL module descriptionfile name>.xml specification file, not the OpenCL kernel source file. To use thesame RTL module with multiple parameters, create a separate FUNCTION tag foreach parameter combination.

Currently, the SDK's RTL module support for the library feature has the followinglimitations:

• You can only pass data inputs to an RTL module by value via the OpenCL kernelcode. Do not pass data inputs to an RTL module via pass-by reference, structs, orchannels. In the case of channel data, extract the data from the channel first andthen pass the extracted the scalar data to the RTL module.

Note: Passing data inputs to an RTL module via pass-by reference or structs willcause a fatal error to occur in the offline compiler.

• The debugger (for example, GDB for Linux) cannot step into a library functionduring emulation. In addition, optimization and area reports will not include codeline numbers beside the library functions.

• Names of RTL module source files cannot conflict with the file names of Intel FPGASDK for OpenCL Offline Compiler IP. Both the RTL module source files and theoffline compiler IP files are stored in the <kernel file name>/system/synthesis/submodules directory. Naming conflicts will cause existing offlinecompiler IP files in the directory to be overwritten by the RTL module source files.

• The SDK does not support .qip files. You must manually parse nested .qip filesto create a flat list of RTL files.



• It is very difficult to debug an RTL module that works correctly on its own butworks incorrectly as part of an OpenCL kernel. Double check all parameters underthe ATTRIBUTES element in the <RTL module description filename>.xml file.

• All offline compiler area estimation tools assume that RTL module area is 0. TheSDK does not currently support the capability of specifying an area model for RTLmodules.

• RTL modules cannot access a 2x clock that is in-phase with the kernel clock and attwice the kernel clock frequency.

Related Links

• XML Syntax of an RTL Module on page 118This section provides the syntax of a simple XML specification file for an RTLmodule that implements double-precision square root function.

• Using an OpenCL Library that Works with Simple Functions (Example 1) on page130

Intel provides an OpenCL library design example of a simple kernel that uses alibrary containing RTL implementations of three double-precision functions:sqrt, rsqrt, and divide.

• Stall-Free RTL on page 117The Intel FPGA SDK for OpenCL Offline Compiler can optimize hardwareresource usage and performance by removing stall logic around an RTL modulewith fixed latency.

2.1.4 Verifying the RTL Modules

The creator of an OpenCL library is responsible for verifying the RTL modules withinthe library, both as stand-alone entities and as part of an OpenCL system.

1. Verify each RTL module using standard hardware verification methods.

2. Modify one of Intel FPGA SDK for OpenCL library design examples to test your RTLmodules inside the overall OpenCL system.

This testing step is critical to prevent library users from encountering hardwareproblems.

It is crucial that you set the values for the ATTRIBUTES elements in the XMLspecification file correctly. Because you cannot simulate the entire OpenCL system,you will likely not discover problems caused by interface-level errors untilhardware runs.

3. Note: The Intel FPGA SDK for OpenCL library utility performs consistencychecks on the XML specification file and source files, with some limitations.

Invoke the aocl library [<command option>] command.

• For a list of supported <command options>, invoke the aocl librarycommand.

• The library utility does not detect errors in values assigined to elementswithin the ATTRIBUTES, MEM_INPUT, and AVALON_MEM elements in the XMLspecification file.

• The library utility does not detect RTL syntax errors. You must check the<your_kernel_filename>/quartus_sh_compile.log file for RTL syntaxerrors. However, parsing the errors might be time consuming.



2.1.5 Packaging Multiple Object Files into a Library File

After creating the .aoco files that you want to include into an OpenCL library,package them into a library file by invoking the Intel FPGA SDK for OpenCL libraryutility command option.

• To package multiple object files into a single library file, invoke the followingcommand: aocl library create -o <library file name>.aoclib<object file 1>.aoco [<object file 2>.aoco ... <object fileN>.aoco]

The aocl library utility command creates a <library file name>.aocliblibrary file, which includes the .aoco object files you specify in the command. Alibrary file may contain both RTL-based object files and OpenCL-based object files.

2.1.6 Specifying an OpenCL Library when Compiling an OpenCL Kernel

To use an OpenCL library in an OpenCL kernel, specify the library file name anddirectory when you compile the kernel.

Important: Using a library does not reduce kernel compilation time.

• To specify an OpenCL library to the Intel FPGA SDK for OpenCL Offline Compiler,invoke the following command: aoc -l <library_file_name>.aoclib [-L<library directory>] <kernel file name>.cl

where the -l <library_file_name>.aoclib command option specifies thelibrary file name, and the -L <library directory> command option specifiesthe directory containing the library files.

You may include multiple instances of -l <library file name> and -L<library directory> in the offline compiler command.

For example, if you create a library that includes the functions my_div_fd(),my_sqrtfd(), and myrsqrtfd(), the OpenCL kernel code might resemble thefollowing:

#include “lib_header.h”

kernel void test_lib ( global double * restrict in, global double * restrict out, int N) { int i = get_global_id(0); for (int k =0; k < N; k++) { double x = in[i*N + k]; out[i*N + k] = my_divfd (my_rsqrtfd(x), my_sqrtfd(my_rsqrtfd (x))); }}

Note: Library-related lines are highlighted in bold.



The corresponding lib_header.h file might resemble the following:

double my_sqrtfd (double x);double my_rsqrtfd(double x);double my_divfd(double a, double b);

2.1.7 Using an OpenCL Library that Works with Simple Functions(Example 1)

Intel provides an OpenCL library design example of a simple kernel that uses a librarycontaining RTL implementations of three double-precision functions: sqrt, rsqrt,and divide.

The example1.tgz tar ball includes a library, a kernel, and a host system. Theexample1.cl kernel source file includes two kernels. The kernel test_lib useslibrary functions; the kernel test_builtin uses built-in functions. The host runsboth kernels and then compares their outputs and runtimes. Intel recommends thatyou use the same strategy to verify your own library functions.

To compile this design example, perform the following tasks:

1. Obtain example1.tgz from the OpenCL Design Examples page on the Alterawebsite and store it in a directory that you own.

2. At the Intel FPGA SDK for OpenCL command prompt, navigate to the location ofthe design example.

3. Type perl make_lib.pl to create the lib1/double_lib.aoclib library file.

4. Type aoc -l double_lib.aoclib -L lib1 -I lib1 example1.cl tocompile the OpenCL kernel while including the double_lib.aoclib library file.

5. Type cd host to navigate to the host directory.

6. Type gmake -f Makefile to build the host program.

7. Type host/example1 to run the host program.The SDK generates the following messages after the host program runssuccessfully:

Loading example1.aocx ...Create buffersGenerate random data for conversion...Enqueueing both library and builtin in kernels 4 times with global size 65536Kernel computation using library function took 5.35333 secondsKernel computation using built-in function took 5.39949 secondsReading results to buffers...Checking results...Library function throughput is within 5% of builtin throughput.PASSED

Related Links

OpenCL Design Examples page



https://www.altera.com/support/support-resources/design-examples/design-software/opencl.html

2.1.8 Using an OpenCL Library that Works with External Memory(Example 2)

Intel provides an OpenCL library design example of a simple kernel that uses a librarycontaining two RTL modules that communicate with global memory.

The example1.tgz tar ball includes a library, a kernel, and a host system. In thisexample, the RTL code that communicates with global memory is Custom Platform- orReference Platform-dependent. Ensure that the compilation targets the board thatcorresponds to the Stratix V Network Reference Platform.

Intel generated the RTL modules copyElement() and sumOfElements() using theIntel FPGA SDK for OpenCL Offline Compiler, which explains the extra inputs in thecode.

The example2.cl kernel source file includes two kernels. The kernel test6 is anNDRange kernel that calls the copyElement() RTL function, which copies data fromB[] to A[] and then stores global_id+100 in C[]. The kernel test11 is a singlework-item kernel that uses an RTL function . The sumOfElements() RTL functiondetermines the sum of the elements of A[] in range [i, N] and then adds the restto C[i].

Note: First invocations of sumOfElements(i=0) will take more time to execute than laterinvocations.

To compile this design example, perform the following tasks:

1. Obtain example2.tgz from the OpenCL Design Examples page on the Alterawebsite and store it in a directory that you own.

2. At the Intel FPGA SDK for OpenCL command prompt, navigate to the location ofthe design example.

3. Type perl make_lib.pl to create the lib1/mem_users.aoclib library file.

4. Type aoc -l lib/mem_users.aoclib -I lib example2.cl to compile theOpenCL kernel while including the mem_users.aoclib library file.

5. Type cd host to navigate to the host directory.

6. Type gmake -f Makefile to build the host program.

7. Type host/example2 to run the host program.The SDK generates the following messages after the host program runssuccessfully:

Loading example2.aocx ...Running test6Launching the kernel test6 with globalsize=128 localSize=16Loading example2.aocx ...Running test11Launching the kernel test11 with globalsize=1 localSize=1PASSED

Related Links

• OpenCL Design Examples page




https://www.altera.com/support/support-resources/design-examples/design-software/opencl.html


• Intel FPGA SDK for OpenCL Stratix V Network Reference Platform Porting Guide

2.1.9 OpenCL Library Command-Line Options

Both the Intel FPGA SDK for OpenCL Offline Compiler's set of commands and the SDKutility include options you can invoke to perform OpenCL library-related tasks.

Table 10. Library-Related Intel FPGA SDK for OpenCL Offline Compiler CommandOptions

Command Option Description

-shared In conjunction with the -c command option, compiles an OpenCLsource file into an object file (.aoco) that you can then include intoa library.aoc -c -shared <OpenCL source file name>.cl -o<OpenCL object file name>.aoco

-I <library_directory> Adds <library directory> to the header file search path.aocl -I <library_header_file_directory> -l<library_file_name>.aoclib <kernel_file_name>.cl

-L <library directory> Adds <library directory> to the OpenCL library search path.Space after "-L" is optional.aoc -l <library_file_name>.aoclib [-L <librarydirectory>] <kernel file name>.cl

-l <library_file_name>.aoclib Specifies the OpenCL library file(<library_file_name>.aoclib).

Space after -l is optional.

aoc -l <library_file_name>.aoclib [-L <librarydirectory>] <kernel file name>.cl

--library-debug Generates debug output that relates to libraries. Part of theadditional output appears in stdout, the other part appears in the<kernel_file_name>/<kernel_file_name>.log file.

aoc -l <library_file_name>.aoclib --library-debug<kernel_file_name>.cl

Table 11. Intel FPGA SDK for OpenCL Library Utility (aocl library) Command Options


hdl-comp-pkg <XML_specification_file>.xml

Packages a single HDL component into a .aoco file that you theninclude into a library. Invoking this command option is similar toinvoking aoc -c <XML_specification_file>.xml. However,the processing time is faster because the aocl utility will notperform any environment checks.aocl library hdl-comp-pkg <XML_specification_file>.xml -o <output_file>.aoco

-c <XML_specification_ file>.xml Same function as hdl-comp-pkg <XML_specification_file>.xml.

aocl library -c <XML_specification_ file>.xml

create Creates a library file from the .aoco files that you created byinvoking the hdl-comp-pkg utility option or the aoc -sharedcommand, and any other .aoclib libraries.

continued...





aocl library create [-name <library_name>] [-vendor <library_vendor>] [-version<library_version>] [-o <output_file>.aoclib][.aoco...] [.aoclib...]

where -name, -vendor, and -version are optional informationstrings you can specify and add to the library.

list <library_name> Lists all the RTL components in the library. Currently, this option isnot available for use to list OpenCL functions.aocl library list <library_name>

help Prints the list of Intel FPGA SDK for OpenCL library utility optionsand their descriptions on screen.aocl library help

2.2 Kernel Attributes for Configuring Local Memory System

The Intel FPGA SDK for OpenCL includes kernel attributes that you can include in akernel to customize the geometry of the local memory system.

Attention: Only apply these local memory kernel attributes to local variables.

Table 12. OpenCL Kernel Attributes for Configuring Local Memory

Kernel Attribute Description

register Specifies that the local variable must be implemented in a register.

memory Specifies that the local variable must be implemented in a memorysystem. Including the memory kernel attribute is equivalent todeclaring the local variable with the __local qualifier.

numbanks(N)

N is an integer value.Specifies that the memory system implementing the local variablemust have N banks, where N is a power-of-2 integer value greaterthan zero.

bankwidth(N)

N is an integer value.Specifies that the memory system implementing the local variablemust have banks that are N bytes wide, where N is a power-of-2integer value greater than zero.

singlepump Specifies that the memory system implementing the local variablemust be single pumped.

doublepump Specifies that the memory system implementing the local variablemust be double pumped.

numreadports(N)

N is an integer value.Specifies that the memory system implementing the local variablemust have N read ports, where N is an integer value greater thanzero.

numwriteports(N)

N is an integer value.Specifies that the memory system implementing the local variablemust have N read ports, where N is an integer value greater thanzero.



Table 13. Code Examples for Local Memory Kernel Attributes

Example Use Case Syntax

Implements a local variable in a registerint __attribute__((register)) a[12];

Implements a local memory system with eight banks, eachwith a width of 8 bytes int __attribute__((memory,

numbanks(8), bankwidth(8)) b[16];

Implements a double-pumped local memory system withone 128-byte wide bank, one write port, and four read ports int __attribute__((memory,

numbanks(1), bankwidth(128), doublepump, numwriteports(1), numreadports(4)) c[32];

Related Links

• Improve Kernel Performance by Banking the Local Memory

• Optimize Accesses to Local Memory by Controlling the Memory Replication Factor

2.2.1 Restrictions on the Usage of Local Variable-Specific KernelAttributes

The Intel FPGA SDK for OpenCL Offline Compiler will error out or issue warnings if itdetects unsupported usages of the local variable-specific kernel attributes or incorrectmemory configurations.

Unsupported usages of local variable-specific kernel attributes that cause compilationerrors:

• You use the kernel attributes in declarations other than local variable declarations(for example, declarations for function parameters, global variable declarations, orfunction declarations).

• You use the register attribute in conjunction with any of the other localvariable-specific kernel attributes.

• You specify the numbanks kernel attribute but not the bankwidth kernel attributein the same local variable declaration, and vice versa.

• You include both the singlepump and doublepump kernel attributes in the samelocal variable declaration.





• You specify the numreadports and numwriteports kernel attributes withoutalso including the singlepump or doublepump kernel attribute in the same localvariable declaration.

• You specify the numreadports kernel attribute but not the numwriteportskernel attribute in the same local variable declaration, and vice versa.

• You specify any of the following kernel attributes without also specifying thenumbanks and bankwidth kernel attributes in the same local variabledeclaration:

— numreadports

— numwriteports

— singlepump

— doublepump

Incorrect memory configurations that cause the offline compiler to issue warningsduring compilation:

• The memory configuration that is defined by the local variable-specific kernelattributes exceeds the available storage size (for example, specifying eight banksof local memory for an integer variable).

Incorrect memory configurations that cause compilation errors:

• The bank width is smaller than the data storage size (for example, bank width is 2bytes for an array of 4-byte integers).

• You specify memory configurations for the local variables. However, because ofcompiler restrictions or coding style, the offline compiler implements the variablesin the same memory instead of splitting the memory.

• You specify the register kernel attribute for a local variable. However, becauseof compiler restrictions or coding style, the offline compiler cannot implement thevariable in a register.

2.3 Kernel Attributes for Reducing the Overhead on HardwareUsage

The Intel FPGA SDK for OpenCL includes kernel attributes that you can include in asingle work-item kernel to reduce logic utilization and improve kernelperformance.These kernel attributes enables the Intel FPGA SDK for OpenCL OfflineCompiler to omit the generation of unnecessary hardware to increase efficiency.

2.3.1 Hardware for Kernel Interface

The Intel FPGA SDK for OpenCL Offline Compiler generates hardware around thekernel pipeline. For some OpenCL applications, these interface hardware componentsare not necessary.

Hardware around the kernel pipeline is necessary for functions such as the following:

• Dispatching IDs for work-items and work-groups

• Communicating with the host regarding kernel arguments and work-group sizes



Figure 15 on page 136 illustrates the hardware that the offline compiler generateswhen it compiles the following kernel:

__kernel void my_kernel(global int* arg){ … int sum = 0; for(unsigned i = 0; i < n; i++) { if(sum < m) sum += val; } *arg = sum; …}

Figure 15. Intel FPGA SDK for OpenCL Offline Compiler-Generated Interface Hardwarearound a Kernel Pipeline

Host Link Hardware

Kernel ID Generators

Kernel

2.3.1.1 Omit Hardware that Generates and Dispatches Kernel IDs

The max_global_work_dim(0) kernel attribute instructs the Intel FPGA SDK forOpenCL Offline Compiler to omit logic that generates and dispatches global, local, andgroup IDs into the compiled kernel.

Semantically, the max_global_work_dim(0) kernel attribute specifies that theglobal work dimension of the kernel is zero. Setting this kernel attribute means thatthe kernel does not use any global, local, or group IDs. The presence of this attributein the kernel code serves as a guarantee to the offline compiler that the kernel is asingle work-item kernel.

When compiling the following kernel, the offline compiler will generate interfacehardware as illustrated in Figure 16 on page 137.

channel int chan_in;channel int chan_out;

__attribute__((max_global_work_dim(0)))__kernel void plusK (int N, int k) { for (int i = 0; i < N; ++i) { int data_in = read_channel_altera(chan_in); write_channel_altera(chan_out, data_in + k); }}



Figure 16. Intel FPGA SDK for OpenCL Offline Compiler-Generated Interface Hardwarefor a Kernel with the max_global_work_dim(0) Attribute

Host Link Hardware


Kernel

If your current kernel implementation has multiple work-items but does not useglobal, local, or group IDs, you can use the max_global_work_dim(0) kernelattribute if you modify the kernel code accordingly:

1. Wrap the kernel body in a for loop that iterates as many times as the number ofwork-items.

2. Launch the modified kernel with only one work-item.

2.3.1.2 Omit Communication Hardware between the Host and the Kernel

The autorun kernel attribute instructs the Intel FPGA SDK for OpenCL OfflineCompiler to omit logic that is used for communication between the host and thekernel. A kernel that uses the autorun attribute starts executing automatically beforeany kernel that the host launches explicitly. In addition, this kernel restartsautomatically as soon as it finishes its execution.

The autorun kernel attribute notifies the offline compiler that the kernel runs on itsown and will not be enqueued by any host.

To leverage the autorun attribute, a kernel must meet all of the following criteria:

1. Does not use I/O channels

Note: Kernel-to-kernel channels are supported.

2. Does not have any arguments

3. Has either the max_global_work_dim(0) attribute or thereqd_work_group_size(X,Y,Z) attribute

Note: The parameters of the reqd_work_group_size(X,Y,Z) attribute must bedivisors of 232.

As mentioned above, kernels with the autorun attribute cannot have any argumentsand start executing without the host launching them explicitly. As a result, the offlinecompiler does not need to generate the logic for communication between the host andthe kernel. Omitting this logic reduces logic utilization and allows the offline compilerto apply additional performance optimizations.



A typical use case for the autorun attribute is a kernel that reads data from one ormore kernel-to-kernel channels, processes the data, and then writes the results to oneor more channels. When compiling the kernel, the offline compiler will generatehardware as illustrated in Figure 17 on page 138.

channel int chan_in;channel int chan_out;

__attribute__((max_global_work_dim(0)))__attribute__((autorun))__kernel void plusOne () { while(1) { int data_in = read_channel_altera(chan_in); write_channel_altera(chan_out, data_in + 1); }}

Figure 17. Single Work-Item Kernel with No Interface Hardware

Host Link Hardware


Kernel

2.4 Kernel Replication Using the num_compute_units(X,Y,Z)Attribute

You can replicate your single work-item OpenCL kernel by including thenum_compute_units(X,Y,Z) kernel attribute.

As mentioned in Specifying Number of Compute Units, including thenum_compute_units(N) kernel attribute in your kernel instructs the Intel FPGA SDKfor OpenCL Offline Compiler to generate multiple compute units to process data. Sincethe offline compiler processes a single work-item kernel in one compute unit, thenum_compute_unit(N) attribute instructs the offline compiler to generate N identicalcopies of the kernel in hardware.

Related Links

Specifying Number of Compute Units on page 22To increase the data-processing efficiency of an OpenCL kernel, you can instructthe Intel FPGA SDK for OpenCL Offline Compiler to generate multiple kernelcompute units. Each compute unit is capable of executing multiple work-groupssimultaneously.



2.4.1 Customization of Replicated Kernels Using the get_compute_id()Function

To create compute units that are slightly different from one another but share a lot ofcommon code, call the get_compute_id() intrinsic function in a kernel that alsouses the num_compute_units (X,Y,Z) attribute.

Attention: You can only use the get_compute_id() function in a kernel that also uses theautorun and max_global_work_dim(0) kernel attributes.

Retrieving compute IDs is a convenient alternative to replicating your kernel in sourcecode and then adding specialized code to each kernel copy. When a kernel uses thenum_compute_units(X,Y,Z) attribute and calls the get_compute_id() function,the Intel FPGA SDK for OpenCL Offline Compiler assigns a unique compute ID to eachcompute unit. The get_compute_id() function then retrieves these unique computeIDs. You can use the compute ID to specify how the associated compute unit shouldbehave differently from the other compute units that are derived from the same kernelsource code. For example, you can use the return value of get_compute_id() toindex into an array of channels to specify which channel each compute unit shouldread from or write to.

The num_compute_units attribute accepts up to three arguments (that is,num_compute_units(X,Y,Z)). In conjunction with the get_compute_id()function, this attribute allows you to create one-dimensional, two-dimensional, andthree-dimensional logical arrays of compute units. An example use case of a 1D arrayof compute units is a linear pipeline of kernels (also called a daisy chain of kernels).An example use case of a 2D array of compute units is a systolic array of kernels.



Figure 18. Schematic Diagram of a 4x4 Array of Compute UnitsThe following example code specifies num_compute_units(4,4) in a single work-item kernel results in a 4x4 array that consists of 4 x 4 = 16 compute units.

__attribute__((max_global_work_dim(0)))__attribute__((autorun))__attribute__((num_compute_units(4,4)))__kernel void PE() {

row = get_compute_id(0); col = get_compute_id(1);

…}

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

0

3

2

1

3210col

row

For a 3D array of compute units, you can retrieve the X, Y, and Z coordinates of acompute unit in the logical compute unit array using get_compute_id(0),get_compute_id(1), and get_compute_id(2), respectively. In this case, the APIis very similar to the API of the work-item's intrinsic functions (that is,get_global_id(), get_local_id(), and get_group_id()).

Global IDs, local IDs, and group IDs can vary at runtime based on how the hostinvokes the kernel. However, compute IDs are known at compilation time, allowing theoffline compiler to generate optimized hardware for each compute unit.

2.4.2 Using Channels with Kernel Copies

To implement channels within compute units (that is, replicated kernel copies), createan array of channels and then index into that array using the return value ofget_compute_id().

The example code below implements channels within multiple compute units.

#define N 4channel int chain_channels[N+1];



__attribute__((max_global_work_dim(0)))__kernel void reader(global int *data_in, int size) { for (i = 0; i < size; ++i) { write_channel_altera(chain_channels[0], data_in[i]); }}

__attribute__((max_global_work_dim(0)))__attribute__((autorun)) __attribute__((num_compute_units(N))) __kernel void plusOne() { int compute_id = get_compute_id(0); int input = read_channel_altera(chain_channels[compute_id]); write_channel_altera(chain_channels[compute_id+1], input + 1);}

__attribute__((max_global_work_dim(0)))__kernel void writer(global int *data_out, int size) { for (i = 0; i < size; ++i) { data_out[i] = read_channel_altera(chain_channels[N]);; }}

Figure 19. Example Topology of Kernel Copies that Implement ChannelsThis figure illustrates the topology of the group of kernels that the OpenCL applicationcode above generates.

reader writer+1 +1 +1 +1

DDR4 DDR4kernel copies created using num_compute_units(N)

Note: The implementation of kernel copies is functionally equivalent to defining fourseparate kernels in your source code and then hard-coding unique indexes for theaccesses to chain_channels[N].

2.5 Document Revision History

Table 14. Document Revision History of the Advanced Features Chapter of the IntelFPGA SDK for OpenCL Programming Guide


October 2016 2016.10.31 • Rebranded Altera SDK for OpenCL to Intel FPGA SDK for OpenCL.• Rebranded Altera Offline Compiler to Intel FPGA SDK for OpenCL Offline

Compiler.

May 2016 2016.05.02 Initial release.



A Support Statuses of OpenCL FeaturesTheIntel FPGA SDK for OpenCL host runtime conforms with the OpenCL platform layerand application programming interface (API), with clarifications and exceptions.

Support Statuses of OpenCL 1.0 Features on page 142



Intel FPGA SDK for OpenCL Allocation Limits on page 150

Document Revision History on page 151

A.1 Support Statuses of OpenCL 1.0 Features

The following sections outline the support statuses of the OpenCL features describedin the OpenCL Specification version 1.0.

A.1.1 OpenCL1.0 C Programming Language Implementation

OpenCL is based on C99 with some limitations. Section 6 of the OpenCL Specificationversion 1.0 describes the OpenCL C programming language. The Intel FPGA SDK forOpenCL conforms with the OpenCL C programming language with clarifications andexceptions. The table below summarizes the support statuses of the features in theOpenCL programming language implementation.

Attention: The support status "●" means that the feature is supported, and there might be aclarification for the supported feature in the Notes column. The support status "○"means that the feature is supported with exceptions identified in the Notes column. Afeature that is not supported by the SDK is identified with an "X". OpenCLprogramming language implementations that are supported with no additionalclarifications are not shown.

Section

Feature SupportStatus

Notes

6.1.1 Built-in Scalar Data Types

double precision float ○ Preliminary support for all double precision float built-in scalardata type. This feature might not conform with the OpenCLSpecification version 1.0.Currently, the following double precision floating-point functionsconform with the OpenCL Specification version 1.0:add / subtract / multiply / divide / ceil / floor / rint / trunc /fabs / fmax / fmin / sqrt / rsqrt / exp / exp2 / exp10 / log /log2 / log10 / sin / cos / asin / acos / sinh / cosh / tanh /asinh / acosh / atanh / pow / pown / powr / tanh / atan /atan2 / ldexp / log1p / sincos

continued...

A Support Statuses of OpenCL Features






Section


Notes

half precision float ○ Support for scalar addition, subtraction and multiplication.Support for conversions to and from single-precision floatingpoint. This feature might not conform with the OpenCLSpecification version 1.0.This feature is supported in the Emulator.

6.1.2 Built-in Vector Data Types ○ Preliminary support for vectors with three elements. Three-element vector support is a supplement to the OpenCLSpecification version 1.0.

6.1.3 Built-in Data Types X

6.1.4 Reserved Data Types X

6.1.5 Alignment of Types ● All scalar and vector types are aligned as required (vectors withthree elements are aligned as if they had four elements).

6.2.1 Implicit Conversions ● Refer to Section 6.2.6: Usual Arithmetic Conversions in theOpenCL Specification version 1.2 for an important clarificationof implicit conversions between scalar and vector types.

6.2.2 Explicit Casts ● The SDK allows scalar data casts to a vector with a differentelement type.

6.5 Address Space Qualifiers ○ Function scope__constant variables are not supported.

6.6 Image Access Qualifiers X

6.7 Function Qualifiers

6.7.2 Optional Attribute Qualifiers ● Refer to the Intel FPGA SDK for OpenCL Best Practices Guidefor tips on using reqd_work_group_size to improve kernelperformance.The SDK parses but ignores the vec_type_hint andwork_group_size_hint attribute qualifiers.

6.9 Preprocessor Directives and Macros

#pragma directive: #pragmaunroll

● The Intel FPGA SDK for OpenCL Offline Compiler supports only#pragma unroll. You may assign an integer argument to theunroll directive to control the extent of loop unrolling.For example, #pragma unroll 4 unrolls four iterations of aloop.By default, an unroll directive with no unroll factor causes theoffline compiler to attempt to unroll the loop fully.Refer to the Intel FPGA SDK for OpenCL Best Practices Guidefor tips on using #pragma unroll to improve kernelperformance.

__ENDIAN_LITTLE__ defined tobe value 1

● The target FPGA is little-endian.

__IMAGE_SUPPORT__ X __IMAGE_SUPPORT__ is undefined; the SDK does not supportimages.

6.10 Attribute Qualifiers—The offline compiler parses attribute qualifiers as follows:

6.10.2 Specifying Attributes of Functions—Structure-type kernelarguments

X Convert structure arguments to a pointer to a structure inglobal memory.

6.10.3 Specifying Attributes of Variables—endian

X

6.10.4 Specifying Attributes of Blocksand Control-Flow-Statements

X

continued...



Section


Notes

6.10.5 Extending Attribute Qualifiers ● The offline compiler can parse attributes on various syntacticstructures. It reserves some attribute names for its owninternal use.Refer to the Intel FPGA SDK for OpenCL Best Practices Guidefor tips on how to optimize kernel performance using thesekernel attributes.

6.11.2 Math Functions

built-in math functions ○ Preliminary support for built-in math functions for doubleprecision float. These functions might not conform with theOpenCL Specification version 1.0.

built-in half_ and native_math functions

○ Preliminary support for built-in half_ and native_ mathfunctions for double precision float. These functions might notconform with the OpenCL Specification version 1.0.

6.11.5 Geometric Functions ○ Preliminary support for built-in geometric functions for doubleprecision float. These functions might not conform with theOpenCL Specification version 1.0.Refer to Argument Types for Built-in Geometric Functions for alist of built-in geometric functions supported by the SDK.

6.11.8 Image Read and Write Functions X

6.11.9 Synchronization Functions—thebarrier synchronization function

○ Clarifications and exceptions:If a kernel specifies the reqd_work_group_size ormax_work_group_size attribute, barrier supports thecorresponding number of work-items.If neither attribute is specified, a barrier is instantiated with adefault limit of 256 work-items.The work-item limit is the maximum supported work-group sizefor the kernel; this limit is enforced by the runtime.

6.11.11

Async Copies from Global toLocal Memory, Local to GlobalMemory, and Prefetch

○ The implementation is naive:Work-item (0,0,0) performs the copy and thewait_group_events is implemented as a barrier.If a kernel specifies the reqd_work_group_size ormax_work_group_size attribute, wait_group_eventssupports the corresponding number of work-items.If neither attribute is specified, wait_group_events isinstantiated with a default limit of 256 work-items.

Related Links

• Intel FPGA SDK for OpenCL Best Practices Guide

• Argument Types for Built-in Geometric Functions on page 145The Intel FPGA SDK for OpenCL supports scalar and vector argument built-ingeometric functions with certain limitations.

A.1.2 OpenCL C Programming Language Restrictions

The Intel FPGA SDK for OpenCL conforms with the OpenCL Specification restrictionson specific programming language features, as described in section 6.8 of the OpenCLSpecification version 1.0.

Warning: The Intel FPGA SDK for OpenCL Offline Compiler does not enforce restrictions oncertain disallowed programming language features. Ensure that your kernel code doesnot contain features that the OpenCL Specification version 1.0 does not support.





Notes

pointer assignments between addressspaces

● Arguments to __kernel functions declared in a program that arepointers must be declared with the __global, __constant, or__local qualifier.The offline compiler enforces the OpenCL restriction againstpointer assignments between address spaces.

pointers to functions X The offline compiler does not enforce this restriction.

structure-type kernel arguments X Convert structure arguments to a pointer to a structure in globalmemory.

images X The SDK does not support images.

bit fields X The offline compiler does not enforce this restriction.

variable length arrays and structures X

variable macros and functions X

C99 headers X

extern, static, auto, and registerstorage-class specifiers

X The offline compiler does not enforce this restriction.

predefined identifiers ● Use the -D option of the aoc command to provide preprocessorsymbol definitions in your kernel code.

recursion X The offline compiler does not enforce this restriction.

irreducible control flow X The offline compiler does not enforce this restriction.

writes to memory of built-in types lessthan 32 bits in size

○ Store operations less than 32 bits in size might result in lowermemory performance.

declaration of arguments to __kernelfunctions of type event_t

X The offline compiler does not enforce this restriction.

elements of a struct or a unionbelonging to different address spaces

X The offline compiler does not enforce this restriction.Warning: Assigning elements of a struct or a union to

different address spaces might cause a fatal error.

A.1.3 Argument Types for Built-in Geometric Functions

The Intel FPGA SDK for OpenCL supports scalar and vector argument built-ingeometric functions with certain limitations.

Function Argument Type

float double

cross ● ●

dot ●

distance ●

length ●

normalize ●

fast_distance —

fast_length —

fast_normalize —



A.1.4 Numerical Compliance Implementation

Section 7 of the OpenCL Specification version 1.0 describes features of the C99 andIEEE 754 standards that OpenCL-compliant devices must support. The Intel FPGA SDKfor OpenCL operates on 32-bit and 64-bit floating-point values in IEEE Standard754-2008 format, but not all floating-point operators have been implemented.

The table below summarizes the implementation statuses of the floating-pointoperators:

Section Feature SupportStatus

Notes

7.1 Rounding Modes ○ Conversion between integer and single and half precisionfloating-point types support all rounding modes.Conversions between integer and double precision floating-point types support all rounding modes on a preliminarybasis. This feature might not conform with the OpenCLSpecification version 1.0.

7.2 INF, NaN and DenormalizedNumbers

○ Infinity (INF) and Not a Number (NaN) results for singleprecision operations are generated in a manner thatconforms with the OpenCL Specification version 1.0. Mostoperations that handle denormalized numbers are flushedprior to and after a floating-point operation.Preliminary support for double precision floating-pointoperation. This feature might not conform with the OpenCLSpecification version 1.0.

7.3 Floating-Point Exceptions X

7.4 Relative Error as ULPs ○ Single precision floating-point operations conform with thenumerical accuracy requirements for an embedded profile ofthe OpenCL Specification version 1.0.Preliminary support for double precision floating-pointoperation. This feature might not conform with the OpenCLSpecification version 1.0.

7.5 Edge Case Behavior ●

A.1.5 Image Addressing and Filtering Implementation

The Intel FPGA SDK for OpenCL does not support image addressing and filtering. TheSDK does not support images.

A.1.6 Atomic Functions

Section 9 of the OpenCL Specification version 1.0 describes a list of optional featuresthat some OpenCL implementations might support. The Intel FPGA SDK for OpenCLsupports atomic functions conditionally.

• Section 9.5: Atomic Functions for 32-bit Integers—The SDK supports all 32-bitglobal and local memory atomic functions. The SDK also supports 32-bit atomicfunctions described in Section 6.11.11 of the OpenCL Specification version 1.1 andSection 6.12.11 of the OpenCL Specification version 1.2.

— The SDK does not support 64-bit atomic functions described in Section 9.7 ofthe OpenCL Specification version 1.0.



Attention: The use of atomic functions might lower the performance of your design. Theoperating frequency of the hardware might decrease further if you implement morethan one type of atomic functions (for example, atomic_add and atomic_sub) inthe kernel.

A.1.7 Embedded Profile Implementation

Section 10 of the OpenCL Specification version 1.0 describes the OpenCL embeddedprofile. The Intel FPGA SDK for OpenCL conforms with the OpenCL embedded profilewith clarifications and exceptions.

The table below summarizes the clarifications and exceptions to the OpenCLembedded profile:

Clause Feature SupportStatus

Notes

1 64-bit integers ●

2 3D images X The SDK does not support images.

3 Create 2D and 3D images withimage_channel_data_typevalues

X The SDK does not support images.

4 Samplers X

5 Rounding modes ● The default rounding mode forCL_DEVICE_SINGLE_FP_CONFIG isCL_FP_ROUND_TO_NEAREST.

6 Restrictions listed for singleprecision basic floating-pointoperations

X

7 half type X This clause of the OpenCL Specification version 1.0 does notapply to the SDK.

8 Error bounds listed forconversions fromCL_UNORM_INT8,CL_SNORM_INT8,CL_UNORM_INT16 andCL_SNORM_INT16 to float

● Refer to the table below for a list of allocation limits.



A.2.1 OpenCL 1.2 Runtime Implementation

The Intel FPGA SDK for OpenCL supports the implementation of sub-buffer objectsand image objects. For more information on sub-buffer objects and image objects,refer to sections 5.2 and 5.3 of the OpenCL Specification version 1.2, respectively.

The SDK also supports the implementation of the following APIs:

• clSetMemObjectDestructorCallback

• clGetKernelArgInfo

• clSetEventCallback



For more information on these APIs, refer to sections 5.4.1, 5.7.3, and 5.9 of theOpenCL Specification 1.2, respectively.

Related Links


A.2.2 OpenCL 1.2 C Programming Language Implementation

The Intel FPGA SDK for OpenCL supports a number of OpenCL C programminglanguage features that are specified section 6 of the OpenCL Specification version 1.2.The SDK conforms with the OpenCL C programming language with clarifications andexceptions.

Attention: The support status "●" means that the feature is supported, and there might be aclarification for the supported feature in the Notes column. The support status "○"means that the feature is supported with exceptions identified in the Notes column.

Table 15. Support Statuses of OpenCL 1.2 C Programming Language Features

Section Feature SupportStatus

Notes

6.1.3 Other Built-in Data Types ● Preliminary support. This feature might not conform with theOpenCL Specification version 1.0.

6.12.12 Miscellaneous VectorFunctions

● The SDK supports implementations of the following additionalbuilt-in vector functions:• vec_step

• shuffle

• shuffle2

6.12.13 printf ○ Preliminary support. This feature might not conform with theOpenCL Specification version 1.0. See below for details.

The printf function in OpenCL has syntax and features similar to the printf function in C99, with a few exceptions. Fordetails, refer to the OpenCL Specification version 1.2.To use a printf function, there are no requirements for special compilation steps, buffers, or flags. You can compilekernels that include printf instructions with the usual aoc command.During kernel execution, printf data is stored in a global printf buffer that the Intel FPGA SDK for OpenCL OfflineCompiler allocates automatically. The size of this buffer is 64 kB; the total size of data arguments to a printf call shouldnot exceed this size. When kernel execution completes, the contents of the printf buffer are printed to standard output.Buffer overflows are handled seamlessly; printf instructions can be executed an unlimited number of times. However, ifthe printf buffer overflows, kernel pipeline execution stalls until the host reads the buffer and prints the buffer contents.Because printf functions store their data into a global memory buffer, the performance of your kernel will drop if itincludes such functions.There are no usage limitations on printf functions. You can use printf instructions inside if-then-else statements,loops, etc. A kernel can contain multiple printf instructions executed by multiple work-items.Format string arguments and literal string arguments of printf calls are transferred to the host system from the FPGAusing a special memory region. This memory region can overflow if the total size of the printf string arguments is large(3000 characters or less is usually safe in a typical OpenCL application). If there is an overflow, the error message cannotparse auto-discovery string at byte offset 4096 is printed during host program execution.Output from printf is never intermixed, even though work-items may execute printf functions concurrently. However,the order of concurrent printf execution is not guaranteed. In other words, printf outputs might not appear in programorder if the printf instructions are in concurrent datapaths.

Related Links








A.3.1 OpenCL 2.0 Headers

The Intel FPGA SDK for OpenCL provides both the OpenCL 1.0 and OpenCL 2.0headers by the Khronos Group.

Attention: The SDK currently does not support all OpenCL 2.0 APIs. If you use the OpenCL 2.0headers and make a call to an unsupported API, the call will return with an error codeto indicate that the API is not fully supported.

A.3.2 OpenCL 2.0 Runtime Implementation

The Intel FPGA SDK for OpenCL offers preliminary support for shared virtual memoryimplementation, as described in section 5.6 of the OpenCL Specification version 2.0.For more information on shared virtual memory, refer to section 5.6 of the OpenCLSpecification version 2.0.

Important: Refer to your board's specifications to verify that your board supports shared virtualmemory.

Related Links


A.3.3 OpenCL 2.0 C Programming Language Restrictions for Pipes

The Intel FPGA SDK for OpenCL offers preliminary support of OpenCL pipes.Thefollowing table lists the support statuses of pipe-specific OpenCL C programminglanguage implementations, as described in the OpenCL Specification version 2.0

Attention: The support status "●" means that the feature is supported. There might be aclarification for the supported feature in the Notes column. A feature that is notsupported by the SDK is identified with an "X".

Table 16. Support Statuses of Built-in Pipe Read and Write FunctionsDetails of the built-in pipe read and write functions are available in section 6.13.16.2 of the OpenCLSpecification version 2.0.

Function Support Status

int read_pipe (pipe gentype p, gentype *ptr) ●

int write_pipe (pipe gentype p, const gentype *ptr) ●

int read_pipe (pipe gentype p, reserve_id_t reserve_id, uint index, gentype*ptr)

X

int write_pipe (pipe gentype p, reserve_id_t reserve_id, uint index, constgentype *ptr)

X

reserve_id_t reserve_read_pipe (pipe gentype p, uint num_packets) X

continued...





reserve_id_t reserve_write_pipe (pipe gentype p, uint num_packets)

void commit_read_pipe (pipe gentype p, reserve_id_t reserve_id)

void commit_write_pipe (pipe gentype p, reserve_id_t reserve_id)

X

bool is_valid_reserve_id (reserve_id_t reserve_id) X

Table 17. Support Statuses of Built-in Work-Group Pipe Read and Write FunctionsDetails of the built-in pipe read and write functions are available in section 6.13.16.3 of the OpenCLSpecification version 2.0.


reserve_id_t work_group_reserve_read_pipe (pipe gentype p, uint num_packets)

reserve_id_t work_group_reserve_write_pipe (pipe gentype p, uint num_packets)

X

void work_group_commit_read_pipe (pipe gentype p, reserve_id_t reserve_id)

void work_group_commit_write_pipe (pipe gentype p, reserve_id_t reserve_id)

X

Table 18. Support Statuses of Built-in Pipe Query FunctionsDetails of the built-in pipe query functions are available in section 6.13.16.4 of the OpenCL Specificationversion 2.0.


uint get_pipe_num_packets (pipe gentype p) X

uint get_pipe_max_packets (pipe gentype p) X

Related Links

OpenCL Specification version 2.0 (C Language)

A.4 Intel FPGA SDK for OpenCL Allocation Limits

Item Limit

Maximum number of contexts Limited only by host memory size

Minimum global memory allocation byruntime

The runtime allocates 64 kB of device memory when the context iscreated. This memory is reserved for program variables in global addressspace and for static variables inside functions. You may overwrite theamount of this memory, to as low as 0 bytes, by setting the environmentvariable CL_CONTEXT_PROGRAM_VARIABLES_TOTAL_SIZE_ALTERA to thedesired value in bytes.If the OpenCL kernel uses the printf function, the runtime allocates anadditional 64 kB of device memory.

Maximum number of queues 256Attention: Each context uses two queues for system purposes.

Maximum number of program objects percontext

20

Maximum number of even objects percontext

Limited only by host memory size

Maximum number of dependencies betweenevents within a context

1000

continued...



https://www.khronos.org/registry/cl/specs/opencl-2.0-openclc.pdf

Item Limit

Maximum number of event dependencies percommand

20

Maximum number of concurrently runningkernels

The total number of queues

Maximum number of enqueued kernels 1000

Maximum number of kernels per FPGA device Hardware: no static limitEmulator: 256

Maximum number of arguments per kernel 128

Maximum total size of kernel arguments 256 bytes per kernel

A.5 Document Revision History

Table 19. Document Revision History of the Intel FPGA SDK for OpenCL ProgrammingGuide Appendix A: Support Statuses of OpenCL Features

Date DocumentVersion

Changes

October 2016 2016.10.31 • Rebranded the Altera SDK for OpenCL to Intel FPGA SDK for OpenCL.• Rebranded the Altera Offline Compiler to Intel FPGA SDK for OpenCL

Offline Compiler.• Modified information in the Intel FPGA SDK for OpenCL Allocation Limits

section:— Updated information regarding minimum global memory allocation by

runtime.— Updated the maximum number of queues from 70 to 256.— Updated the maximum number of kernels per FPGA device from 64 to

no static limit when compiling to hardware and 256 when compiling toemulator.

• In OpenCL 1.0 C Programming Language Implementation, under theDescription column for half-precision float, added a note that this featureis supported in the Emulator. In addition, updated the support status ofhalf-precision float from X to ○.

• Under Support Statuses of OpenCL 2.0 Features, added the topic OpenCL2.0 Headers to explain that using the OpenCL 2.0 headers to callunsupported APIs will result in an error.

May 2016 2016.05.02 In OpenCL 1.2 Runtime Implementation, noted that AOCL supports theclSetEventCallback, clGetKernelArgInfo, andclSetMemObjectDestructorCallback APIs.

November 2015 2015.11.02 • Categorized feature support statuses and limitations based on OpenCLSpecification versions.

• Added the following functions to the list of OpenCL-conformant doubleprecision floating-point functions:sinh / cosh / tanh / asinh / acosh / atanh / pow / pown / powr / tanh /atan / atan2 / ldexp / log1p / sincos

• In OpenCL 1.2 Runtime Implementation, added sub-buffer object support.• In OpenCL 2.0 Runtime Implementation, added preliminary shared virtual

memory support.• In Altera SDK for OpenCL Allocation Limits, added a minimum global

memory allocation limit by the runtime.

May 2015 15.0.0 • Listed the double precision floating-point functions that the Altera SDK forOpenCL supports preliminarily.

• Added OpenCL C Programming Language Restrictions for Pipes.

continued...



Date DocumentVersion

Changes

December 2014 14.1.0 • In AOCL Allocation Limits, updated the maximum number of kernels perFPGA device from 32 to 64.

June 2014 14.0.0 • Updated the following AOCL allocation limits:— Maximum number of contexts— Maximum number of queues— Maximum number of even objects per context

December 2013 13.1.1 • Modified support status designations in Appendix: Support Statuses ofOpenCL Features.

• Removed information on OpenCL programming language restrictions fromthe section OpenCL Programming Language Implementation, andpresented the information in a new section titled OpenCL ProgrammingLanguage Restrictions.

November 2013 13.1.0 Maintenance release.

June 2013 13.0 SP1.0 • Renamed Optional Extensions to Atomic Functions, and updated itscontent.

• Removed Platform Layer and Runtime Implementation.

May 2013 13.0.1 Maintenance release.

May 2013 13.0.0 • Added updated information on allocation limits and OpenCL languagesupport.

November 2012 12.1.0 Initial release.



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