January 2018Revision Number: 3.2

Order No. 333016-006

Intel Ethernet Controller I210 DatasheetNetworking Division (ND)

Features: Small package: 9 x 9 mm PCIe v2.1 (2.5 GT/s) x1, with Switching Voltage Regulator (iSVR) Integrated Non-Volatile Memory (iNVM) Three single port SKUs: SerDes, Copper, Copper IT Value Part (Intel Ethernet Controller I211) Platform Power Efficiency

IEEE 802.3az Energy Efficient Ethernet (EEE) Proxy: ECMA-393 and Windows* logo for proxy offload

Advanced Features: 0 to 70 C commercial temperature or -40 to 85 C industrial temperature Audio-video bridging

IEEE 1588/802.1AS precision time synchronization IEEE 802.1Qav traffic shaper (with software extensions)

Jumbo frames Interrupt moderation, VLAN support, IP checksum offload PCIe OBFF (Optimized Buffer Flush/Fill) for improved system power management Four transmit and four receive queues RSS and MSI-X to lower CPU utilization in multi-core systems Advanced cable diagnostics, auto MDI-X ECC error correcting memory in packet buffers Four Software Definable Pins (SDPs)

Manageability: NC-SI for greater bandwidth pass through SMBus low-speed serial bus to pass network traffic Flexible firmware architecture with secure Flash update MCTP over SMBus/PCIe OS2BMC/CEM (optionally enabled via external Flash) PXE and iSCSI boot

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Revision HistoryEthernet Controller I210

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Revision History

Rev Date Notes

3.2 January 2018

Updated Table 2-1 (Pull-Up/Pull-Down Resistors).Added section 3.3.2.4 (iNVM Structure Version Information).Updated section 5.5.6 (Timing Guarantees).Updated section 6.8.2 (Port Identification LED Blinking; Word 0x04).Updated section 11.8.1 (Flash Parts).

3.1 June 2017Revised Section: 3.4.3 (iNVM Programming Flows).

3.0 March 2017

Revised Sections: 3.7.8.5.7 (Internal PHY Power-Down State). 11.6.2.7 (MDIO AC Specification). 12.4 (Oscillator Support). 12.11 (XOR Testing).

2.9 January 2016

Revised Table 2-1 (changed JTAG_CLK to show a pull down resistor instead of a pull up). Updated intra-document cross references. Revised the description of Section 7.8.3.3.3 (Synchronized Output Clock on SDP Pins). Revised Section 8.15.13 (TimeSync Auxiliary Control Register - TSAUXC (0xB640; RW), bit 4

and bit 7 description).

2.8 September 2015

Revised Section 6.8.7.2 (added image build information). Updated Table 11-11 (tDS and tDH descriptions). Updated Table 11-15 (cload value). Updated Figure 12.12 (changed pull-up value from 1.9 to 1.5). Updated Section 12.5.4 (Diff to CMR value). Added Section 12.5.6.5 (Maximum Trace Lengths Based on Trace Geometry). Fixed cross references in Section 12.6.

2.7 February 2015

Removed all references to IEEE Std 1149.6-2003, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks, IEEE, 2003.

Updated section 8.27.3.37 (Misc Test - Page 6, Register 26). Removed sections 8.27.3.38 through 8.27.3.43. Updated section 12-4 (Oscillator Support). Added section 12.5.5 (Designing the I210 as a 10/100 Mb/s Only Device). Updated section 12.5.6.4 (Differential Pair Trace Routing for 10/100/1000 Designs).

2.6 June 2014 Revised section 11.8.1 (replaced W25Q16DWSSIG with W25Q16DVSSIG).

2.5 February 2014

Replaced figure 2-2. Revised section 3.4 (iNVM). Revised section 3.4.2 (iNVM Structures). Revised section 3.7.8.5.5.1 (Internal PHY Back-to-Back SPD). Revised table 8-6 (Register Summary; PQMPRC[0 - 3]). Revised table 11-11 (Flash I/F Timing Parameters). Revised table 11-17 (Specification for External Clock Oscillator).

2.4 July 2013 Updated revision history.

Ethernet Controller I210 Revision History

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2.3 June 2013

Revised section 1.3.1 (Audio/Video Bridging Support). Revised section 6.7.1.2 (Common Firmware Parameters 1 - Offset 0x1; bit 15). Revised section 7.1.2.10 (Receive-Side Scaling (RSS). Revised section 7.8.3.1 (Capture Timestamp Mechanism). Revised section 8.21.18 (Flexible Host Filter Table Registers - FHFT (0x9000 + 4*n

[n=0...255]; RW); updated note. Revised section 8.27.3.23 (MAC Specific Control Register 1 - Page 2, Register 16; bits 9:8). Revised table 10-37 (Decision Filter Values).

Rev Date Notes

2.2 April 2013

Updated title page (Platform Power Efficiency description). Revised VPD Area Update Flow description (section 3.3.9.3.2). Revised iNVM description (section 3.4). Added line loopback information (section 3.7.6.6). Revised Acquiring Ownership Over a Shared Resource description (section 4.6.1). Revised Releasing Ownership Over a Shared Resource description (section 4.6.2). Revised Dr Disable Mode description (section 5.2.4.1). Revised Device Rev ID (section 6.2.19). Revised Common Firmware Parameters 1 - Offset 0x1 (section 6.7.1.2). Updated Compatibility (Word 0x03) bit 11 description (section 6.8.1). Updated Setup Options PCIe Function 0 (Word 0x30) bit 5 description (section 6.8.6.1). Added PXE VLAN Flash settings (Sections 6.8.6.5 through 6.8.6.9). Updated Software Semaphore - SWSM (0x5B50; R/W) Removed Firmware Status Register (0x8F0C) entry from Table 8-6. Revised note (changed . . . has both F and L flags off to on (section 10.5.7.1). Revised Specification for XTAL1 (In); table 11.16. Revised Third-Party Magnetics Manufacturers table (section 12.5.3). Added Power Delivery Solutions (section 12.7.1).

2.1 November 2012

Revised table 11.1 - Absolute Maximum Ratings Revised section 12.5.3 - Third-Party Magnetics Manufacturers. Revised table 12.16 - Absolute Maximum Case Temperature. Revised table 12.17 - Thermal Simulation Results for Various Environmental Conditions.

2.0 November 2012

The following sections were revised: 1.0 Introduction. 3.0 Interconnects. 6.0 Flash Map. 7.0 Inline Functions. 8.0 Programming Interface. 9.0 PCIe Programming Interface. 11.0 Electrical/Mechanical Specification. 12.0 Design Considerations. 14.0 Diagnostics Added new section 13.0 - Thermal Considerations.

1.9 October 2012 Initial Release (Intel Public).

IntroductionEthernet Controller I210

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1.0 Introduction

The Intel Ethernet Controller I210 (I210) is a single port, compact, low power component that supports GbE designs. The I210 offers a fully-integrated GbE Media Access Control (MAC), Physical Layer (PHY) port and a SGMII/SerDes port that can be connected to an external PHY. The I210 supports PCI Express* [PCIe v2.1 (2.5GT/s)].

The I210 enables 1000BASE-T implementations using an integrated PHY. It can be used for server system configurations such as rack mounted or pedestal servers, in an add-on NIC or LAN on Motherboard (LOM) design. Another possible system configuration is for blade servers as a LOM or mezzanine card. It can also be used in embedded applications such as switch add-on cards and network appliances.

1.1 ScopeThis document provides the external architecture (including device operation, pin descriptions, register definitions, etc.) for the I210.

This document is a reference for software device driver developers, board designers, test engineers, and others who may need specific technical or programming information.

1.2 Terminology and Acronyms

Table 1-1. Glossary

Definition Meaning

1000BASE-BX 1000BASE-BX is the PICMG 3.1 electrical specification for transmitting 1 Gb/s Ethernet or 1 Gb/s fibre channel encoded data over the backplane.

1000BASE-KX 1000BASE-KX is the IEEE802.3ap electrical specification for transmitting1 Gb/s Ethernet over the backplane.

1000BASE-CX 1000BASE-X over specialty shielded 150 balanced copper jumper cable assemblies as specified in IEEE 802.3 Clause 39.

1000BASE-T 1000BASE-T is the specification for 1 Gb/s Ethernet over category 5e twisted pair cables as defined in IEEE 802.3 clause 40.

AEN Asynchronous Event Notification

b/w Bandwidth.

BIOS Basic Input/Output System.

BMC Baseboard Management Controller - often used interchangeably with Manageability Controller (MC).

BT Bit Time.

CRC Cyclic redundancy check

DCA Direct Cache Access.

DDOFF Dynamic Device Off

Ethernet Controller I210 Introduction

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DFT Design for Testability.

DQ Descriptor Queue.

DMTF Distributed Management Task Force standard body.

DW Double word (4 bytes).

EEE Energy Efficient Ethernet - IEEE802.3az standard

EEPROM Electrically Erasable Programmable Memory. A non-volatile memory located on the LAN controller that is directly accessible from the host.

EOP End of Packet.

FC Flow Control.

FCS Frame Check