Intel® 9 Series Chipset Family Platform Controller Hub ... · Intel does not assu me any liability...

Intel® 9 Series Chipset Family Platform Controller Hub (PCH)Datasheet

June 2015

330550-002

2 Datasheet

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer.No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses.The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. 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Implementations of the I2C bus/protocol may require licenses from various entities, including NXP Semiconductors N.V.Intel® Anti-Theft Technology (Intel® AT): No system can provide absolute security under all conditions. Requires an enabled chipset, BIOS, firmware and software and a subscription with a capable Service Provider. Consult your System manufacturer and Service Provider for availability and functionality. Intel assumes no liability for lost or stolen data and/or systems or any other damages resulting thereof. For more information, visit http://www.intel.com/go/anti-theftIntel® High Definition Audio (Intel® HD Audio): Requires an Intel® HD Audio enabled system. Consult your PC manufacturer for more information. Sound quality will depend on equipment and actual implementation. For more information about Intel® HD Audio, refer to http://www.intel.com/design/chipsets/hdaudio.htmIntel® Trusted Execution Technology (Intel® TXT): No computer system can provide absolute security under all conditions. Intel® TXT requires a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, see http://www.intel.com/technology/securityIntel® Active Management Technology (Intel® AMT) requires activation and a system with a corporate network connection, an Intel® AMT-enabled chipset, network hardware and software. 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Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization.Intel® vPro™ Technology is sophisticated and requires setup and activation. Availability of features and results will depend upon the setup and configuration of your hardware, software and IT environment. To learn more visit: http://www.intel.com/technology/vpro Intel, Pentium, Intel vPro, Xeon, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.*Other names and brands may be claimed as the property of others.Copyright © 2014–2015, Intel Corporation. All rights reserved.

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Contents

1 Introduction ............................................................................................................ 411.1 About This Manual ............................................................................................. 41

1.1.1 Chapter Descriptions ............................................................................. 421.2 Overview ......................................................................................................... 44

1.2.1 Capability Overview............................................................................... 451.3 Intel® 9 Series Chipset Family PCH SKU Definition................................................. 521.4 Device and Revision ID Table .............................................................................. 55

2 Signal Description ................................................................................................... 572.1 Flexible I/O ...................................................................................................... 592.2 USB Interface ................................................................................................... 602.3 PCI Express* .................................................................................................... 632.4 Serial ATA Interface........................................................................................... 642.5 Clock Signals .................................................................................................... 662.6 Real Time Clock Interface................................................................................... 672.7 External RTC Circuitry........................................................................................ 682.8 Interrupt Interface ............................................................................................ 682.9 Processor Interface............................................................................................ 692.10 Direct Media Interface (DMI) to Host Controller ..................................................... 692.11 Intel® Flexible Display Interface (Intel® FDI) ........................................................ 702.12 Analog Display/VGA DAC Signals ......................................................................... 702.13 Digital Display Signals........................................................................................ 702.14 embedded DisplayPort* (eDP*) Backlight Control Signals ....................................... 712.15 Intel® High Definition Audio (Intel® HD Audio) Link ............................................... 712.16 Low Pin Count (LPC) Interface............................................................................. 722.17 General Purpose I/O Signals ............................................................................... 722.18 Functional Straps .............................................................................................. 782.19 SMBus Interface................................................................................................ 812.20 System Management Interface............................................................................ 812.21 Controller Link .................................................................................................. 812.22 Serial Peripheral Interface (SPI) .......................................................................... 822.23 Manageability Signals ........................................................................................ 822.24 Power Management Interface.............................................................................. 832.25 Power and Ground Signals.................................................................................. 862.26 Thermal Signals ................................................................................................ 872.27 Miscellaneous Signals ........................................................................................ 872.28 Testability Signals ............................................................................................. 882.29 Reserved / Test Pins .......................................................................................... 89

3 PCH Pin States......................................................................................................... 903.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 903.2 Output Signals Planes and States ........................................................................ 923.3 Input and I/O Signals Planes and States............................................................... 97

4 PCH and System Clocks ......................................................................................... 1024.1 Straps Related to Clock Configuration ................................................................ 1024.2 Platform Clocking Requirements ........................................................................ 1024.3 Functional Blocks ............................................................................................ 1044.4 Clock Configuration Access Overview ................................................................. 106

5 Functional Description ........................................................................................... 1075.1 Flexible I/O .................................................................................................... 1075.2 PCI-to-PCI Bridge............................................................................................ 108

5.2.1 PCI Bus Interface................................................................................ 1085.2.2 PCI Legacy Mode................................................................................. 108

5.3 PCI Express* Root Ports (D28:F0~F7)................................................................ 1085.3.1 Supported PCI Express* (PCIe*) Port Configurations................................ 1095.3.2 Interrupt Generation ........................................................................... 1095.3.3 Power Management ............................................................................. 110

5.3.3.1 S3/S4/S5 Support................................................................. 1105.3.3.2 Resuming from Suspended State............................................. 1105.3.3.3 Device Initiated PM_PME Message ........................................... 110

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5.3.3.4 SMI/SCI Generation...............................................................1115.3.3.5 Latency Tolerance Reporting (LTR) ..........................................1115.3.3.6 Opportunistic Buffer Flush/Fill (OBFF).......................................111

5.3.4 SERR# Generation...............................................................................1115.3.5 Hot-Plug.............................................................................................112

5.3.5.1 Presence Detection ................................................................1125.3.5.2 SMI/SCI Generation...............................................................112

5.4 Gigabit Ethernet Controller (B0:D25:F0) .............................................................1135.4.1 GbE PCI Express* Bus Interface ............................................................115

5.4.1.1 Transaction Layer ..................................................................1155.4.1.2 Data Alignment .....................................................................1155.4.1.3 Configuration Request Retry Status..........................................115

5.4.2 Error Events and Error Reporting ...........................................................1165.4.2.1 Data Parity Error ...................................................................1165.4.2.2 Completion with Unsuccessful Completion Status .......................116

5.4.3 Ethernet Interface ...............................................................................1165.4.3.1 Intel® Ethernet Network Connection I127LM/V Platform LAN

Connect Device Interface........................................................1165.4.4 PCI Power Management........................................................................117

5.4.4.1 Wake Up ..............................................................................1175.4.5 Configurable LEDs ...............................................................................1195.4.6 Function Level Reset Support (FLR)........................................................120

5.4.6.1 FLR Steps.............................................................................1205.5 Low Pin Count (LPC) Bridge (with System and

Management Functions) (D31:F0) ......................................................................1215.5.1 LPC Interface ......................................................................................121

5.5.1.1 LPC Cycle Types ....................................................................1225.5.1.2 Start Field Definition ..............................................................1225.5.1.3 Cycle Type / Direction (CYCTYPE + DIR)...................................1225.5.1.4 Size.....................................................................................1235.5.1.5 SYNC...................................................................................1235.5.1.6 SYNC Time-Out .....................................................................1235.5.1.7 SYNC Error Indication ............................................................1245.5.1.8 LFRAME# Usage....................................................................1245.5.1.9 I/O Cycles ............................................................................1245.5.1.10 Bus Master Cycles .................................................................1245.5.1.11 LPC Power Management .........................................................1245.5.1.12 Configuration and PCH Implications .........................................125

5.6 DMA Operation (D31:F0) ..................................................................................1255.6.1 Channel Priority...................................................................................126

5.6.1.1 Fixed Priority ........................................................................1265.6.1.2 Rotating Priority ....................................................................126

5.6.2 Address Compatibility Mode ..................................................................1265.6.3 Summary of DMA Transfer Sizes............................................................127

5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words .............................................................................127

5.6.4 Autoinitialize.......................................................................................1275.6.5 Software Commands............................................................................128

5.7 Low Pin Count (LPC) DMA .................................................................................1285.7.1 Asserting DMA Requests .......................................................................1285.7.2 Abandoning DMA Requests ...................................................................1295.7.3 General Flow of DMA Transfers ..............................................................1295.7.4 Terminal Count ...................................................................................1305.7.5 Verify Mode ........................................................................................1305.7.6 DMA Request De-assertion....................................................................1305.7.7 SYNC Field / LDRQ# Rules ....................................................................131

5.8 8254 Timers (D31:F0)......................................................................................1315.8.1 Timer Programming .............................................................................1325.8.2 Reading from the Interval Timer............................................................133

5.8.2.1 Simple Read .........................................................................1335.8.2.2 Counter Latch Command ........................................................1335.8.2.3 Read Back Command .............................................................134

5.9 8259 Programmable Interrupt Controllers (PIC) (D31:F0) .....................................1345.9.1 Interrupt Handling ...............................................................................135

5.9.1.1 Generating Interrupts ............................................................1355.9.1.2 Acknowledging Interrupts .......................................................1355.9.1.3 Hardware/Software Interrupt Sequence....................................136

4 Datasheet

5.9.2 Initialization Command Words (ICWx).................................................... 1365.9.2.1 ICW1 .................................................................................. 1365.9.2.2 ICW2 .................................................................................. 1375.9.2.3 ICW3 .................................................................................. 1375.9.2.4 ICW4 .................................................................................. 137

5.9.3 Operation Command Words (OCW)........................................................ 1375.9.4 Modes of Operation ............................................................................. 138

5.9.4.1 Fully Nested Mode................................................................. 1385.9.4.2 Special Fully-Nested Mode...................................................... 1385.9.4.3 Automatic Rotation Mode (Equal Priority Devices)...................... 1385.9.4.4 Specific Rotation Mode (Specific Priority).................................. 1385.9.4.5 Poll Mode............................................................................. 1395.9.4.6 Edge and Level Triggered Mode............................................... 1395.9.4.7 End of Interrupt (EOI) Operations ........................................... 1395.9.4.8 Normal End of Interrupt......................................................... 1395.9.4.9 Automatic End of Interrupt Mode............................................. 140

5.9.5 Masking Interrupts .............................................................................. 1405.9.5.1 Masking on an Individual Interrupt Request .............................. 1405.9.5.2 Special Mask Mode ................................................................ 140

5.9.6 Steering PCI Interrupts ........................................................................ 1405.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 141

5.10.1 Interrupt Handling............................................................................... 1415.10.2 Interrupt Mapping ............................................................................... 1415.10.3 PCI / PCI Express* Message-Based Interrupts......................................... 1425.10.4 IOxAPIC Address Remapping ................................................................ 1425.10.5 External Interrupt Controller Support..................................................... 142

5.11 Serial Interrupt (D31:F0) ................................................................................. 1435.11.1 Start Frame........................................................................................ 1435.11.2 Data Frames ...................................................................................... 1435.11.3 Stop Frame ........................................................................................ 1445.11.4 Specific Interrupts Not Supported Using SERIRQ ..................................... 1445.11.5 Data Frame Format ............................................................................. 144

5.12 Real Time Clock (D31:F0)................................................................................. 1455.12.1 Update Cycles..................................................................................... 1465.12.2 Interrupts .......................................................................................... 1465.12.3 Lockable RAM Ranges .......................................................................... 1465.12.4 Century Rollover ................................................................................. 1465.12.5 Clearing Battery-Backed RTC RAM......................................................... 146

5.13 Processor Interface (D31:F0) ............................................................................ 1485.13.1 Processor Interface Signals and VLW Messages ....................................... 148

5.13.1.1 INIT (Initialization)................................................................ 1485.13.1.2 FERR# (Numeric Coprocessor Error) ........................................ 1485.13.1.3 NMI (Non-Maskable Interrupt) ................................................ 1495.13.1.4 Processor Power Good (PROCPWRGD)...................................... 149

5.13.2 Dual-Processor Issues.......................................................................... 1495.13.2.1 Usage Differences ................................................................. 149

5.13.3 Virtual Legacy Wire (VLW) Messages ..................................................... 1495.14 Power Management ......................................................................................... 150

5.14.1 Features ............................................................................................ 1505.14.2 PCH and System Power States .............................................................. 1505.14.3 System Power Planes........................................................................... 1525.14.4 SMI# / SCI Generation ........................................................................ 152

5.14.4.1 PCI Express* SCI .................................................................. 1555.14.4.2 PCI Express* Hot-Plug ........................................................... 155

5.14.5 C-States ............................................................................................ 1555.14.6 Dynamic 33 MHz Clock Control (Mobile Only) .......................................... 155

5.14.6.1 Conditions for Checking the 33 MHz Clock ................................ 1565.14.6.2 Conditions for Maintaining the 33MHz Clock.............................. 1565.14.6.3 Conditions for Stopping the 33MHz Clock ................................. 1565.14.6.4 Conditions for Re-Starting the 33MHz Clock .............................. 1565.14.6.5 LPC Devices and CLKRUN#..................................................... 156

5.14.7 Sleep States....................................................................................... 1575.14.7.1 Sleep State Overview ............................................................ 1575.14.7.2 Initiating Sleep State............................................................. 1575.14.7.3 Exiting Sleep States .............................................................. 1575.14.7.4 PCI Express* WAKE# Signal and PME Event Message................. 1595.14.7.5 Sx-G3-Sx, Handling Power Failures.......................................... 159

Datasheet 5

5.14.7.6 Deep Sx ...............................................................................1605.14.8 Event Input Signals and Their Usage ......................................................161

5.14.8.1 PWRBTN# (Power Button) ......................................................1615.14.8.2 RI# (Ring Indicator) ..............................................................1625.14.8.3 PME# (PCI Power Management Event) .....................................1635.14.8.4 SYS_RESET# Signal...............................................................1635.14.8.5 THRMTRIP# Signal ................................................................163

5.14.9 ALT Access Mode .................................................................................1645.14.9.1 Write Only Registers with Read Paths in ALT Access Mode ...........1655.14.9.2 PIC Reserved Bits ..................................................................1665.14.9.3 Read Only Registers with Write Paths in ALT Access Mode ...........166

5.14.10 System Power Supplies, Planes, and Signals ...........................................1675.14.10.1 Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#.............................1675.14.10.2 SLP_S4# and Suspend-To-RAM Sequencing ..............................1675.14.10.3 PWROK Signal.......................................................................1685.14.10.4 BATLOW# (Battery Low) (Mobile Only).....................................1685.14.10.5 SLP_LAN# Pin Behavior..........................................................1685.14.10.6 SLP_WLAN# Pin Behavior .......................................................1705.14.10.7 SUSPWRDNACK/SUSWARN#/GPIO30 Steady State Pin Behavior..1705.14.10.8 RTCRST# and SRTCRST# .......................................................171

5.14.11 Legacy Power Management Theory of Operation ......................................1715.14.11.1 APM Power Management (Desktop Only) ..................................1715.14.11.2 Mobile APM Power Management (Mobile Only) ...........................171

5.14.12 Reset Behavior....................................................................................1725.15 System Management (D31:F0) ..........................................................................173

5.15.1 Theory of Operation.............................................................................1745.15.1.1 Detecting a System Lockup.....................................................1745.15.1.2 Handling an Intruder..............................................................1745.15.1.3 Detecting Improper Flash Programming....................................1755.15.1.4 Heartbeat and Event Reporting using SMLink/SMBus ..................175

5.15.2 TCO Modes .........................................................................................1755.15.2.1 TCO Legacy / Compatible Mode ...............................................1755.15.2.2 Advanced TCO Mode ..............................................................176

5.16 General Purpose I/O (D31:F0) ...........................................................................1775.16.1 Power Wells ........................................................................................1775.16.2 SMI#, SCI, and NMI Routing.................................................................1775.16.3 Triggering ..........................................................................................1785.16.4 GPIO Registers Lockdown .....................................................................1785.16.5 Serial POST Codes over GPIO................................................................178

5.16.5.1 Theory of Operation...............................................................1795.16.5.2 Serial Message Format ...........................................................180

5.17 SATA Host Controller (D31:F2, F5).....................................................................1815.17.1 SATA 6 Gb/s Support ...........................................................................1815.17.2 SATA Feature Support..........................................................................1815.17.3 Theory of Operation.............................................................................182

5.17.3.1 Standard ATA Emulation.........................................................1825.17.3.2 48-Bit LBA Operation .............................................................183

5.17.4 SATA Swap Bay Support.......................................................................1835.17.5 Hot-Plug Operation ..............................................................................1835.17.6 Intel® Rapid Storage Technology (Intel RST®) Configuration.....................183

5.17.6.1 Intel® Rapid Storage Technology (Intel® RST) RAID Option ROM.1845.17.7 Intel® Smart Response Technology........................................................1845.17.8 Power Management Operation...............................................................184

5.17.8.1 Power State Mappings............................................................1855.17.8.2 Power State Transitions..........................................................1855.17.8.3 SMI Trapping (APM)...............................................................186

5.17.9 SATA Device Presence..........................................................................1865.17.10 SATA LED...........................................................................................1875.17.11 AHCI Operation ...................................................................................1875.17.12 SGPIO Signals.....................................................................................188

5.17.12.1 Mechanism ...........................................................................1885.17.12.2 Message Format....................................................................1895.17.12.3 LED Message Type.................................................................1895.17.12.4 SGPIO Waveform ..................................................................191

5.17.13 External SATA.....................................................................................1925.18 High Precision Event Timers (HPET)....................................................................192

6 Datasheet

5.18.1 Timer Accuracy................................................................................... 1925.18.2 Interrupt Mapping ............................................................................... 1925.18.3 Periodic versus Non-Periodic Modes ....................................................... 1945.18.4 Enabling the Timers............................................................................. 1945.18.5 Interrupt Levels .................................................................................. 1955.18.6 Handling Interrupts ............................................................................. 1955.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors............................. 195

5.19 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 1965.19.1 EHC Initialization ................................................................................ 196

5.19.1.1 BIOS Initialization ................................................................. 1965.19.1.2 Driver Initialization................................................................ 1965.19.1.3 EHC Resets .......................................................................... 196

5.19.2 Data Structures in Main Memory ........................................................... 1965.19.3 USB 2.0 Enhanced Host Controller DMA ................................................. 1975.19.4 Data Encoding and Bit Stuffing.............................................................. 1975.19.5 Packet Formats................................................................................... 1975.19.6 USB 2.0 Interrupts and Error Conditions................................................. 197

5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads .............................. 1985.19.7 USB 2.0 Power Management................................................................. 198

5.19.7.1 Pause Feature ...................................................................... 1985.19.7.2 Suspend Feature................................................................... 1985.19.7.3 ACPI Device States................................................................ 1985.19.7.4 ACPI System States .............................................................. 199

5.19.8 USB 2.0 Legacy Keyboard Operation...................................................... 1995.19.9 USB 2.0 Based Debug Port ................................................................... 199

5.19.9.1 Theory of Operation ............................................................. 2005.19.10 EHCI Caching ..................................................................................... 2045.19.11 Intel® USB Prefetch Based Pause .......................................................... 2045.19.12 Function Level Reset Support (FLR) ....................................................... 204

5.19.12.1 FLR Steps ............................................................................ 2055.19.13 USB Overcurrent Protection .................................................................. 205

5.20 Integrated USB 2.0 Rate Matching Hub .............................................................. 2065.20.1 Overview ........................................................................................... 2065.20.2 Architecture ....................................................................................... 206

5.21 xHCI Controller (D20:F0) ................................................................................. 2075.22 SMBus Controller (D31:F3) ............................................................................... 207

5.22.1 Host Controller ................................................................................... 2085.22.1.1 Command Protocols .............................................................. 208

5.22.2 Bus Arbitration ................................................................................... 2125.22.3 Bus Timing......................................................................................... 212

5.22.3.1 Clock Stretching ................................................................... 2125.22.3.2 Bus Time Out (The PCH as SMBus Master)................................ 212

5.22.4 Interrupts / SMI# ............................................................................... 2125.22.5 SMBALERT# ....................................................................................... 2135.22.6 SMBus CRC Generation and Checking .................................................... 2145.22.7 SMBus Slave Interface......................................................................... 214

5.22.7.1 Format of Slave Write Cycle ................................................... 2155.22.7.2 Format of Read Command...................................................... 2165.22.7.3 Slave Read of RTC Time Bytes ................................................ 2175.22.7.4 Format of Host Notify Command ............................................. 218

5.23 Thermal Management ...................................................................................... 2195.23.1 Thermal Sensor .................................................................................. 219

5.23.1.1 Internal Thermal Sensor Operation.......................................... 2195.23.2 PCH Thermal Throttling........................................................................ 2205.23.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1) ... 221

5.23.3.1 Block Read Address............................................................... 2225.23.3.2 Block Read Command............................................................ 2225.23.3.3 Read Data Format................................................................. 2225.23.3.4 Thermal Data Update Rate ..................................................... 2225.23.3.5 Temperature Comparator and Alert ......................................... 2235.23.3.6 BIOS Set Up......................................................................... 2245.23.3.7 SMBus Rules ........................................................................ 2245.23.3.8 Case for Considerations ......................................................... 225

5.24 Intel® High Definition Audio (Intel® HD Audio) Overview (D27:F0) ........................ 2275.24.1 Intel® High Definition Audio (Intel® HD Audio) Docking (Mobile Only) ........ 227

5.24.1.1 Dock Sequence..................................................................... 2275.24.1.2 Exiting D3/CRST# When Docked ............................................. 228

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5.24.1.3 Cold Boot/Resume from S3 When Docked.................................2295.24.1.4 Undock Sequence ..................................................................2295.24.1.5 Normal Undock .....................................................................2295.24.1.6 Surprise Undock....................................................................2305.24.1.7 Interaction between Dock/Undock and Power Management States2305.24.1.8 Relationship between HDA_DOCK_RST# and HDA_RST# ............230

5.25 Intel® Management Engine (Intel® ME) and Intel® Management Engine Firmware (Intel® ME FW) 9.0 ...............................................2315.25.1 Intel® Management Engine (Intel® ME) Requirements..............................232

5.26 Serial Peripheral Interface (SPI) ........................................................................2335.26.1 SPI Supported Feature Overview ...........................................................233

5.26.1.1 Non-Descriptor Mode .............................................................2335.26.1.2 Descriptor Mode ....................................................................234

5.26.2 Flash Descriptor ..................................................................................2355.26.2.1 Descriptor Master Region........................................................236

5.26.3 Flash Access .......................................................................................2365.26.3.1 Direct Access Security............................................................2375.26.3.2 Register Access Security.........................................................237

5.26.4 Serial Flash Device Compatibility Requirements .......................................2375.26.4.1 PCH SPI Based BIOS Requirements..........................................2375.26.4.2 Integrated LAN Firmware SPI Flash Requirements......................2385.26.4.3 Intel® Management Engine Firmware (Intel® ME FW) SPI Flash

Requirements .......................................................................2385.26.4.4 Hardware Sequencing Requirements ........................................239

5.26.5 Multiple Page Write Usage Model ...........................................................2405.26.5.1 Soft Flash Protection ..............................................................2405.26.5.2 BIOS Range Write Protection...................................................2415.26.5.3 SMI# Based Global Write Protection.........................................241

5.26.6 Flash Device Configurations ..................................................................2415.26.7 SPI Flash Device Recommended Pinout...................................................2415.26.8 Serial Flash Device Package ..................................................................242

5.26.8.1 Common Footprint Usage Model ..............................................2425.26.8.2 Serial Flash Device Package Recommendations..........................242

5.27 Feature Capability Mechanism ...........................................................................2435.28 PCH Display Interface and Intel® Flexible Display Interface (Intel® FDI)

Interconnect ...................................................................................................2435.28.1 Analog Display Interface Characteristics .................................................244

5.28.1.1 Integrated RAMDAC...............................................................2445.28.1.2 DDC (Display Data Channel) ...................................................244

5.28.2 Digital Display Side Band Signals ...........................................................2455.28.2.1 DisplayPort AUX CH ...............................................................2455.28.2.2 DDC (Display Data Channel) ...................................................2455.28.2.3 Hot-Plug Detect.....................................................................2455.28.2.4 Map of Digital Display Side Band Signals Per Display

Configuration ........................................................................2455.28.2.5 Panel Power Sequencing and Backlight Control ..........................246

5.28.3 Intel® Flexible Display Interface (Intel® FDI) ..........................................2465.29 Intel® Virtualization Technology (Intel® VT) ........................................................247

5.29.1 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives.....................................................247

5.29.2 Intel® VT-d Features Supported ............................................................2475.29.3 Support for Function Level Reset (FLR) in PCH.........................................2475.29.4 Virtualization Support for PCH IOxAPIC...................................................2485.29.5 Virtualization Support for High Precision Event Timer (HPET) .....................248

6 Ballout Definition ...................................................................................................2496.1 Desktop PCH Ballout ........................................................................................2496.2 Mobile PCH Ballout...........................................................................................258

7 Package Information .............................................................................................2667.1 Desktop PCH Package.......................................................................................266

7.1.1 Tape and Reel Pin 1 Placement..............................................................2667.2 Mobile PCH Package .........................................................................................268

7.2.1 Tape and Reel Pin 1 Placement..............................................................2688 Electrical Characteristics........................................................................................270

8.1 Thermal Specifications......................................................................................2708.1.1 Storage Specifications and Thermal Design Power (TDP) ...........................270

8 Datasheet

8.2 Absolute Maximum Ratings............................................................................... 2718.3 PCH Power Supply Range ................................................................................. 2718.4 General DC Characteristics ............................................................................... 2728.5 Display DC Characteristics ................................................................................ 2818.6 AC Characteristics ........................................................................................... 2828.7 Power Sequencing and Reset Signal Timings ....................................................... 2938.8 Power Management Timing Diagrams................................................................. 2968.9 AC Timing Diagrams ........................................................................................ 3018.10 Sequencing Rails Within The Same Well ............................................................. 312

9 Register and Memory Mapping............................................................................... 3139.1 PCI Devices and Functions................................................................................ 3149.2 PCI Configuration Map ..................................................................................... 3159.3 I/O Map ......................................................................................................... 315

9.3.1 Fixed I/O Address Ranges .................................................................... 3159.3.2 Variable I/O Decode Ranges ................................................................. 317

9.4 Memory Map................................................................................................... 3189.4.1 Boot-Block Update Scheme .................................................................. 320

10 Chipset Configuration Registers............................................................................. 32210.1 Chipset Configuration Registers (Memory Space) ................................................. 322

10.1.1 RPC—Root Port Configuration Register ................................................... 32410.1.2 RPFN—Root Port Function Number and Hide for PCI

Express* Root Ports Register ................................................................ 32410.1.3 FLRSTAT—Function Level Reset Pending Status Register........................... 32610.1.4 TRSR—Trap Status Register.................................................................. 32610.1.5 TRCR—Trapped Cycle Register .............................................................. 32710.1.6 TWDR—Trapped Write Data Register...................................................... 32710.1.7 IOTRn—I/O Trap Register (0–3) ............................................................ 32810.1.8 V0CTL—Virtual Channel 0 Resource Control Register................................ 32910.1.9 V0STS—Virtual Channel 0 Resource Status Register................................. 32910.1.10 V1CTL—Virtual Channel 1 Resource Control Register................................ 32910.1.11 V1STS—Virtual Channel 1 Resource Status Register................................. 33010.1.12 REC—Root Error Command Register ...................................................... 33010.1.13 LCAP—Link Capabilities Register............................................................ 33010.1.14 LCTL—Link Control Register.................................................................. 33110.1.15 LSTS—Link Status Register................................................................... 33110.1.16 TCTL—TCO Configuration Register ........................................................ 33110.1.17 D31IP—Device 31 Interrupt Pin Register ................................................ 33210.1.18 D30IP—Device 30 Interrupt Pin Register ................................................ 33210.1.19 D29IP—Device 29 Interrupt Pin Register ................................................ 33310.1.20 D28IP—Device 28 Interrupt Pin Register ................................................ 33310.1.21 D27IP—Device 27 Interrupt Pin Register ................................................ 33410.1.22 D26IP—Device 26 Interrupt Pin Register ................................................ 33510.1.23 D25IP—Device 25 Interrupt Pin Register ................................................ 33510.1.24 D22IP—Device 22 Interrupt Pin Register ................................................ 33510.1.25 D20IP—Device 20 Interrupt Pin Register ................................................ 33610.1.26 D31IR—Device 31 Interrupt Route Register ............................................ 33610.1.27 D30IR—Device 30 Interrupt Route Register ............................................ 33710.1.28 D29IR—Device 29 Interrupt Route Register ............................................ 33710.1.29 D28IR—Device 28 Interrupt Route Register ............................................ 33810.1.30 D27IR—Device 27 Interrupt Route Register ............................................ 33910.1.31 D26IR—Device 26 Interrupt Route Register ............................................ 34010.1.32 D25IR—Device 25 Interrupt Route Register ............................................ 34110.1.33 D22IR—Device 22 Interrupt Route Register ............................................ 34210.1.34 D20IR—Device 20 Interrupt Route Register ............................................ 34310.1.35 OIC—Other Interrupt Control Register.................................................... 34410.1.36 WADT_AC—Wake Alarm Device Timer – AC Register................................ 34410.1.37 WADT_DC—Wake Alarm Device Timer – DC Register ............................... 34410.1.38 WADT_EXP_AC—Wake Alarm Device Expired Timer – AC

Register............................................................................................. 34510.1.39 WADT_EXP_DC—Wake Alarm Device Expired Timer – DC

Register............................................................................................. 34510.1.40 PRSTS—Power and Reset Status Register ............................................... 34510.1.41 PM_CFG—Power Management Configuration Register ............................... 34610.1.42 DEEP_S3_POL—Deep Sx From S3 Power Policies Register......................... 34810.1.43 DEEP_S4_POL—Deep Sx From S4 Power Policies Register......................... 348

Datasheet 9

10.1.44 DEEP_S5_POL—Deep Sx From S5 Power Policies Register .........................34810.1.45 DSX_CFG—Deep Sx Configuration Register .............................................34910.1.46 PMSYNC_CFG—PMSYNC Configuration....................................................34910.1.47 RC—RTC Configuration Register.............................................................35010.1.48 HPTC—High Precision Timer Configuration Register ..................................35010.1.49 GCS—General Control and Status Register ..............................................35110.1.50 BUC—Backed Up Control Register ..........................................................35210.1.51 FD—Function Disable Register ...............................................................35210.1.52 CG—Clock Gating Register ....................................................................35410.1.53 FDSW—Function Disable SUS Well Register .............................................35510.1.54 DISPBDF—Display Bus, Device and Function

Initialization Register ...........................................................................35510.1.55 FD2—Function Disable 2 Register...........................................................355

11 Gigabit LAN Configuration Registers ......................................................................35611.1 Gigabit LAN Configuration Registers

(Gigabit LAN—D25:F0) .....................................................................................35611.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0) .........................................................................35711.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0) .........................................................................35711.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0) .........................................................................35811.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0) .........................................................................35811.1.5 RID—Revision Identification Register

(Gigabit LAN—D25:F0) .........................................................................35911.1.6 CC—Class Code Register

(Gigabit LAN—D25:F0) .........................................................................35911.1.7 CLS—Cache Line Size Register

(Gigabit LAN—D25:F0) .........................................................................36011.1.8 PLT—Primary Latency Timer Register

(Gigabit LAN—D25:F0) .........................................................................36011.1.9 HEADTYP—Header Type Register

(Gigabit LAN—D25:F0) .........................................................................36011.1.10 MBARA—Memory Base Address Register A

(Gigabit LAN—D25:F0) .........................................................................36011.1.11 MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0) .........................................................................36111.1.12 MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0) .........................................................................36111.1.13 SVID—Subsystem Vendor ID Register

(Gigabit LAN—D25:F0) .........................................................................36111.1.14 SID—Subsystem ID Register

(Gigabit LAN—D25:F0) .........................................................................36211.1.15 ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0) .........................................................................36211.1.16 CAPP—Capabilities List Pointer Register

(Gigabit LAN—D25:F0) .........................................................................36211.1.17 INTR—Interrupt Information Register

(Gigabit LAN—D25:F0) .........................................................................36211.1.18 MLMG—Maximum Latency / Minimum Grant Register

(Gigabit LAN—D25:F0) .........................................................................36211.1.19 STCL—System Time Control Low Register

(Gigabit LAN—D25:F0) .........................................................................36311.1.20 STCH—System Time Control High Register

(Gigabit LAN—D25:F0) .........................................................................36311.1.21 LTRCAP—System Time Control High Register

(Gigabit LAN—D25:F0) .........................................................................36311.1.22 CLIST1—Capabilities List Register 1

(Gigabit LAN—D25:F0) .........................................................................36411.1.23 PMC—PCI Power Management Capabilities Register

(Gigabit LAN—D25:F0) .........................................................................36411.1.24 PMCS—PCI Power Management Control and Status

Register (Gigabit LAN—D25:F0).............................................................36411.1.25 DR—Data Register

(Gigabit LAN—D25:F0) .........................................................................365

10 Datasheet

11.1.26 CLIST2—Capabilities List Register 2(Gigabit LAN—D25:F0) ........................................................................ 365

11.1.27 MCTL—Message Control Register(Gigabit LAN—D25:F0) ........................................................................ 366

11.1.28 MADDL—Message Address Low Register(Gigabit LAN—D25:F0) ........................................................................ 366

11.1.29 MADDH—Message Address High Register(Gigabit LAN—D25:F0) ........................................................................ 366

11.1.30 MDAT—Message Data Register(Gigabit LAN—D25:F0) ........................................................................ 366

11.1.31 FLRCAP—Function Level Reset Capability(Gigabit LAN—D25:F0) ........................................................................ 367

11.1.32 FLRCLV—Function Level Reset Capability Length andVersion Register (Gigabit LAN—D25:F0) ................................................. 367

11.1.33 DEVCTRL—Device Control Register (Gigabit LAN—D25:F0) ....................... 36811.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 368

11.2.1 GBECSR_00—Gigabit Ethernet Capabilities and Status Register 00............. 36911.2.2 GBECSR_18—Gigabit Ethernet Capabilities and Status Register 18............. 36911.2.3 GBECSR_20—Gigabit Ethernet Capabilities and Status Register 20............. 36911.2.4 GBECSR_F00—Gigabit Ethernet Capabilities and Status Register F00 ......... 37011.2.5 GBECSR_F10—Gigabit Ethernet Capabilities and Status Register F10 ......... 37011.2.6 GBECSR_5400—Gigabit Ethernet Capabilities and Status Register 5400...... 37011.2.7 GBECSR_5404—Gigabit Ethernet Capabilities and Status Register 5404...... 37011.2.8 GBECSR_5800—Gigabit Ethernet Capabilities and Status Register 5800...... 37111.2.9 GBECSR_5B54—Gigabit Ethernet Capabilities and Status Register 5B54 ..... 371

12 LPC Interface Bridge Registers (D31:F0) ............................................................... 37212.1 PCI Configuration Registers (LPC I/F—D31:F0).................................................... 372

12.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)............................. 37312.1.2 DID—Device Identification Register (LPC I/F—D31:F0) ............................. 37312.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ............................... 37312.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)...................................... 37412.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)........................... 37512.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)............................ 37512.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ................................... 37512.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0) .................................. 37512.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) .......................... 37512.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) ................................ 37512.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) ........................... 37612.1.12 CAPP—Capability List Pointer Register (LPC I/F—D31:F0) ......................... 37612.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) ......................... 37612.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0) ............................. 37712.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F—D31:F0) ..................... 37712.1.16 GC—GPIO Control Register (LPC I/F—D31:F0) ........................................ 37812.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0)............................................................................... 37812.1.18 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0)............................................................................... 37912.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0)............................................................................... 37912.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0)............................................................................... 38012.1.21 LPC_HnBDF—HPET n Bus:Device:Function

(LPC I/F—D31:F0)............................................................................... 38012.1.22 LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0)............................................................................... 38112.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) .............................. 38112.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0)............................................................................... 38212.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register



(LPC I/F—D31:F0)............................................................................... 38412.1.28 ULKMC—USB Legacy Keyboard / Mouse

Control Register(LPC I/F—D31:F0) ........................................................ 384

Datasheet 11

12.1.29 LGMR—LPC I/F Generic Memory Range Register(LPC I/F—D31:F0) ...............................................................................385

12.1.30 BIOS_SEL1—BIOS Select 1 Register (LPC I/F—D31:F0) ...............................................................................386

12.1.31 BIOS_SEL2—BIOS Select 2 Register (LPC I/F—D31:F0) ...............................................................................387

12.1.32 BIOS_DEC_EN1—BIOS Decode Enable Register (LPC I/F—D31:F0)...................................................................387

12.1.33 BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) ...............................................................................389

12.1.34 FDCAP—Feature Detection Capability ID Register(LPC I/F—D31:F0) ...............................................................................389

12.1.35 FDLEN—Feature Detection Capability Length Register(LPC I/F—D31:F0) ...............................................................................390

12.1.36 FDVER—Feature Detection Version Register(LPC I/F—D31:F0) ...............................................................................390

12.1.37 FVECIDX—Feature Vector Index Register(LPC I/F—D31:F0) ...............................................................................390

12.1.38 FVECD—Feature Vector Data Register(LPC I/F—D31:F0) ...............................................................................390

12.1.39 Feature Vector Space ...........................................................................39112.1.39.1 FVEC0—Feature Vector Register 0............................................39112.1.39.2 FVEC1—Feature Vector Register 1............................................39212.1.39.3 FVEC2—Feature Vector Register 2............................................39212.1.39.4 FVEC3—Feature Vector Register 3............................................392

12.1.40 RCBA—Root Complex Base Address Register (LPC I/F—D31:F0) ...............................................................................393

12.2 DMA I/O Registers ...........................................................................................39312.2.1 DMABASE_CA—DMA Base and Current Address Registers .........................39412.2.2 DMABASE_CC—DMA Base and Current Count Registers ............................39512.2.3 DMAMEM_LP—DMA Memory Low Page Registers ......................................39512.2.4 DMACMD—DMA Command Register........................................................39612.2.5 DMASTA—DMA Status Register..............................................................39612.2.6 DMA_WRSMSK—DMA Write Single Mask Register.....................................39712.2.7 DMACH_MODE—DMA Channel Mode Register ..........................................39712.2.8 DMA Clear Byte Pointer Register ............................................................39812.2.9 DMA Master Clear Register....................................................................39812.2.10 DMA_CLMSK—DMA Clear Mask Register .................................................39812.2.11 DMA_WRMSK—DMA Write All Mask Register............................................399

12.3 Timer I/O Registers..........................................................................................39912.3.1 TCW—Timer Control Word Register ........................................................40012.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register..........................40212.3.3 Counter Access Ports Register ...............................................................402

12.4 8259 Interrupt Controller (PIC) Registers ............................................................40312.4.1 Interrupt Controller I/O MAP .................................................................40312.4.2 ICW1—Initialization Command Word 1 Register .......................................40312.4.3 ICW2—Initialization Command Word 2 Register .......................................40412.4.4 ICW3—Master Controller Initialization Command

Word 3 Register ..................................................................................40512.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register ..................................................................................40512.4.6 ICW4—Initialization Command Word 4 Register .......................................40512.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Register .............................................................................................40612.4.8 OCW2—Operational Control Word 2 Register ...........................................40612.4.9 OCW3—Operational Control Word 3 Register ...........................................40712.4.10 ELCR1—Master Controller Edge/Level Triggered Register ..........................40812.4.11 ELCR2—Slave Controller Edge/Level Triggered Register ............................409

12.5 Advanced Programmable Interrupt Controller (APIC) ............................................41012.5.1 APIC Register Map ...............................................................................41012.5.2 IND—Index Register ............................................................................41012.5.3 DAT—Data Register .............................................................................41112.5.4 EOIR—EOI Register .............................................................................41112.5.5 ID—Identification Register ....................................................................41212.5.6 VER—Version Register..........................................................................41212.5.7 REDIR_TBL—Redirection Table Register ..................................................413

12.6 Real Time Clock Registers .................................................................................414

12 Datasheet

12.6.1 I/O Register Address Map..................................................................... 41412.6.2 Indexed Registers ............................................................................... 415

12.6.2.1 RTC_REGA—Register A .......................................................... 41612.6.2.2 RTC_REGB—Register B (General Configuration) ........................ 41712.6.2.3 RTC_REGC—Register C (Flag Register)..................................... 41812.6.2.4 RTC_REGD—Register D (Flag Register) .................................... 418

12.7 Processor Interface Registers ............................................................................ 41812.7.1 NMI_SC—NMI Status and Control Register.............................................. 41912.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

Register............................................................................................. 41912.7.3 PORT92—Init Register ......................................................................... 42012.7.4 COPROC_ERR—Coprocessor Error Register ............................................. 42012.7.5 RST_CNT—Reset Control Register ......................................................... 420

12.8 Power Management Registers ........................................................................... 42112.8.1 Power Management PCI Configuration Registers

(PM—D31:F0)..................................................................................... 42112.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0)....................................................................... 42112.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0)....................................................................... 42312.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0)....................................................................... 42412.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration

Lock Register ....................................................................... 42712.8.1.5 BM_BREAK_EN_2 Register #2 (PM—D31:F0) ............................ 42712.8.1.6 BM_BREAK_EN Register (PM—D31:F0)..................................... 42812.8.1.7 GPI_ROUT—GPI Routing Control Register

(PM—D31:F0)....................................................................... 42912.8.1.8 GPI_ROUT2—GPI Routing Control Register #2 (PM-D31:F0) ....... 430

12.8.2 APM I/O Decode Register ..................................................................... 43012.8.2.1 APM_CNT—Advanced Power Management Control Port Register... 43012.8.2.2 APM_STS—Advanced Power Management Status Port Register .... 431

12.8.3 Power Management I/O Registers.......................................................... 43112.8.3.1 PM1_STS—Power Management 1 Status Register ...................... 43212.8.3.2 PM1_EN—Power Management 1 Enable Register........................ 43312.8.3.3 PM1_CNT—Power Management 1 Control Register ..................... 43412.8.3.4 PM1_TMR—Power Management 1 Timer Register....................... 43512.8.3.5 GPE0_STS—General Purpose Event 0 Status Register ................ 43512.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register ................ 43812.8.3.7 SMI_EN—SMI Control and Enable Register................................ 43912.8.3.8 SMI_STS—SMI Status Register ............................................... 44112.8.3.9 ALT_GPI_SMI_EN—Alternate GPI SMI Enable Register ............... 44312.8.3.10 ALT_GPI_SMI_STS—Alternate GPI SMI Status Register .............. 44312.8.3.11 GPE_CNTL—General Purpose Control Register ........................... 44312.8.3.12 DEVACT_STS—Device Activity Status Register .......................... 44412.8.3.13 PM2_CNT—Power Management 2 Control Register ..................... 44512.8.3.14 ALT_GPI_SMI_EN2—Alternate GPI SMI Enable 2 Register ........... 44512.8.3.15 ALT_GPI_SMI_STS2—Alternate GPI SMI Status 2 Register.......... 445

12.9 System Management TCO Registers................................................................... 44612.9.1 TCO_RLD—TCO Timer Reload and Current Value Register ......................... 44712.9.2 TCO_DAT_IN—TCO Data In Register...................................................... 44712.9.3 TCO_DAT_OUT—TCO Data Out Register ................................................. 44712.9.4 TCO1_STS—TCO1 Status Register ......................................................... 44712.9.5 TCO2_STS—TCO2 Status Register ......................................................... 44812.9.6 TCO1_CNT—TCO1 Control Register........................................................ 44912.9.7 TCO2_CNT—TCO2 Control Register........................................................ 45012.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers...................................... 45112.9.9 TCO_WDCNT—TCO Watchdog Control Register........................................ 45112.9.10 SW_IRQ_GEN—Software IRQ Generation Register ................................... 45112.9.11 TCO_TMR—TCO Timer Initial Value Register ........................................... 451

12.10 General Purpose I/O Registers .......................................................................... 45212.10.1 GPIO_USE_SEL—GPIO Use Select Register ............................................. 45312.10.2 GP_IO_SEL—GPIO Input/Output Select Register...................................... 45312.10.3 GP_LVL—GPIO Level for Input or Output Register .................................... 45312.10.4 GPO_BLINK—GPO Blink Enable Register ................................................. 45412.10.5 GP_SER_BLINK—GP Serial Blink Register ............................................... 454

Datasheet 13

12.10.6 GP_SB_CMDSTS—GP Serial Blink CommandStatus Register ...................................................................................455

12.10.7 GP_SB_DATA—GP Serial Blink Data Register ...........................................45512.10.8 GPI_NMI_EN—GPI NMI Enable Register ..................................................45512.10.9 GPI_NMI_STS—GPI NMI Status Register.................................................45612.10.10GPI_INV—GPIO Signal Invert Register....................................................45612.10.11GPIO_USE_SEL2—GPIO Use Select 2 Register .........................................45712.10.12GP_IO_SEL2—GPIO Input/Output Select 2 Register .................................45712.10.13GP_LVL2—GPIO Level for Input or Output 2 Register................................45812.10.14GPIO_USE_SEL3—GPIO Use Select 3 Register .........................................45812.10.15GP_IO_SEL3—GPIO Input/Output Select 3 Register .................................45912.10.16GP_LVL3—GPIO Level for Input or Output 3 Register................................45912.10.17GP_RST_SEL1—GPIO Reset Select Register ............................................45912.10.18GP_RST_SEL2—GPIO Reset Select Register ............................................46012.10.19GP_RST_SEL3—GPIO Reset Select Register ............................................460

13 SATA Controller Registers (D31:F2) .......................................................................46113.1 PCI Configuration Registers (SATA–D31:F2) ........................................................461

13.1.1 VID—Vendor Identification Register (SATA—D31:F2)................................46213.1.2 DID—Device Identification Register (SATA—D31:F2) ................................46313.1.3 PCICMD—PCI Command Register (SATA–D31:F2) ....................................46313.1.4 PCISTS—PCI Status Register (SATA–D31:F2) ..........................................46413.1.5 RID—Revision Identification Register (SATA—D31:F2) ..............................46413.1.6 PI—Programming Interface Register (SATA–D31:F2) ................................465

13.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h .........46513.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .........46513.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h .........465

13.1.7 SCC—Sub Class Code Register (SATA–D31:F2)........................................46613.1.8 BCC—Base Class Code Register

(SATA–D31:F2SATA–D31:F2)................................................................46613.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2)...................................................................................46613.1.10 HTYPE—Header Type Register

(SATA–D31:F2)...................................................................................46613.1.11 PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F2) ......................................................................46713.1.12 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2)...................................................................................46713.1.13 SCMD_BAR—Secondary Command Block Base Address

Register (SATA D31:F2) .......................................................................46713.1.14 SCNL_BAR—Secondary Control Block Base Address

Register (SATA D31:F2) .......................................................................46813.1.15 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F2)...................................................................................46813.1.16 ABAR/SIDPBA1—AHCI Base Address Register / Serial ATA

Index Data Pair Base Address (SATA–D31:F2).........................................46813.1.16.1 When SCC is not 01h .............................................................46913.1.16.2 When SCC is 01h...................................................................469

13.1.17 SVID—Subsystem Vendor Identification Register (SATA–D31:F2)...................................................................................469

13.1.18 SID—Subsystem Identification Register (SATA–D31:F2) ...........................47013.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2)...................................47013.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) .....................................47013.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2).......................................47013.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2)........................................47113.1.23 SIDETIM—Slave IDE Timing Register (SATA–D31:F2) ...............................47113.1.24 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2)...................................................................................47113.1.25 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2)...................................................................................47213.1.26 IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2)...................................................................................47213.1.27 PID—PCI Power Management Capability Identification

Register (SATA–D31:F2) ......................................................................47213.1.28 PC—PCI Power Management Capabilities Register

(SATA–D31:F2)...................................................................................473

14 Datasheet

13.1.29 PMCS—PCI Power Management Control and StatusRegister (SATA–D31:F2) ...................................................................... 473

13.1.30 MSICI—Message Signaled Interrupt CapabilityIdentification Register (SATA–D31:F2) ................................................... 474

13.1.31 MSIMC—Message Signaled Interrupt MessageControl Register (SATA–D31:F2) ........................................................... 474

13.1.32 MSIMA—Message Signaled Interrupt MessageAddress Register (SATA–D31:F2) .......................................................... 475

13.1.33 MSIMD—Message Signaled Interrupt MessageData Register (SATA–D31:F2)............................................................... 476

13.1.34 MAP—Address Map Register (SATA–D31:F2)........................................... 47613.1.35 PCS—Port Control and Status Register (SATA–D31:F2) ............................ 47613.1.36 SCLKCG—SATA Clock Gating Control Register ......................................... 47913.1.37 SGC—SATA General Configuration Register............................................. 47913.1.38 SATACR0—SATA Capability Register 0 (SATA–D31:F2)............................. 48013.1.39 SATACR1—SATA Capability Register 1 (SATA–D31:F2)............................. 48013.1.40 FLRCID—FLR Capability Identification Register (SATA–D31:F2) ................. 48113.1.41 FLRCLV—FLR Capability Length and Version Register (SATA–D31:F2)......... 48113.1.42 FLRC—FLR Control Register (SATA–D31:F2) ........................................... 48113.1.43 ATC—APM Trapping Control Register (SATA–D31:F2) ............................... 48213.1.44 ATS—APM Trapping Status Register (SATA–D31:F2) ................................ 48213.1.45 SP—Scratch Pad Register (SATA–D31:F2) .............................................. 48213.1.46 BFCS—BIST FIS Control/Status Register (SATA–D31:F2).......................... 48213.1.47 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)....................... 48413.1.48 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)....................... 484

13.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 48513.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)......................... 48613.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) .............................. 48613.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F2) ............................................................................... 48713.2.4 AIR—AHCI Index Register (D31:F2)....................................................... 48713.2.5 AIDR—AHCI Index Data Register (D31:F2) ............................................. 488

13.3 Serial ATA Index/Data Pair Superset Registers .................................................... 48813.3.1 SINDX—Serial ATA Index Register (D31:F2) ........................................... 48813.3.2 SDATA—Serial ATA Data Register (D31:F2) ............................................ 489

13.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2)........................... 48913.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2).......................... 49013.3.2.3 PxSERR—Serial ATA Error Register (D31:F2) ............................ 491

13.4 AHCI Registers (D31:F2) .................................................................................. 49213.4.1 AHCI Generic Host Control Registers (D31:F2) ........................................ 493

13.4.1.1 CAP—Host Capabilities Register (D31:F2)................................. 49313.4.1.2 GHC—Global PCH Control Register (D31:F2) ............................. 49413.4.1.3 IS—Interrupt Status Register (D31:F2) .................................... 49513.4.1.4 PI—Ports Implemented Register (D31:F2) ................................ 49613.4.1.5 VS—AHCI Version Register (D31:F2) ....................................... 49713.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2) ..... 49713.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2) ..... 49713.4.1.8 CAP2—HBA Capabilities Extended Register ............................... 49813.4.1.9 RSTF—Intel® RST Feature Capabilities Register......................... 499

13.4.2 Port Registers (D31:F2) ....................................................................... 50013.4.2.1 PxCLB—Port [5:0] Command List Base Address Register

(D31:F2) ............................................................................. 50213.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper

32-Bits Register (D31:F2) ...................................................... 50313.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2)................ 50313.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits

Register (D31:F2) ................................................................. 50313.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2) .................. 50413.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2).................. 50513.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2) ....................... 50613.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) .................. 50813.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2)......................... 50913.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2)............ 50913.4.2.11 PxSCTL—Port [5:0] Serial ATA Control Register (D31:F2) ........... 51013.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2).............. 51113.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2) ............ 51213.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2).................. 513

Datasheet 15

14 SATA Controller Registers (D31:F5) .......................................................................51414.1 PCI Configuration Registers (SATA–D31:F5) ........................................................514

14.1.1 VID—Vendor Identification Register (SATA—D31:F5)................................51514.1.2 DID—Device Identification Register (SATA—D31:F5) ................................51514.1.3 PCICMD—PCI Command Register (SATA–D31:F5) ....................................51514.1.4 PCISTS—PCI Status Register (SATA–D31:F5) ..........................................51614.1.5 RID—Revision Identification Register (SATA—D31:F5) ..............................51714.1.6 PI—Programming Interface Register (SATA–D31:F5) ................................51714.1.7 SCC—Sub Class Code Register (SATA–D31:F5)........................................51714.1.8 BCC—Base Class Code Register

(SATA–D31:F5SATA–D31:F5)................................................................51814.1.9 PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F5) ......................................................................51814.1.10 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5)...................................................................................51814.1.11 SCMD_BAR—Secondary Command Block Base Address

Register (SATA D31:F5) .......................................................................51914.1.12 SCNL_BAR—Secondary Control Block Base Address

Register (SATA D31:F5) .......................................................................51914.1.13 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F5)...................................................................................51914.1.14 SIDPBA—SATA Index/Data Pair Base Address Register

(SATA–D31:F5)...................................................................................52014.1.15 SVID—Subsystem Vendor Identification Register

(SATA–D31:F5)...................................................................................52014.1.16 SID—Subsystem Identification Register (SATA–D31:F5) ...........................52014.1.17 CAP—Capabilities Pointer Register (SATA–D31:F5)...................................52014.1.18 INT_LN—Interrupt Line Register (SATA–D31:F5) .....................................52114.1.19 INT_PN—Interrupt Pin Register (SATA–D31:F5).......................................52114.1.20 IDE_TIM—IDE Timing Register (SATA–D31:F5)........................................52114.1.21 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5)...................................................................................52114.1.22 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F5)...................................................................................52214.1.23 IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F5)...................................................................................52214.

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