Integrating Power Models into Instruction Accurate …...Integrating Power Models into Instruction...
Transcript of Integrating Power Models into Instruction Accurate …...Integrating Power Models into Instruction...
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Integrating Power Models into Integrating Power Models into Instruction Accurate Virtual Instruction Accurate Virtual Platforms for ARMPlatforms for ARM--based based MPSoCsMPSoCsARM TechCon 201626 October 2016
R. Görgen2, D. Graham1, K. Grüttner2, L. Lapides1, S. Schreiner2
1Imperas, 2OFFIS
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
AgendaAgenda
Current state of embedded software development
Comparison of hardware-based and virtual platform-based methodologies
Instruction accurate software timing simulation
Power model with dynamic frequency and voltage scaling (DVFS) support
Case study: Simple power model for ARM Cortex-A9
Demo of case study
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
AgendaAgenda
Current state of embedded software development
Comparison of hardware-based and virtual platform-based methodologies
Instruction accurate software timing simulation
Power model with dynamic frequency and voltage scaling (DVFS) support
Case study: Simple power model for ARM Cortex-A9
Demo of case study
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Embedded Software Embedded Software Development IssuesDevelopment Issues(in no specific order)(in no specific order)
Schedule
Quality
Functionality
Timing, power constraints
Security / safety
Predictability of the software engineering task: management accuracy on software resource and schedule requirements is +/- 50%
Unknown / unmeasurable delivery risk
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The last two bullets are management issues, and their importance should not be underestimated.
Modern SoCs Have Many Concurrent Processing Elements
Renesas R-Car H2: Automotive infotainment and ADAS
AMP coresSMP cores Accelerators
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 5
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
SW Verification RequirementsSW Verification Requirements
Hardware Dependent Software (HDS) Most complex foundation layer
Drivers, hypervisors, assembly libraries, operating system
Buried problems often appear elsewhere in a system, leading to misdirected analysis
Ripe for corner case type issues Post development bugs hardest to fix Testing needs to be platform centric not
application centric
Modern SoC SW verification is complex SMP/AMP multicore interaction Shared memory & devices Extensive accelerators, peripherals Externally authored, complex libraries Complex SW/HW interaction (e.g. power)
How to estimate power consumption and test power management strategies over a wide range of conditions?
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Hardware-Based Software Development
Has timing/cycle accuracy JTAG-based debug, trace Traditional development board or hardware emulator based
testing Late to arrive Limited physical system availability Emulators are too slow to run enough system scenarios Limited external test access (controllability) Limited internal visibility
How to observe power consumption?
To get around these limitations, software is modified printf Debug versions of OS kernels Instrumentation for specific analytical tools, e.g. code
coverage, profiling
Modified software may not have the same behavior as clean source code
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 7
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
AgendaAgenda
Current state of embedded software development
Comparison of hardware-based and virtual platform-based methodologies
Instruction accurate software timing simulation
Power model with dynamic frequency and voltage scaling (DVFS) support
Case study: Simple power model for ARM Cortex-A9
Demo of case study
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Advantages of Virtual Platform Based Software Development(Instruction Accurate Simulation)
Test Set 1
Test Set n
Earlier system availability Easy access for entire team Runs actual binaries, e.g. runs ARM executables on x86 host Fast, enables quick turnaround and comprehensive testing Full controllability of platform both from external ports and internal nodes
Corner cases can be tested Errors can be made to happen
Full visibility into platform: if an error occurs, it will be observed by the test environment
Easy to replicate platform and test environment to support automated continuous integration (CI) and regression testing on compute farms
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 9
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Application Layer: Customer DifferentiationApplication Layer: Customer Differentiation
Middleware: TCP/IP, DHCP, LCD, …Middleware: TCP/IP, DHCP, LCD, …
OS: Linux, FreeRTOS, µC/OS-III, ThreadX, …OS: Linux, FreeRTOS, µC/OS-III, ThreadX, …
Virtual PlatformVirtual Platform
Drivers: USB, SPI, ethernet, …Drivers: USB, SPI, ethernet, …
Actual HardwareActual Hardware or
Virtual Platforms Complement Virtual Platforms Complement HardwareHardware--Based Software Based Software DevelopmentDevelopment Current methodology employs testing on hardware
Proven methodology
Has limitations
We are at the breaking point
Virtual platform based methodology delivers controllability, visibility, repeatability, automation
Virtual platforms – software simulation – provide a complementary technology to the current methodology
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The same software stack can run on either the actual hardware or the virtual platform. This enables users to add virtual platform technology to their existing flow with minimal changes/risk, and achieve the benefits of virtual platforms.
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
AgendaAgenda
Current state of embedded software development
Comparison of hardware-based and virtual platform-based methodologies
Instruction accurate software timing simulation
Power model with dynamic frequency and voltage scaling (DVFS) support
Case study: Simple power model for ARM Cortex-A9
Demo of case study
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Building the Virtual PlatformBuilding the Virtual Platform The virtual platform is a set of models that reflects the hardware on which the
software will execute Could be 1 SoC, multiple SoCs, board, system; no physical limitations Functionally accurate, such that the software does not know that it is not running on
the hardware Models are typically written in C or SystemC Models for individual components – interrupt controller, UART, ethernet, … –
are connected just like in the hardware Peripheral components can be connected to the real world by using the host
workstation resources: keyboard, mouse, screen, ethernet, USB, …
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SlipStreamer APISlipStreamer API
Imperas Tool Architecture
Application Software& Operating System
Application Software& Operating System
TESTBENCH
Virtual Platform
Memory
Peripheral
OVPCPU
BUS
OVPCPU
CPU
HELPER
VAP
TOOLS
OS
HELPER
TraceProfileCoverageSchedule…
Output Data
Just In Time (JIT) sim engineJust In Time (JIT) sim engine
Multiprocessor / Multicore Debugger
Eclipse IDE
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 13
The SlipStreamer™ API enables the building of non-intrusive tools in the simulation environment. These tools include tracing (instructions, C functions, OS tasks), profiling, code coverage, OS scheduler analysis, memory analysis, and more. The SlipStreamer API is made available to both Imperas engineers and Imperas users, so that custom tools can be developed, such as the power analysis tools discussed in this presentation.
Simulator / Tool / Model Architecture
Build environment elements separately Simulator engine uses Just In Time (JIT) binary translation (code
morphing) technology to efficiently translate instructions for the target processor to x86
SlipStreamer API enables tools to be built non-instrusively, i.e. no instrumentation or modification of software or operating systems
Models – processors, peripherals, platforms – are built using the Open Virtual Platforms (OVP) APIs
Software execution For single core processor in the virtual platform, a block (“quantum”) of
instructions, typically 1,000 – 100,000, is executed, then peripheral events are executed
For multicore processors, a quantum of instructions is executed in turn on each processor core; after each core has executed a quantum, theperipheral events are executed
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 14
Simultor / Tool / Model Flow Example
icmInit()
icmNewProcessor()
icmLoadProcessorMemory()
icmSimulatePlatform()
Platform Simulator ProcessorModel
Constructor
Configure
Load Model
Load Programto Memory
icmWriteReg(PC, 0x1000)
Code Dictionary
Create Translation for address
Code Available for Address?noyes
Run
Set PC Write Reg – vmirtSetPC()
End of Code Block
Constructor
InterceptLibrary
Intercept
Intercept
Morph Function (thisPC=0x1000)
Morph Function (thisPC=0x1004)
Morph Function (thisPC=0x100c)Get Next PC
yes no Morph Function (thisPC=0x1008)
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The intercept library, created using the SlipStreamer API, is compiled for the x86 host (not the embedded processor target) and linked into the simulation environment.
Timing Controls in Instruction Accurate Simulation
Instruction accurate simulation is not timing or cycle accurate, however …
The simulator and models have a sense of time Timing assumption is 1 cycle per instruction
Processor models have an assumed speed in MIPS (millions of instructions per second)
Processor speed can be changed during simulation
Quantum size can be changed during simulation, so that artificial waits before peripheral events are reduced
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 16
The ability to dynamically change processor speed will be utilized later in this presentation when we talk about power management using DVFS.
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
AgendaAgenda
Current state of embedded software development
Comparison of hardware-based and virtual platform-based methodologies
Instruction accurate software timing simulation
Power model with dynamic frequency and voltage scaling (DVFS) support
Case study: Simple power model for ARM Cortex-A9
Demo of case study
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Application,
Operating System,
Firmware
Scenarios/
Test-Cases
Stimulate
Timing & PowerMeasurement
Timing & Power
Constraints
Current Measurement Based Current Measurement Based Power AnalysisPower Analysis
Physical
Prototype
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 18
Need hardware board; expensive measurement equipment
How to obtain information about software power consumption?
State-of-the-art approach: Run application on development board and measure the power consumption in the laboratory (depending on the required measurement accuracy different (expensive) equipment is required)
Obtained power measurement results can be compared against the specified power constraints.
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Application,
Operating System,
Firmware
Scenarios/
Test-Cases
Stimulate
Runs on Physical
Prototype
Timing & PowerMeasurement
Virtual
Platform
Timing & Power
Constraints
Virtual Platform for Virtual Platform for Functional Software TestingFunctional Software Testing
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 19
With the availability of a virtual platform, the functional software testing can be performed without going down to the evaluation board.
This approach is well suited for functional software (and to some extent for timing) software testing, BUT
Power measurement still performed on evaluation board.
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Application,
Operating System,
Firmware
Power
Model
Scenarios/
Test-Cases
Stimulate
Physical
Prototype
TimingPowerTemp.Est./
Modeling
Timing & PowerMeasurement
Virtual
Platform
Timing & Power
Constraints
Runs on
Generating a Power Model Generating a Power Model for the Virtual Platformfor the Virtual Platform
Physical
Prototype
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 20
The first step power analysis with virtual platforms is the power model generation/extraction process from measurement trails on the evaluation board.
Different approaches exist (micro-benchmarks, machine-based learning, …) exist, but this is out of the scope of this presentation.
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Application,
Operating System,
Firmware
Analyze/Debug
Power
Model
Scenarios/
Test-Cases
Stimulate
Design-Time Opt.
Tracing
Physical
Prototype
Timing & PowerMeasurement
Virtual
Platform
Timing & Power
Constraints
Runs on
Design Time Power AnalysisDesign Time Power Analysis
Physical
Prototype
ARM TechCon© 2016 Imperas Software Ltd & OFFIS e.V.Page 21
After integration of the power model in the virtual platform (the following slides will show this), we can obtain
-Functional traces
-Timing traces
-AND (this is new) power traces over time
Depending on the spatial granularity of the power model, a hardware component power consumption breakdown can be supported.
Combining functional traces with component power traces, design time power optimization of the software can be performed.
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Application,
Operating System,
Firmware
Analyze/Debug
Power
Model
Scenarios/
Test-Cases
Stimulate
Design-Time Opt.
Tracing
PowerSensor
Run-Time Opt./Mgt.
Physical
Prototype
Timing & PowerMeasurement
Virtual
Platform
Timing & Power
Constraints
Runs on
RunRun--Time Power Time Power ManagementManagement
ARM TechCon© 2016 Imperas Software
Ltd & OFFIS e.V.Page 22
Since many software already performs power management (usually based on temperature sensing).
Instead of writing the power information into an analysis trace (as before), we can also feed it into a power sensor that can be mapped into the address space of the hardware platform and thus allow software access to derive power management decisions at run-time.
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SystemSystem--Level Power Model Level Power Model ParametersParameters
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Power
Model
Virtual
Platform
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Looking into the power model:
The applied power model has a hierarchical structure to represent different dies, power domains per die and different modules/functional hardware units per power domain.
The power consumption can be modeled at module level. It consists of:
-A dynamic part: depending on the actual usage of the component, expressed as average switched capacitance. The software dependent activity can be expressed as
- 1) Power State Machine (each state has a switched capacitance, transitions between states are triggered by the software or a power manager)
- 2) Annotation: Can be switched capacitance annotations in the processor model
- Our used power model is an annotation model. We are collection statistics during software execution (CPU load, number of memory read/writetransactions, …) and transform them into a switched capacitance equivalent that is multiplied with the supply voltage and clock frequency to obtain the power consumption (see next slides).
-A static part: depending on the leaking conductance (area and technology dependent)
The actual power for the dynamic and the static part depends on the switching activity and the dynamic parameters of the associated power domain:
-Supply voltage
-Clock frequency 23
SystemSystem--Level Power Model Level Power Model ParametersParameters
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Building blocks for flexible power model Static design parameters
Dynamic annotation/monitoring
Overall power consumption can be computed from static parameters and observations
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Overall power consumption P(t) based on:
-Dynamic part + static part
Important: All parameters can change over time:
-Vdd (supply voltage) can be changes by the software
-F (clock frequency) can be changed by the software
-C (average switched capacitance) is computed by a formula that takes different statistics during software execution (CPU load, number of memory read/write transactions, …) into consideration
-G(theta(t)) is not further taken into consideration. We assume a constanttemperature (e.g. guaranteed by a sufficient cooling system)
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Performance Counter Based Power Performance Counter Based Power Model for the Xilinx Model for the Xilinx ZynqZynq ARMARM--based based SystemSystem
Int nCores number of active cores [0-2]
double clk_cpu clock frequency of CPU in [Mhz]
double load_cpu load of processors [0-1]
double clk_mem clock frequency of memory in [Mhz]
double readrate_mem read rate of external DDR3 memory [0-1]
double writerate_mem write rate of external DDR3 memory [0-1]
double clk_axi AXI clock frequency in [Mhz]
double usage_axi usage rate of AXI interface [0-1]
int axi_bw bit width of AXI interface [32 or 64]
double clk_io clock frequency of IO in [Mhz]
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
double ps_dynpower_est(int nCores, double clk_cpu, double load_cpu, double clk_mem, double readrate_mem, double writerate_mem, double clk_axi, double usage_axi, int axi_bw, double clk_io)
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The function:
double ps_dynpower_est(int nCores, double clk_cpu, double load_cpu,
double clk_mem, double readrate_mem, doublewriterate_mem,
double clk_axi, double usage_axi, intaxi_bw,
double clk_io)
Replaces the dynamic power term of the equation above.
The leakage term is assumed to be only dependent on the supply voltage.
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Obtain Dynamic Parameters Obtain Dynamic Parameters From Virtual PlatformFrom Virtual Platform
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
double clk_cpu: clock frequency of CPU in [Mhz] vmirtAddWriteCallback (vmiProcessorP processor, Addr lowAddr, Addr highAddr,
vmirtMemWatchFn readC, Bvoid* userData ) : void
Monitor access to clock speed register interface
double load_cpu: load of processors [0-1] vmirtGetICount (vmiProcessorP processor ) : Uns64
Load: numer of non-empty instructions / (time interval * clk_cpu)
double readrate_mem: read rate of external DDR3 memory [0-1] vmirtAddReadCallback (vmiProcessorP processor, Addr lowAddr, Addr highAddr,
vmirtMemWatchFn readC, Bvoid* userData ) : void
Read rate: number of read instructions / (time interval * clk_axi)
double writerate_mem: write rate of external DDR3 memory [0-1] vmirtAddWriteCallback (vmiProcessorP processor, Addr lowAddr, Addr highAddr,
vmirtMemWatchFn readC, Bvoid* userData ) : void
Write rate: number of write instructions / (time interval * clk_axi)
double ps_dynpower_est(int nCores, double clk_cpu, double load_cpu, double clk_mem, double readrate_mem, double writerate_mem, double clk_axi, double usage_axi, int axi_bw, double clk_io)
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Shows how some of the parameters of the function
double ps_dynpower_est(int nCores, double clk_cpu, double load_cpu,
double clk_mem, double readrate_mem, doublewriterate_mem,
double clk_axi, double usage_axi, intaxi_bw,
double clk_io)
Are obtained through the OVP VP API.
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Performance Counter Based Power Performance Counter Based Power Model for the Xilinx Model for the Xilinx ZynqZynq ARMARM--based based SystemSystem
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
double ps_dynpower_est(int nCores, double clk_cpu, double load_cpu, double clk_mem, double readrate_mem, double writerate_mem, double clk_axi, double usage_axi, int axi_bw, double clk_io) {
P_Processor = VCCPINT / 1000.0 * (nCores * clk_cpu * load_cpu * 0.415 +(load_cpu<0.5 ? (0.5‐load_cpu)*nCores*clk_cpu*0.1515 : 0));
P_Processor_PLL = (((clk_cpu*2 > 0) ? 15.0 : 0) + clk_cpu*2*0.02)*VCCPAUX/1000.0;P_AXI = (VCCPINT/1000.0)*clk_axi*usage_axi*0.010417*axi_bw/8;P_Logic = P_Processor + P_Processor_PLL + P_AXI;...P_DDR = P_Memory + P_Memory_PLL;...P_Interfaces = P_USB + P_SD + 2*P_UART + P_I2C + P_SPI + 5*P_GPIO;...P_IO = P_Interfaces + P_Interfaces_PLL;P_total = P_Logic + P_DDR + P_IO;return P_total;
}
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This slide just shows the complex power function for the dynamic power consumption of the PS part of the Xilinx Zynq SoC.
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Timed Value Streams:Timed Value Streams:Power TracesPower Traces
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Application,
Operating System,
Firmware
Analyze/Debug
Design-Time Opt.
Virtual
Platform
Runs on
Power
Model
Tracing
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Timed Value Streams:Timed Value Streams:Power Monitoring in SWPower Monitoring in SW
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Application,
Operating System,
Firmware
Analyze/Debug
Design-Time Opt.
Virtual
Platform
Runs on
PowerSensor
Register Interface
Power
Consumption Power
Model
Tracing
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
AgendaAgenda
Current state of embedded software development
Comparison of hardware-based and virtual platform-based methodologies
Instruction accurate software timing simulation
Power model with dynamic frequency and voltage scaling (DVFS) support
Case study: Simple power model for ARM Cortex-A9
Demo of case study
Page 30
ARM CortexARM Cortex--A9 A9 Power Model OverviewPower Model Overview
© 2016 Imperas Software Ltd & OFFIS e.V.Page 31 ARM TechCon
ARMCortex™-A9MPx2
UART0
Timer0
SRAM
SystemManager
L2 Cache Controller
UART1
Ethernet
DMA
Timer1
Timer2
Timer3
Reset Controller
Imperas SmartLoader
Intercept Library
Power Model
Int.Lib.
Power Model
Core Model Platform Model
Platform AccessMemory, Registers, Voltages, etc.
Power Formulas
VCDSink
Clock Rates(CPU, RAM, AXI, IO)and Voltages
Utilizations(CPU, RAM R/W, AXI)
Power Values
File Output
I²C (PMBUS)
Voltage Regulatorsand Power Sensors
Timed Value Streams
Platform Callbacks and Intercepts
This slide shows an overview of the Power Model and the Zynq ARM Dual Core Platform
The Power Model is instantiated in the intercept library, it accesses the platform information via defined memory callbacks and I²C intercepts are used for transmitting new voltage parameters or returning power values.
The power model has 4 main parts which communicate via Timed Value Streams:
-The Platform model is responsible for recognizing all platform values, like frequencies and voltages, as well as the intercepted I²C communication with the Voltage Regulators and Power Sensors
-Both Cores have one Core Model. It is responsible to calculate all Core specific data, like CPU utilization (with vmirtGetExecutedICount and vmirtGetICount), Memory Read and Write rates and AXI Load (both with memory read and write callbacks). All calculations for the utilizations are called periodicaly by a defined Model Timer
-The Power Formulas calculate all power streams for CPU, Memory, AXI, IO, Leakage, etc.
-The VCD Sink writes all traces and data to a trace file
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Executing Linux in VP with Executing Linux in VP with Attached Power ModelAttached Power Model
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Virtual Platform (VP) executes Linux and Power Model recognizes changes: Core frequencies are reconfigured to 333MHz
RAM frequency is configured to 533MHz
Power Model reconfigures MIPS rate of both cores
Core Frequencies
RAM Frequency
Linux Console and Simulator output
The platform is able to boot Linux with the Power Model attached. In the screenshots you the reconfiguration of the core frequencies and the RAM frequency. Since the frequency of the Cores is reduced from 667MHz to 333MHz, also the MIPS rate in the platform is degrated from 667MIPS to 333MIPS with a factor of 50.075
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Executing Linux in VP with Executing Linux in VP with Attached Power ModelAttached Power Model
© 2016 Imperas Software Ltd & OFFIS e.V.Page 33 ARM TechCon
Exported VCD Power Traces0s 250s
idleexecute 3 applicationschange dirsboot Linux
Power Traces in W
CPU0
CPU1
CPU Total
Memory
AXI
IO
Leakage
Total
VCC_PINT
VCC_PAUX
VCC_DDR
This Slide presents all exported power Traces that are written to the VCD file
I booted Linux, switched to the directory „/benchmarks/“ and executed 3 instances of peakSpeed1.exe
Next to the power traces the following data is also written to the VCD file:
Group Power:
-CPU0
-CPU1
-CPU Total
-Memory
-AXI
-IO
-Leakage
-Total Power
-VCC_PINT
-VCC_PAUX
-VCC_DDR
Group Frequency:
-CPU
-Memory
AXI33
DVFS Bare Metal ExampleDVFS Bare Metal Example
Application Binary is executed bare metal on ARM cores
Switch frequencies and voltages for: ARM cores
DDR memory
Power Model recognizes changes
© 2016 Imperas Software Ltd & OFFIS e.V.Page 34 ARM TechCon
VCD Traces of DVFS example
Power CPU Total
Power Memory
Power AXI
Power Leakage
Power Total
Voltage PINT
Voltage DDR
Load CPU 0
Load Mem Read
Load Mem Write
Load AXI
The DVFS Bare Metal Example executes the following:
While(1)
{
// First state
scaleFrequency(DDR_CLK_CTRL, DDR_CLK_533_MHZ);
scaleFrequency(ARM_CLK_CTRL, PS_CLK_667_MHZ);
scaleVoltage(VCCPINT_DEVICE, VCCPINT_PAGE, 1.0);
scaleVoltage(VCCPAUX_DEVICE, VCCPAUX_PAGE, 1.8);
scaleVoltage(VCC1V5_PS_DEVICE, VCC1V5_PS_PAGE, 1.5); //VCC_DDR
// Go throuh the changes
for(i = 0; i < 15000000; i++); // wait
readMeasurementsTI(); // read virtual sensor
for(i = 0; i < 5000000; i++); // wait
scaleVoltage(VCCPINT_DEVICE, VCCPINT_PAGE, 0.9);
for(i = 0; i < 5000000; i++); // wait
readMeasurementsTI(); // read virtual sensor
for(i = 0; i < 5000000; i++); // wait
scaleFrequency(ARM_CLK_CTRL, PS_CLK_333_MHZ);
for(i = 0; i < 5000000; i++); // wait
dM t TI() // d i t l34
Virtual Power SensorVirtual Power Sensor
Power Sensor is represented by an intercepted I²C interface
Power Model getsnew voltage valuesand returns power values
That means: Next to the frequency configuration the application is able to configure the voltages and to request the present power values
© 2016 Imperas Software Ltd & OFFIS e.V.Page 35 ARM TechCon
ARMCortex™-A9MPx2
UART0
Timer0
SRAM
SystemManager
L2 Cache Controller
UART1
Ethernet
DMA
Timer1
Timer2
Timer3
Reset Controller
Imperas SmartLoader
Semihosting Library
Power Model
Semi.Lib.
VCD File
I²C (PMBUS)
Voltage Regulatorsand Power Sensors
The executed application is able to request the current power values over an intercepted I²C communication from the power model. The communication protocolis nearly the same as of the TI chips located at the Zynq zc702 board.
As well as the application is able to reconfigure the frequncies of the cores and the DDR memory via the original register interface, there is the ability to configure also the voltages VCC_PINT, VCC_PAUX and VCC_DDR over the intercepted I²C communication.
In that way the platform and the power model fully supports DVFS.
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Power Monitors in ActionPower Monitors in Action
Bare Metal DVFS example is executed in VP
VP Power Model intercepts I²C communication of Virtual Power Sensor Executed application is able to read power information
Values can be used in applications
Example: UART output of executed application: Simple read and print out of power values
© 2016 Imperas Software Ltd & OFFIS e.V.Page 36 ARM TechCon
The DVFS Bare Metal Example requests the power values (present voltages and currents) over the intercepted I²C communication and prints all grabbed information for the 3 power domains in its UART interface.
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
AgendaAgenda
Current state of embedded software development
Comparison of hardware-based and virtual platform-based methodologies
Instruction accurate software timing simulation
Power model with dynamic frequency and voltage scaling (DVFS) support
Case study: Simple power model for ARM Cortex-A9
Demo of case study
Page 37
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
DemoDemo
Booting Linux
DVFS on the ARM Cortex-A9
Power monitor in action
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Video Demo of Zynq Platform with attached Power Model
1) Linux Demo:- Initialization: Power Model Init Outputs, Streams and other Models are initialized. Power Model outputs of Linux Booting Phase.
See the new derate factor that is set to 50.075 since the Frequency switches from 667MHz to 333MHz, as well as setting the DDR frequency to 533MHz.
The output sequence is the full Linux boot-up until the login comes.-
After it the same is shown with the uart1 output, here I login as root, switch the directory and execute two times the same peakSpeed benchmark-
Next I show the outputs of the power model again. First one task is already running (~0.8W) then the other one is started (~1.2W)-
As last I show the VCD Trace in the Viewer (impulse [http://toem.de/index.php/projects/impulse]). You see the boot phase at the beginning, in the power and utilization traces, as well as the execution of the two benchmarks (2 steps) in the power traces.
2) DVFS Demo:- Initialization: Power Model Init Outputs, Streams and other Models are initialized.
Power Model outputs are shown later again, here only for 2 seconds.
-Power Monitor: Application configures new frequencies and voltages, reads back voltages and currents to calculate power consumption on its own.
-Power Model Output: You see next to the core loads all switching activity of the frequencies and the voltages, as well as the readbacks (... Addr: 52, ...) of the currents. The procedure is described in the slide comments
-Power Model VCD Output: Here you see the swtiching activity in all traces.
© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
SummarySummary
Virtual platforms – software simulation – provide a complementary technology to hardware-based testing of software
Besides functional correctness, timing properties and power consumption are gaining importance
Virtual platforms with a power model can help to Test power management for low power or temperature sensitive
systems and thus contribute to Achieve higher quality software
Reduce development schedules
Increase software project predictability
Reduce delivery risk
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© 2016 Imperas Software Ltd & OFFIS e.V. ARM TechCon
Thank youThank you
This work was partially funded by the European Union’s Horizon2020 research and innovation programmeunder the grant agreement No 687902.
More information at http://www.safepower-project.eu/
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