1.0V

1.8V

1.5V

3.3V

INVERTINGREGULATOR

BOOSTREGULATOR

ADP5070

6A BUCK

2.5A BUCK

2.5A BUCK

SWITCH/MUX

AMP/FILTERANALOG

INPUT

ADC

6A BUCK

5V/12VADP5054

XILINX®/ALTERA®

FPGA

+15V

–15V

Integrated Power Management Solutions

Analog Devices Announces a New Family of Multichannel Regulators

analog.com/power

ADP5050/ADP5051/ADP5052/ADP5053

Quad Buck Switching Regulator with LDO or POR/WDI in LFCSP

12V/5VINPUT

PWRGD

1.2V

2.5V

1.8V

3.3V

1.5V

OPTIONALI2C

4A BUCK REG1

1.2A BUCK REG

1.2A BUCK REG

4A BUCK REG1

200mA LDO

ADP5050/ADP5052

1.0V

2.5V

1.8V

3.3V

4A BUCK REG1

1.2A BUCK REG

1.2A BUCK REG

4A BUCK REG1

POWER-ON,RESET, ANDWATCHDOG

12V/5VINPUT

ADP5051/ADP5053

PWRGD

MRWDI

VTHR

RESET

OPTIONALI2C

Key Features

• Wide input voltage range: 4.5 V to 15 V

• ±1.5% output accuracy over full temperature range

• 250 kHz to 1.4 MHz adjustable switching frequency

• Adjustable/fixed output options via factory

• Pseudo DVS (dynamic voltage scaling)

• I2C interface with interrupt supportive on fault condition

• CH1/CH2: programmable 1.2 A/2.5 A/4 A sync buck regulator with low-side FET driver

• CH3/CH4: 1.2 A sync buck regulator

• CH5: 200 mA low dropout LDO or watchdog timer and power-on reset

• Precision enable on 0.8 V accurate threshold

• Active output discharge switch

• FPWM/PSM mode selection

• Frequency synchronization input or output

• Power-good flag on selective channels

• Startup with the precharged output

• 7 mm × 7 mm, 48-lead LFCSP package

• −40°C to +125°C junction temperature

• I2C functionality

1 Resistor programmable current limit (4 A, 2.5 A, or 1.2 A).

EN4

ALWAYS ON 5V LDO

VOUT1

VOUT2VOUT2

PVIN1 TO PVIN4VIN = 4.5VTO 15V

VOUT3

nINT

SCL

SDA

VOUT4

VOUT5

PWRGD

ADP5050

PVIN5

EN5

EN3

EN2

EN1

VCORE

VDDIO

VAUX

PROCESSOR/FPGA

ANALOG

MEM

INT

SCL

SDA

ADP505x IC

28.3mm × 21.2mm

TIME TIME

12V INPUT VOLTAGE 10.2V(ADJUSTABLE)

INTERRUPT

JUNCTION TEMPERATURE

115˚(ADJUSTABLE)

INTERRUPT

TIME TIME

12V INPUT VOLTAGE 10.2V(ADJUSTABLE)

INTERRUPT

JUNCTION TEMPERATURE

115˚(ADJUSTABLE)

INTERRUPT

Option 1: Resistor-programmable output voltage from 0.8 V to VIN ∙ 0.85

Option 2: Fixed output voltage with I2C programmability with these ranges for each channel

[CH1: 0.85 V TO 1.60 V, 25 mV STEP]

[CH2: 3.3 V TO 5.0 V, ~300 mV STEP]

[CH3: 1.2 V TO 1.80 V, 100 mV STEP]

[CH4: 2.5 V TO 5.5 V, 100 mV STEP]

I2C Functionality

ADP5050 application diagram featuring the I2C interface.

ADP505x output voltage options.

ADP505x solution size only 28.3 mm × 21.2 mm.

Low input voltage detection on PVIN1. Overheat function on junction temperature.

2 | Integrated Power Management Solutions

PWRGD

ADP5054

2.5A BUCKREGULATOR

2.5A BUCKREGULATOR

6A BUCKREGULATOR

6A BUCK REGULATOR

FPGAFET

s

DDRTERM. LDO

DDR3MEMORY

FLASHMEMORY

1.2V/6A COREVOLTAGE

AUXILIARYVOLTAGE

VCCINT

VCCAUX

VCCO_0, 1, 2

VCC0_3

2.5V/4A

1.5V/2A

0.75V

3.3V/1.2A

4.5V TO 15.5VINPUT VOLTAGE

I/Os

I/Os

BANK 0BANK 1BANK 2

BANK 3

ADP5054

Quad Buck Switching Regulator in LFCSP

Power for FPGA Applications Example

Part Number Number of Outputs VIN (V) VOUT (V) Max Output

Current (A)Switching Frequency

Range I2C Reset Trip Threshold (V)

Min Reset Timeout (ms)

Typ Watchdog Timeout (ms) Package Price 1k List

($U.S.)

ADP5050

2 × 4 A1 bucks 4.5 to 15

0.8 to 0.85 × VIN 1.2/2.5/41

250 kHz to 1.4 MHzYes — — — 48-lead LFCSP 4.392 × 1.2 A bucks 0.8 to 0.85 × VIN 1.2

1 × 200 mA LDO 1.7 to 5.5 0.5 to 4.75 200 mA —

ADP50512 × 4 A1 bucks

4.5 to 150.8 to 0.85 × VIN 1.2/2.5/41

250 kHz to 1.4 MHz Yes 0.5 (adj) 1, 20, 140, 1120 6.3, 102, 1600, 25,600 48-lead LFCSP 4.59

2 × 1.2 A bucks 0.8 to 0.85 × VIN 1.2

ADP5052

2 × 4 A1 bucks 4.5 to 15

0.8 to 0.85 × VIN 1.2/2.5/41

250 kHz to 1.4 MHz— — — — 48-lead LFCSP 3.592 × 1.2 A bucks 0.8 to 0.85 × VIN 1.2

1 × 200 mA LDO 1.7 to 5.5 0.5 to 4.75 200 mA —

ADP50532 × 4 A1 bucks

4.5 to 150.8 to 0.85 × VIN 1.2/2.5/41

250 kHz to 1.4 MHz — 0.5 (adj) 1, 20, 140, 1120 6.3, 102, 1600, 25,600 48-lead LFCSP 3.79

2 × 1.2 A bucks 0.8 to 0.85 × VIN 1.2

ADP50542 × 6 A2 bucks

4.5 to 15.50.8 to 0.85 × VIN 6/4/22

250 kHz to 2 MHz — — — — 48-lead LFCSP 4.292 × 2.5 A bucks 0.8 to 0.85 × VIN 2.5

1 Resistor-programmable current limit (4 A, 2.5 A, or 1.2 A). 2 Resistor-programmable current limit (6 A, 4 A, or 2 A).

0.8V TO 0.85 × VIN @ 6A

0.8V TO 0.85 × VIN @ 6A

0.8V TO 0.85 × VIN @ 2.5A

0.8V TO 0.85 × VIN @ 2.5A

PWGRD

6A BUCK REG*

2.5A BUCK REG

2.5A BUCK REG

6A BUCK REG*

VIN4.5V TO 15.5V

ADP5054

Key Features

• CH1/CH2: programmable 2 A/4 A/6 A sync buck regulator with low-side FET driver

• Parallel CH1/CH2 to deliver up to 12 A output

• CH3/CH4: 2.5 A buck regulator

• Parallel CH3/CH4 to deliver up to 5 A output

• Wide input range: 4.5 V to 15.5 V

• Resistor adjustable or fixed output voltage

• 250 kHz ∙ 2 MHz adjustable switching frequency

• 1/2 × fSW selective for each channel

• Precision enable on accurate 0.8 V threshold

• Programmable current limit in CH1/CH2

• Soft start timer programmable

• FPWM/PSM mode selection

• Active output discharge switch

• PWRGD flag on selective channels

• Frequency synchronization input or output

• Hiccup or latch-off for output short protection

• UVLO, OCP, TSD

• 7 mm × 7 mm, 48-lead LFCSP package

*Resistor-programmable current limit (6 A, 4 A, 2 A).

analog.com/power | 3

OFFON

OFFON

RFB1

RFT1

RFT2

D2

COUT2

COUT1

CVREFCIN1

CVREG

CC1 RC1

CC2 RC2

VNEG(−12V, −15V,−18V)

VIN

D1VPOS

(+12V, +15V,+18V)

L2

L1

INBK

SW1

FB1

PGND

VREF

FB2

SW2SS

COMP1

COMP2

VREG

PVIN1

PVIN2

PVINSYS

EN2

EN1

SYNC/FREQ

SLEW

SEQ AGND

RFB2

BOOSTREGULATOR

ADP5070/ADP5071

INVERTINGREGULATOR

BOOSTREGULATOR

INVERTINGREGULATOR

OFFON

OFFON

RFB1RFT1

RFT2

D2

COUT2

COUT1

CVREF

C8

CIN1

CVREG

CC1 RC1

CC2 RC2−5V

VIN: 12VVOUT_1: +5VVOUT_2: −5V

VIN =12V

D1

+5V

STANDALONE ORCOUPLED INDUCTOR

L3

L2

L1

INBK

SW1

FB1

PGND

VREF

FB2

SW2

SS

COMP1

COMP2

VREG

PVINSYS

EN2

EN1

SYNC/FREQ

SLEW

SEQ AGND

RFB2

ADP5070SEPIC BUCK

AND RECEIVER

BOOSTREGULATOR

INVERTINGREGULATOR

PVIN1

PVIN2

ADP5070/ADP5071

Dual Switching Regulator for Generating VPOS and VNEG in LFCSP and TSSOP

ADP5070/ADP5071 Demo BoardSEPIC Configuration to Support Automatic Step-Up/Down Capability

Key Features:

• Wide input voltage range: 2.85 V to 15 V

• Generates well regulated, independently resistor-program-mable VPOS and VNEG outputs (for example, +15 V and −10 V)

• True shutdown for both positive and negative outputs

• 1.2 MHz/2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to 2.6 MHz

• Resistor-programmable soft start timer

• Individual precision enable and flexible start-up sequence control for symmetric start, VPOS first, or VNEG first

• Boost and inverter, out of phase operation (180°)

• UVLO, OCP, OVP, and TSD protection

• Slew rate control for lower system noise

• 4 mm × 4 mm, 20-lead LFCSP or TSSOP-EP package

• −40°C to +125°C junction temperature

• Supported by ADIsimPower tool set

Boost Regulator—Positive Rail

• Adjustable positive output: up to +39 V

• Integrated 1.0 A/39 V main switch (ADP5070)

• Integrated 2.0 A/39 V main switch (ADP5071)

• Optional SEPIC configuration for automatic step-up/down

Inverter Regulator—Negative Rail

• Adjustable negative output: up to −39 V below VIN

• Integrated 0.6 A/39 V main switch (ADP5070)

• Integrated 1.2 A/39 V main switch (ADP5071)

• RESISTOR-PROGRAMMABLE (SYMMETRIC AND ASYMMETRIC)

• EXAMPLE OUTPUTS SUPPORTED: ±3V, ±5V, ±12V, ±10V, +15V, AND −10V

• APPLICATIONS: BIPOLAR AMPLIFIERS, ANALOG-TO-DIGITAL CONVERTERS AND DIGITAL-TO-ANALOG CONVERTERS, MULTIPLEXERS, AMPLIFIERS, CCDS AND OLEDS, RF PA BIAS SUPPLY, GaN FET BIAS, AND OPTICAL MODULES

• RESISTOR-PROGRAMMABLE (SYMMETRIC AND ASYMMETRIC)

• EXAMPLE OUTPUTS SUPPORTED: ±5V, ±3.5V, +3.3V, AND −2.5V

http://download.analog.com/PMP/ADP507x_designer.zip

Part Number VIN (V) VOUT (V) Number of Outputs Output Current (mA) Key Features Package Price ($U.S.)

ADP5070 New Boost/inverter: 2.85 to 15

Boost: VIN to 39 1 × boost Input current limit: boost: 1 A, inverter: 0.6 A

Individual enable pin, adjustable outputs, soft start, and slew rate

20-lead LFCSP, 20-lead TSSOP 2.19

Inverter: –0.5 to –39 below VIN 1 × inverter

ADP5071 New Boost/inverter: 2.85 to 15

Boost: VIN to 39 1 × boost Input current limit: boost: 2 A, inverter: 1.2 A

Individual enable pin, adjustable outputs, soft start, and slew rate

20-lead LFCSP, 20-lead TSSOP 2.39

Inverter: –0.5 to –39 below VIN 1 × inverter

4 | Integrated Power Management Solutions

ADP5135 and ADP5133

ADP5135: Triple, 1.8 A, 3 MHz Buck Regulator in LFCSP

ADP5133: Dual 800 mA Buck Regulator in WLCSP

Key Features

• Main input voltage range 3.0 V to 5.5 V

• Three 1800 mA buck regulators

• 4 mm × 4 mm, 24-lead LFCSP package

• Regulator accuracy of ±1.8%

• Individual, dedicated buck power good pins

• Precision enables pins for easier power sequencing

• 3 MHz buck operation with forced PWM and automatic PWM/PSM modes

• Buck output voltage range from 0.8 V to 3.8 V

Applications

• Power for processors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and radio frequency (RF) chipsets

Key Features

• Input voltage range: 2.3 V to 5.5 V

• Two 800 mA buck regulators

• Adjustable and factory-programmable output voltages

• Adjustable output voltage range: 0.8 V to 3.8 V

• Fixed output voltage range: 0.9 V to 3.3 V

• Regulator accuracy: ±1.8%

• Overcurrent and thermal protection

• Soft start and undervoltage lockout

• Buck 1 and Buck 2 key specifications

• Current mode architecture for excellent transient response and 100% duty operation

• 3 MHz operating frequency

• Forced PWM and auto PWM/PSM modes

• Out of phase operation for reduced input filtering

• −40°C to +125°C junction temperature

• Tiny, 2 mm × 2 mm, 16-ball WLCSP package

C14.7�F

C24.7�F

VIN1

EN1

2.3V TO 5.5VSW1

VCORE

VCORE

VIO

VIO

GPIO

FB1

FB2

VOUT1

PGND1

MODE

C310�F

L1 1�H

L2 1�H

800mABUCK 1

VIN2

SW2

AGND

PGND2

C410�F

800mABUCK 2

EN2ON

OFF

ON

OFF

ADP5133PROCESSOR/FPGA

VOUT2

R3

R4

R1

R2

L1 1�H

C222�F

PGND1

PGND3

PG1

PG2

PG3

FB1

SW1VIO

VCORE

GPOx

GPIx

MODE

FPGA

VMEM

VIN2

VIN1

C110�F

EN1

VDDIO

1.8ABUCK 1

1.8ABUCK 2

1.8ABUCK 3

C310�F

C510�F

VDDIO/ TO VEN2

3.0V TO 5.5V

AGND

EN2

VOUT1

R1

R2

VIN3

AVIN

AGNDC7

0.1�F

L2 1�H

C422�F

PGND2

FB2

SW2

VEN3VOUT2

R3

R4

L3 1�HSW3

C622�F

FB3

VOUT3

R5

R6

R7 R8 R9

ADP5135

EN3

POWERGOOD

HOUSE-KEEPING

ON

OFF

ON

OFF

ON

OFF

AUTOFPWM

D1PGND1

10�F0402

10�F0402

2.5V

4.5mm × 5.5mm = 24.8mm2mm

mm0.5

0.5

1.0

1.0

1.5

1.5

2.0

2.0

2.5

2.5

3.0

3.0

3.5

3.5

4.0

4.0

4.5

4.5

5.0

5.0

5.5

4.7�F0402

L1

4.7�F0402

D4PGND2

B1AGND

D2SW1

D3SW2

C3VOUT2

C4VIN2

C1VIN1

A2AGND

A3AGND

A4FB2

A1FB1

B3EN1

B2MODE

B4EN2

C2VOUT1

L2 -

1�

H06

03

GPL

GPL

GPLGPL

PPL

PPL

GPL

GPL GPL

analog.com/power | 5

Key Features

• Main input voltage range 2.5 V to 5.5 V

• Two 1200 mA buck regulators and two 300 mA LDO regulators

• 4 mm × 4 mm, 24-lead LFCSP package

• Regulator accuracy of ±1.8%

• Factory-programmable or external adjustable VOUTx

• Precision enables pins for easier power sequencing

• Factory selectable power-good pin

• 3 MHz buck operation with forced PWM and automatic PWM/PSM modes

• Buck 1/Buck 2: output voltage range from 0.8 V to 3.8 V

• LDO1/LDO2: output voltage range of 0.8 V to 5.2 V

• LDO1/LDO2: input voltage range from 1.7 V to 5.5 V

• LDO1/LDO2: high PSRR and low output noise

Applications

• Power for processors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and radio frequency (RF) chipsets

Assumptions

• Power good factory programmed to sense all regulators

Benefits

• Precise and reliable

• Few external components needed

• Minimal cost adder (resistors)

• Flexible sequencing

PG

VOUT1

VOUT4

VOUT3

VOUT2

VOUT5

VIN

VP1 VP1

VP2 VP2

VP3 VP3

VDD

VPO RR

VPO RF

UVLOR UVLOF

+VINVIN1

VIN2

VIN3

VIN4

VINVOUT5

VOUT1

VOUT2

VOUT3

VOUT4

EN1ON/OFF

EN2

EN3

EN

VP1PG

VP3

VP2

VDD

GPIN

EN4

ADP5134

FPGASPARTAN 3×CYCLONE IIICYCLONE IV

BUCK 1

BUCK 2

REG5(EXT)

MEMORY

LDO1

LDO2

L1 1�H

C210�F

PGND1

PG

FB1

SW1VIO

VCORE

GPOx

GPIx

MODE

PROCESSOR/FPGA

VAUX

VMEM

VIN2

VIN1

C14.7�F

EN1

VDDIO

C34.7�F

VDDIOVIN2.5V TO 5.5V

AGND

VOUT1

R1

R2

EN2

C50.1�F

AVIN

VIN3

C61�F

VINLDO11.7V TO 5.5V

L2 1�H

C410�F

PGND2

FB2

SW2

VOUT2

R3

R4

C71�F

FB3

VOUT3

R5

R6

R1100k�

C91�F

FB4

VOUT4

R7

R8

ADP5134

EN3

VIN4

C81�F

VINLDO21.7V TO 5.5V

EN4

POWERGOOD

LDO1300mA

LDO2300mA

1.2ABUCK 1

1.2ABUCK 2

HOUSE-KEEPING

ON

OFF

ON

OFF

ON

OFF

ON

OFF

AUTOFPWM

Sequencing and Power Good with ADP5134

ADP5134

Dual, 3 MHz, 1.2 A Buck Regulator with Two 300 mA LDOs with Precision Enable and a Power Good in LFCSP

6 | Integrated Power Management Solutions

ADP5040 and ADP5041

ADP5040: 1.2 A Buck and Dual 300 mA LDO with Individual Enables in LFCSP

ADP5041: 1.2 A Buck and Dual 300 mA LDO, Supervisory, Watchdog, and Manual Reset in LFCSP

ADP5040 functional block diagram. ADP5041 functional block diagram.

L1 1�H

C610�F

PGND

FB1

SW

MODE

ADP5040

VIN1

VIN2

C11�F

EN1

1.2ABUCKC5

10�F

C31�F

VIIN3

VIN2: 1.7VTO 5.5V

AGND

EN2OFF

ON

PSM/PWMFPWM

OFFON

VIN3: 1.7VTO 5.5V

VOUT1

R1

R2

300mALDO2

300mALDO1

AVIN

VIN1: 2.3VTO 5.5V

VOUT1@ 1.2A

VOUT2 @ 300mA

VOUT3 @ 300mA

EN3OFF

ON

C22.2�F

FB2

VOUT2

R3

R4

C42.2�F

FB4 R5

R6

L1 1�H

C610�F

PGND

FB1

SW

MODE

ADP5041

VIN1

VIN2

C11�F

EN1

1.2ABUCKC5

10�F

C31�F

VIN3

VIN2: 1.7VTO 5.5V

AGND

EN2OFF

ON

PSM/PWMFPWM

OFFON

VIN3: 1.7VTO 5.5V

VOUT1

R1

R2

300mALDO2

SU

PE

RV

ISO

R

EN_LD01

300mALDO1

AVIN

VIN1: 2.3VTO 5.5V

VOUT1@ 1.2A

VOUT2@ 300mA

VOUT3 @ 300mA

EN3OFF

ON

C22.2�F

MICRO-PROCESSOR

FB2

VOUT2

R3

R4

C42.2�F

FB4

VOUT3

R7

R8

VTHR

WDI

nRSTO

R5

R6

MR

Key Features

• Input voltage range: 2.3 V to 5.5 V

• One 1.2 A buck regulator, fixed and adjustable output voltages, up to 96% efficiency

• Two 300 mA LDOs, fixed and adjustable outputs

• 4 mm × 4 mm, 20-lead LFCSP package

• Initial regulator accuracy: ±1%

• Overcurrent and thermal protection

• Soft start

• Undervoltage lockout

• Open-drain processor reset with external adjustable threshold monitoring

• ±1.5% threshold accuracy over the full temperature range

• Guaranteed reset output valid to VCC = 1 V

• Manual reset input

• Watchdog refresh input

• Two reset timeout options: 20 ms and 140 ms (minimum)

• Two watchdog timeout options: 102 ms and 1600 ms (typical)

Assumptions

ADP2311VIN1

VIO

VCORE

GPIO

ASIC/PROCESSOR

GPIO

INT

RST

VIN2

BUCK 1 SW1 3.3V

1.2VSW2

WDI

nRSTO

POR

PFO

BUCK 2

PFI

4.5V to 18V

WATCHDOG

VOLTAGE MONITOR

FPGA

ADP2311

Dual, 1 A Buck Regulators with Fail-Safe Monitoring

Key Features

• Input voltage: 4.5 V to 18 V

• Continuous output current: 1 A/1 A

• Output accuracy: ±1.0%

• Power fail comparator gener-ates warning

• Power-on reset with program-mable delay timer

• Adjustable voltage monitor for power-down (Channel 2)

• Watchdog refresh input

• Fixed switching frequency: 300 kHz

• Internal compensation and soft start

• Precision enable inputs

• Power feedback during power-off

• UVLO, OCP, OVP, and thermal shutdown protection

• 4 mm × 4 mm, 24-lead LFCSP package

Applications

• Industrial and instrumentation

• Healthcare and medical

• DC-to-DC point of load applications

analog.com/power | 7

Inte

grat

ed P

ower

Man

agem

ent S

olut

ions

( Mic

ro-P

MUs

)

Part

Num

ber

Prod

uct D

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iptio

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N (V)

V OUT

( V)

Num

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f Ou

tput

sOu

tput

Cu

rren

t (m

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Rese

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Th

resh

old

( V)

Min

Res

et

Tim

eout

( ms)

Typ

Wat

chdo

g Ti

meo

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s)Ke

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atur

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( $U.

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ADP5

022

Dual

, 3 M

Hz b

uck

w

ith 1

50 m

A LD

O

Buck

: 2.3

to 5

.5

Buck

: 3.3

, 3.0

, 2.8

, 2.5

, 2.3

, 2.0

, 1.8

2, 1

.8, 1

.6, 1

.5, 1

.3, 1

.2, 1

.1, 1

.0, 0

.9, 0

.8

2 ×

buc

k60

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——

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ode

pin,

indi

vidu

al

 ena

ble

pins

16-b

all W

LCSP

1.80

LD

O: 1

.7 to

5.5

LDO:

3.3

, 3.0

, 2.9

, 2.8

, 2.7

75, 2

.5, 2

.0, 1

.875

, 1.8

, 1.7

5,

1.7,

1.6

5, 1

.6, 1

.55,

1.5

, 1.2

1 ×

LDO

150

ADP5

023

Dual

, 800

mA

buck

w

ith 3

00 m

A LD

OBu

ck: 2

.3 to

5.5

Adj (

0.8

to 3

.8)

2 ×

buc

k80

0—

——

—M

ode

pin,

indi

vidu

al

enab

le p

ins

24-le

ad L

FCSP

1.59

LDO:

1.7

to 5

.5Ad

j (0.

8 to

5.2

)1

× L

DO30

0

ADP5

024

Dual

, 1.2

A b

uck

w

ith 3

00 m

A LD

OBu

ck: 2

.3 to

5.5

Adj (

0.8

to 3

.8)

2 ×

buc

k12

00—

——

—M

ode

pin,

indi

vidu

al

enab

le p

ins

24-le

ad L

FCSP

1.79

LDO:

1.7

to 5

.5Ad

j (0.

8 to

5.2

)1

× L

DO30

0

ADP5

033

Dual

, 3 M

Hz b

uck

 re

gula

tor w

ith d

ual L

DOBu

ck: 2

.3 to

5.5

Bu

ck: 3

.3, 3

.0, 2

.8, 2

.5, 2

.3, 2

.0, 1

.8, 1

.6, 1

.5, 1

.4, 1

.3, 1

.2, 1

.1, 1

.0, 0

.92

× b

uck

800

——

——

Mod

e pi

n, tw

o en

able

pin

s16

-bal

l WLC

SP1.

90LD

O: 1

.7 to

5.5

LDO:

3.3

, 3.0

, 2.8

, 2.5

, 2.2

5, 2

.0, 1

.8, 1

.7, 1

.6, 1

.5, 1

.2, 1

.1, 1

.0, 0

.9, 0

.82

× L

DO30

0

ADP5

034

Dual

, 3 M

Hz b

uck

regu

lato

r w

ith d

ual L

DOBu

ck: 2

.3 to

5.5

Adj (

0.8

to 3

.8)

2 ×

buc

k12

00—

——

—M

ode

pin,

indi

vidu

al

enab

le p

ins

24-le

ad L

FCSP

,1.

99LD

O: 1

.7 to

5.5

Adj (

0.8

to 5

.2)

2 ×

LDO

300

28-le

ad T

SSOP

ADP5

133 New

Dual

, 3 M

Hz b

uck

regu

lato

rBu

ck: 2

.3 to

5.5

Adj (

0.8

to 3

.8) o

r 3.3

, 3.0

, 2.8

, 2.5

, 2.3

, 2.0

, 1.8

, 1.6

, 1.5

, 1

.4, 1

.3, 1

.2, 1

.1, 1

.0, 0

.92

× b

uck

800

——

——

Adju

stab

le a

nd fi

xed

outp

uts

16-b

all W

LCSP

1.29

ADP5

134 New

Dual

, 3 M

Hz b

uck

regu

lato

r w

ith d

ual L

DOBu

ck: 2

.5 to

5.5

Adj (

0.8

to 3

.8)

2 ×

buc

k12

00—

——

—Pr

ecis

ion

enab

le p

ins

an

d po

wer

-goo

d pi

n24

-lead

LFC

SP2.

09LD

O: 1

.7 to

5.5

Adj (

0.8

to 5

.2)

2 ×

LDO

300

ADP5

135 New

Trip

le, 3

MHz

buc

k re

gula

tor

Buck

: 3.0

to 5

.5Ad

j (0.

8 to

3.8

)3

× b

uck

1800

——

——

Prec

isio

n en

able

pin

s an

d po

wer

-goo

d pi

ns24

-lead

LFC

SP1.

69

ADP5

037

Dual

, 3 M

Hz, 8

00 m

A bu

ck

regu

lato

r with

dua

l 300

m

A LD

O

Buck

: 2.3

to 5

.5Ad

j (0.

8 to

3.8

)2

× b

uck

800

——

——

Mod

e pi

n, in

divi

dual

en

able

pin

s24

-lead

LFC

SP1.

69LD

O: 1

.7 to

5.5

Adj (

0.8

to 5

.2)

2 ×

LDO

300

ADP5

040

3 M

Hz b

uck

regu

lato

r  w

ith d

ual L

DOBu

ck: 2

.3 to

5.5

Ad

j (0.

8 to

3.8

)1

× b

uck

1200

——

——

Indi

vidu

al e

nabl

e pi

ns,

mod

e pi

n20

-lead

LFC

SP1.

39LD

O: 1

.7 to

5.5

Adj (

0.8

to 5

.2)

2 ×

LDO

300

ADP5

041

3 M

Hz b

uck

regu

lato

r with

du

al L

DO, s

uper

viso

r, an

d w

atch

dog

timer

Buck

: 2.3

to 5

.5Ad

j (0.

8 to

3.8

)1

× b

uck

1200

—0.

5 ( a

dj)

20, 1

4010

2, 1

600

Indi

vidu

al e

nabl

e pi

ns

and

supe

rvis

or, W

DI,

mod

e pi

n, a

nd M

R pi

n20

-lead

LFC

SP1.

79LD

O: 1

.7 to

5.5

Adj (

0.8

to 5

.2)

2 ×

LDO

300

ADP5

070 New

Dual

dc-

to-d

c w

ith b

oost

an

d in

verte

r out

puts

for

gene

ratin

g V P

OS a

nd V

NEG

Boos

t/inv

erte

r: 2.

85 to

15

Boos

t: V I

N to

39

1 ×

boo

stIn

put c

urre

nt

limit:

boo

st: 1

A

inve

rter:

0.6

A—

——

—In

divi

dual

ena

ble

pin,

ad

just

able

out

puts

, sof

t sta

rt,

and

slew

rate

20-le

ad L

FCSP

, 20

-lead

TSS

OP2.

19In

verte

r: –0

.5 to

–39

bel

ow V

IN1

× in

verte

r

ADP5

071 New

Dual

dc-

to-d

c w

ith b

oost

an

d in

verte

r out

puts

for

gene

ratin

g V P

OS a

nd V

NEG

Boos

t/inv

erte

r: 2.

85 to

15

Boos

t: V I

N to

39

1 ×

boo

stIn

put c

urre

nt

limit:

boo

st: 2

A

inve

rter:

1.2

A—

——

—In

divi

dual

ena

ble

pin,

ad

just

able

out

puts

, sof

t sta

rt,

and

slew

rate

20-le

ad L

FCSP

, 20

-lead

TSS

OP2.

39In

verte

r: –0

.5 to

–39

bel

ow V

IN1

× in

verte

r

ADP5

073 New

Inve

rting

sw

itchi

ng re

gula

tor

for g

ener

atin

g V N

EG

Inve

rter:

2.

85 to

15

Inve

rter:

–0.5

to –

39 b

elow

VIN

1 ×

inve

rter

Inve

rter:

1.2

A—

——

—En

able

pin

, adj

usta

ble

outp

ut,

soft

star

t, an

d sl

ew ra

te16

-lead

LFC

SP1.

49

ADP5

074 New

Inve

rting

sw

itchi

ng re

gula

tor

for g

ener

atin

g V N

EG

Inve

rter:

2.

85 to

15

Inve

rter:

–0.5

to –

39 b

elow

VIN

1 ×

inve

rter

Inve

rter:

2.4

A—

——

—En

able

pin

, adj

usta

ble

outp

ut,

soft

star

t, an

d sl

ew ra

te16

-lead

LFC

SP1.

75

ADP5

075 New

Inve

rting

sw

itchi

ng re

gula

tor

for g

ener

atin

g V N

EG

Inve

rter:

2.

85 to

15

Inve

rter:

–0.5

to –

39 b

elow

VIN

1 ×

inve

rter

Inve

rter:

0.6

A—

——

—En

able

pin

, adj

usta

ble

outp

ut,

soft

star

t, an

d sl

ew ra

te12

-bal

l WLC

SP0.

99

ADP5

050 New

Quad

buc

k re

gula

tor

with

LDO

with

I2C

Buck

: 4.5

to 1

50.

8 to

0.8

5 ×

VIN

2 ×

buc

k40

001

Yes

——

—I2 C

inte

rface

with

indi

vidu

al

enab

le p

ins

and

pow

er g

ood

48-le

ad L

FCSP

4.39

2 ×

buc

k12

00

LDO:

1.7

to 5

.50.

5 to

4.7

51

× L

DO20

0

ADP5

051 New

Quad

buc

k re

gula

tor,

POR,

an

d W

DI w

ith I2

CBu

ck: 4

.5 to

15

0.8

to 0

.85

× V

IN2

× b

uck

4000

1

Yes

0.5

( adj

)1,

20,

140

, 11

206.

3, 1

02, 1

600,

25

,600

I2 C in

terfa

ce w

ith in

divi

dual

en

able

pin

s an

d po

wer

goo

d48

-lead

LFC

SP4.

592

× b

uck

1200

ADP5

052 New

Quad

buc

k re

gula

tor w

ith L

DOBu

ck: 4

.5 to

15

0.8

to 0

.85

× V

IN2

× b

uck

4000

1

——

——

Indi

vidu

al e

nabl

e pi

ns

with

pow

er g

ood

48-le

ad L

FCSP

3.59

2 ×

buc

k12

00

LDO:

1.7

to 5

.50.

5 to

4.7

51

× L

DO20

0

ADP5

053 New

Quad

buc

k re

gula

tor

with

POR

and

WDI

Buck

: 4.5

to 1

50.

8 to

0.8

5 ×

VIN

2 ×

buc

k40

001

—0.

5 ( a

dj)

1, 2

0, 1

40,

1120

6.3,

102

, 160

0,

25,6

00In

divi

dual

ena

ble

pins

w

ith p

ower

goo

d48

-lead

LFC

SP3.

792

× b

uck

1200

ADP5

054 New

Quad

buc

k re

gula

tor

Buck

: 4.5

to 1

5.5

0.8

to 0

.85

× V

IN2

× b

uck

6000

2

——

——

Indi

vidu

al e

nabl

e pi

ns

with

pow

er g

ood

48-le

ad L

FCSP

4.29

2 ×

buc

k25

00

ADP2

311 New

Dual

1 A

buc

k4.

5 to

18

Adj,

( 0.6

to 0

.85

× V

IN)

2 ×

buc

k10

00—

0.95

× V

FBAd

j50

, 100

,150

, 20

0PF

O, P

FI, W

DI24

-lead

LFC

SP2.

38

1 Res

isto

r-pr

ogra

mm

able

cur

rent

lim

it ( 4

A, 2

.5 A

, or 1

.2 A

) . 2 R

esis

tor-

prog

ram

mab

le c

urre

nt li

mit

( 6 A

, 4 A

, or 2

A) .

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