Integrated Converter Topology with ZVS for Power Factor ... · Integrated Converter Topology with...

IJSRD - International Journal for Scientific Research & Development| Vol. 4, Issue 04, 2016 | ISSN (online): 2321-0613

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Integrated Converter Topology with ZVS for Power Factor Correction Anitha1 Dr.B V Sumangala2

1M.Tech Student 2Professor & HOD 2Department of Electrical & Electronic Engineering 1,2Dr.Ambedkar Institute of Technology, Bengaluru

Abstract— This project proposes an integrated Boost-Buck

converter to correct power factor at the front end of the AC-

DC converter module. Circuit topology integrates boost and

buck converter. Power factor correction is taken care by

boost converter and DC output regulation is taken care by

buck converter. With this proposed topology zero voltage

transition is made in the circuit naturally without use of any

auxiliary circuit or switch. MATLAB software is used to

carry out the simulation work. A low voltage prototype is

done for testing the performance in the open loop.

Key words: Boost converter, buck converter, Discontinuous

Conduction Mode (DCM), Zero-Voltage Switching (ZVS),

Power Factor Correction (PFC)

I. INTRODUCTION

There are numerous ways to make almost sinusoidal line

current. Boost or buck-boost converter has simple circuit

and control which are extensively used for improving power

factor [1]. To reach unity power factor, both converters

voltage at the output side must be greater than magnitude of

the ac line voltage. Accordingly, AC-DC converter consists

of two-phases to get high power factor. First Phase power

factor correction and second phase supplying stable DC

output voltage to load [2-3]. The disadvantage of this two-

phase it takes power conversion approaches which simply

introduces few losses which encompass switching losses,

conduction losses and magnetic core loss.

Sepic and cuk converters also do power factor

correction and stabilizes DC output [4-5].Cuk and sepic

converter are the combination of boost and buck converter,

both these converters have simple circuit topology which

includes only a diode and active switch. The drawback of

using these converters are excessive switching losses and

high spike current this is because of energy stored in the

parasitic capacitor discharges. By synchronous rectification

technique the cuk and sepic converters are made to operate

in critical conduction mode (CRM), timing of the switches

has to be adjusted in this technique using additional circuit

which is a disadvantage [6].

Many single stage AC-DC converters are designed

by recent researchers. The single stage methodologies that

associate PWM converter moreover have a few drawbacks

which restrict further improving the circuit performance.

Drawback of this converter is hard switching operation of

the switches which causes high current and voltage stress on

components of the circuit, high switching losses this result

in the poor efficiency and circuit balance [7-8].

This paper proposes a new circuit topology that

consists of integrated boost-buck converter along with the

zero voltage switching for correcting power factor at the

front end of AC-DC converter which decreases switching

losses, high current and voltage stress.

II. CIRCUIT CONFIGURATION AND OPERATION MODES

For solving hard Switching problem, a new ac/dc converter

is proposed, as shown in Fig. 1.The proposed circuit mainly

consists of a diode-bridge rectifier (D1- D4), low-pass filter

(Lm and Cm), a boost converter and a buck converter.

MOSFETs S1 and S2 play the roles of active switches and

the antiparallel diodes DS1 and DS2 are their intrinsic body

diodes, respectively. The boost converter is composed of Lp,

DS1, S2 and Cdc and the buck converter is composed of Lb, D5,

DS2, S1 and Co. Both converters operate at a high-switching

frequency, fs. The boost converter corrects the power factor.

Low pass filter removes high frequency current components

of inductor current. By this way, the boost converter can

wave shape the input line current and input voltage to be in

sinusoidal and in phase. The buck converter regulates the

output voltage of the boost converter to supply stable dc

voltage. For achieving ZVS buck converter designed to

operate at DCM. To prevent cross conducting of the

switches dead time is provided. Neglecting the short dead

time, the duty cycle of vGS1 and vGS2 is 0.5.

Fig. 1: Proposed AC-DC converter

For simplifying the circuit analysis, the following

assumptions are made:

1) The semiconductor devices are ideal except for the

MOSFETs parasitic output capacitance

2) The capacitances of Cdc and Co are large enough

that the dc-link voltage Vdc and the output voltage

Vo can be regarded as constant.

The circuit operation can be divided into eight modes in

every cycle.

MODE 1: Mode 1 starts when the switch S1 is

made to turn off by gate voltage, VGS1. Buck inductor

current ib deviates from S1 to flow through the output

capacitance. Correspondingly Capacitance CDS1 and CDS2 are

charged and discharged. Boost inductor current starts to

increase, when the rectified input voltage Vrec is more than

the voltage VDS2 .The moment VDS2 reaches -0.7V, DS2 turns

on and at this stage mode 1 ends.

Integrated Converter Topology with ZVS for Power Factor Correction

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MODE 2: VDS2 is maintained about -0.7V by anti-

parallel diode at beginning of the mode 2. S2 is made to turn

on by the gate voltage VGS2. If S2 on-resistance is small

enough, majority of ib current flows through S2 from source

to drain path. Lb and Lp voltages are equal to

𝑣𝑏(𝑡) = −𝑉𝑜 (1)

𝑣𝑝(𝑡) = 𝑣𝑟𝑒𝑐(𝑡) = 𝑉𝑚| sin(2𝜋𝑓𝐿𝑡)| (2)

Time interval of mode 1 is short ib can be expressed as

𝑖𝑏(𝑡) = 𝑖𝑏(𝑡𝑜) −𝑉𝑜

𝐿𝑝(𝑡 − 𝑡𝑜) (3)

From equation (3) ib reduces from crest value.

Boost converter is designed such that it operates in DCM ip

increases from 0-Vrec.

𝑖𝑝(𝑡) =𝑉𝑟𝑒𝑐

𝐿𝑝(𝑡 − 𝑡𝑜) =

𝑉𝑚|sin(2𝜋𝑓𝐿𝑡)|

𝐿𝑝(𝑡 − 𝑡𝑜) (4)

Current ib has two loops, part of which flows

through S2 and remaining to ip. Mode 2 ends when ip rises

more than ib.

MODE 3: In this mode, ip > ib. current ip has two

loops, part of which flows through buck converter while rest

of current to switch S2. The direction of current changes

from drain to source naturally. Current ib decreases

continuously on the other side ip increases. ib reduces to zero

at the end of this mode.

MODE 4: In this mode the S2 switch is ON which

carries current ip. The buck converter is off because ib is zero

and output capacitor supplies load current. Mode 4 ends

when switch S2 is made to turn off by gate voltage VGS2.

MODE 5: At the instant of turning off of S2,

current ip reaches crest value. Boost inductor current flows

through the CDS1 and CDS2 instead of switch S2.At onset of

this mode ib is zero, and will start to increase when CDS1

voltage decreases than Vdc-Vo.Mode 5 ends when DS1 turns

on.

MODE 6: VDS1 Voltage is maintained to -0.7V at

onset of mode 6 by the diode DS1 connected antiparallel.

After the short overlap time the switch S1 is turned on. If S1

switch on-resistance is small enough, almost ip current

courses through S1 from source to drain way. LP and Lb can

be expressed as

𝑉𝑝(𝑡) = 𝑉𝑟𝑒𝑐(𝑡) − 𝑉𝑑𝑐 = 𝑉𝑚|sin(2𝜋𝑓𝐿𝑡)| − 𝑉𝑑𝑐 (5)

Vb (t) = Vdc -Vo (6)

Neglecting short dead time

𝑖𝑝(𝑡) = 𝑖𝑝(𝑡4) −𝑉𝑚| sin(2𝜋𝑓𝐿𝑡)|−𝑉𝑑𝑐

𝐿𝑝(𝑡 − 𝑡4) (7)

𝑖𝑏(𝑡) =𝑉𝑑𝑐−𝑉𝑜

𝐿𝑝(𝑡 − 𝑡4) (8)

ip has two current loops,. Part of ip flows through

switch 1 and rest to buck converter. Mode 6 ends when ib

rises more than ip.

MODE 7: ib is greater than the ip during

mode7.There are two current loops for ib, Part of which

flows through the boost converter and rest to switch S1.The

direction of current changes naturally from drain to source.

ip decreases continuously while ib increases. As soon as ip

reduces to zero mode ends.

MODE 8: Ib keeps increasing as S1 remains ON.

This mode ends when VGS1 becomes lower level to turn off

switch S1.operating circuit enters into mode 1 in the next

high frequency cycle.

Fig. 2: Mode 1

Fig. 3: Mode 2

Fig. 4: Mode3

Fig. 5: Mode 4

Fig. 6: Mode 5




Fig. 7: Mode 6

Fig. 8: Mode 7

Fig. 9: Mode 8

Fig. 10: Theoretical waveforms of the proposed converter

III. DESIGN PROCEDURE

Table I lists the circuit specifications. The input voltage is

230Vrms ± 10%. The switching frequency is 50 kHz at rated

power operation. In this design example, both converters are

designed to operate at DCM. The circuit parameters are

designed as follows:

Calculation of design parameter

Vpeak = Vrms ∗ √2 = 230 ∗ √2 = 325V

The dc link voltage is given by

𝑉𝑑𝑐 ≥ 2 ∗ 𝑉𝑚 , 𝑉𝑑𝑐 ≤ 2 ∗ 𝑉𝑜

𝑉𝑑𝑐 ≥ 2 ∗ 325 = 650 , 𝑉𝑑𝑐 ≤ 2 ∗ 450 = 900

Vdc chosen is 750V

K= 𝑉𝑑𝑐

𝑉𝑚=

750

325= 2.3

Boost inductor value is obtained as

𝐿𝑝 = ƞ∗𝑉𝑚

2

8∗𝑃𝑜∗𝑓𝑠[

𝐾3

√𝑘2−1(1 +

2

𝜋sin−1 1

𝑘) − 𝑘2 −

2

𝜋𝑘]

=0.95∗3252

8∗60∗50∗1000[

2.33

√2.32−1(1 +

2

𝜋sin−1 1

2.3) − 2.32 −

2

𝜋∗ 2.3]

𝐿𝑝 = 3.35𝑚𝐻

Buck inductor value found to be

𝐿𝑏 = (𝑉𝑑𝑐−𝑉𝑜)

8∗𝑃𝑜∗𝑓𝑠=

(750−450)∗750

8∗450∗0.13∗50∗1000= 9.39𝑚𝐻

Low pass filter at input side is taken as

𝐶 𝑖𝑠 𝑐ℎ𝑜𝑜𝑠𝑒𝑛 𝑎𝑠 0.47𝑢𝐹 𝑠𝑜 𝐿𝑚 = 2.16𝑚𝐻

𝑅 =𝑉

𝐼=

450

0.13= 3461 𝑜ℎ𝑚

Input voltage 230Vrms,50Hz

Boost inductor Lp=3.35mH

Buck inductor Lb=9.39mH

DC link capacitor Cdc=100𝜇𝐹

Load capacitor Co=100𝜇𝐹

Load resistor Ro=3461ohms

Switching frequency fs=50kHz

Table 1: Circuit Specification




IV. SIMULATION RESULTS

Simulation work is carried out using MATLAB/Simulink

software. The input voltage is 230V ac and output voltage is

450V dc with power factor correction to 0.998.

Fig. 11: Simulink model of proposed circuit

Closed loop operation of the proposed circuit is

carried out to maintain the output voltage of the load to be

constant for power reducing from 60W to 1W

Fig. 12: Simulink model of closed loop control of proposed circuit




Fig. 13: Waveforms of VDS1, iS1, VDS2, iS2

Fig. 14: Output current io =0.13A

Fig. 15: Output voltage V0=450V

Fig. 16: Dc link voltage Vdc =750V

Fig. 17: THD of 230 open loop system

Fig. 18: Inductor current of Boost and Buck

Fig. 20: Power factor of closed loop 230,50Hz system

Fig. 21: THD of 230v, 50Hz closed loop

V. HARDWARE IMPLEMENTATION

Time (sec)

Time (sec)

Time (sec)

Dc

link

volt

age

Vd

c(volt

s)




Fig. 22: Block diagram of hardware

Driver circuit is connected to pin 1.1 and 1.2 of

microcontroller board (AT89C51) 8051, driver circuit

provides gate signals to the switches as shown in Fig.13.60V

ac supply is provided to diode bridge rectifier which

converters ac to dc and buck converter provides a regulated

dc output voltage.

Components used in driver circuit:

1) Diode IN4007

2) Capacitors 1000𝜇𝐹/50𝑉,1000𝜇𝐹/25𝑉

3) Opto coupler MCT2E

4) Transistors 2N2222,SK100

5) Resistors 1k and 100 ohm

6) Transformer 230/12V

Fig. 23: Hardware of 60V, 50Hz

Fig. 24: Switching pulse

Fig. 25: Output voltage Vo =74V

Fig. 26: Dc link voltage Vdc=92V

VI. CONCLUSION

With the proposed converter topology the front end AC-DC

converter power factor is made near to unity i.e. 0.99.The

topology integrates boost and buck converter. Boost

converter used to improve power factor and buck converter

maintains regulated output voltage .using this new topology

the zero voltage switching is achieved without use of any

additional circuits. Closed loop operation is done in

simulation so that the output voltage is maintained constant




from 60W to 1W. Simulation results show that the THD is

improved in the closed loop compared with open loop. The

results of simulation are practical tested by developing a low

voltage of 60V prototype.

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[6] J. W. Yang and H. L. Do, “High-efficiency ZVS AC-

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