Tahira K. Hira, Professor Executive Assistant to the President tkhira@iastate
Instructor: Dr. Phillip Jones (phjones@iastate) Reconfigurable Computing Laboratory
description
Transcript of Instructor: Dr. Phillip Jones (phjones@iastate) Reconfigurable Computing Laboratory
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1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
CPRE 583Reconfigurable Computing
Lecture 3: Wed 9/2/2009(Reconfigurable Computing Architectures,
VHDL Overview 3)
Instructor: Dr. Phillip Jones([email protected])
Reconfigurable Computing LaboratoryIowa State University
Ames, Iowa, USA
http://class.ece.iastate.edu/cpre583/
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2 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
• Reinforce some common questions
• Finish Chapter 1 Lecture
• Continue Chapter 2
• VHDL review
Overview
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3 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
• How does an FPGA work?
• How does VHDL execute on an FPGA?
• How many LUT on the classes FPGA? 44,000
• State machines will be cover more next lecture
• Final Project group selection: choose your own groups
• Class machine resources– Coover 2048, 1212; Coover 2041 ML507 (will be 2)– Distance students xilinx.ece.iastate.edu (other servers on the way)
Common Questions
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4 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
• Basic trade-offs associated with different aspects of a Reconfigurable Architecture. (Chapter 2)
• Practice with timing diagrams, start state machines
What you should learn
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5 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Reconfigurable Architectures
• Main Idea Chapter 2’s author wants to convey– Applications often have one or more small
computationally intense regions of code (kernels)
– Can these kernels be sped up using dedicated hardware?
– Different kernels have different needs. How does a kernels requirements guide design decisions when implementing a Reconfigurable Architecture?
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6 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Reconfigurable Architectures• Forces that drive a Reconfigurable Architecture
– Price• Mass production 100K to millions• Experimental 1 to 10’s
– Granularity of reconfiguration• Fine grain• Course Grain
– Degree of system integration/coupling• Tightly• Loosely
All are a function of the application that will run on the Architecture
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7 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Example Points in (Price,Granularity,Coupling) Space
Price
$100’s
$1M’s
Granularity
Coarse
Fine
CouplingLoose Tight
Intel /AMD
Int
float
RFU
Processor
PC
ML507
Ethernet
Decode
Exec
Store
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8 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
What’s the point of a Reconfigurable Architecture
• Performance metrics– Computational
• Throughput• Latency
– Power• Total power dissipation• Thermal
– Reliability• Recovery from faults
Increase application performance!
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9 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Typical Approach for Increasing Performance
• Application/algorithm implemented in software– Often easier to write an application in software
• Profile application (e.g. gprof)– Determine where the application is spending its time
• Identify kernels of interest– e.g. application spends 90% of its time in function
matrix_multiply()• Design custom hardware/instruction to accelerate kernel(s)
– Analysis to kernel to determine how to extract fine/coarse grain parallelism (does any parallelism even exist?)
Amdahl’s Law!
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10 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Amdahl’s Law: Example• Application My_app
– Running time: 100 seconds– Spends 90 seconds in matrix_mul()
• What is the maximum possible speed up of My_app if I place matrix_mul() in hardware?
• What if the original My_app spends 99 seconds in matrx_mul()?
10 seconds = 10x faster
1 seconds = 100x faster
Good recent FPGA paper that illustrates increasing an algorithm’s performance with Hardware
“NOVEL FPGA BASED HAAR CLASSIFIER FACE DETECTION ALGORITHM ACCELERATION”, FPL 2008
http://class.ece.iastate.edu/cpre583/papers/Shih-Lien_Lu_FPL2008.pdf
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11 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Reconfigurable Architectures• RPF -> VIC (short slide)
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12 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity
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13 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Coarse Grain
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
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14 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Coarse Grain
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
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15 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Coarse Grain
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
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16 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Fine Grain
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
Configurable Logic Block
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17 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Fine Grain
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
Configurable Logic Block
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18 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Fine Grain
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB
CLB
CLB
CLB CLB CLB CLB
Configurable Logic Block
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19 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUTMicroprocessor
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20 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUTMicroprocessor
4
3
3
AB
op3
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21 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUTMicroprocessor
4
3
3
AB
op3
4
3
3AB
op3
4
3
3
AB
op3
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22 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUTMicroprocessor
4
3
3
AB
op
3
4
3
3AB
op
3
3
3
3
AB
op
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23 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUTMicroprocessor
4
3
3
AB
op
3
4
3
3AB
op
3
4
3
3
AB
op
3
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24 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUT
Bit logic and constants
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25 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUT
Bit logic and constants
(A and “1100”) or (B or “1000”)
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26 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUT
Bit logic and constants
(A and “1100”) or (B or “1000”)
A
B
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27 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Trade-offsTrade-offs associated with LUT size
Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits
1024-bits
2-LUT
10-LUT
Bit logic and constants
(A and “1100”) or (B or “1000”)
A AND
OR
OR
1
0
B
4
4
It’s much worse, each 10-LUT only has one output
Area that wasrequired using
2-LUTS
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28 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: Example Architectures
• Fine grain: GARP
• Course grain: PipeRench
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29 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: GARP
CPU RFU
Garp chip
Memory
I-cache D-cache
Configcache
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30 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: GARP
CPU RFU
Garp chip
Memory
I-cache D-cache
Configcache
RFUcontrol
(1)Execution(16, 2-bit)
N
PE (Processing Element)
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31 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: GARP
CPU RFU
Garp chip
Memory
I-cache D-cache
Configcache
RFUcontrol
(1)Execution(16, 2-bit)
N
PE (Processing Element)Example computations in one cycleA<<10 | (b&c)(A-2*b+c)
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32 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: GARP
CPU RFU
Garp chip
Memory
I-cache D-cache
Configcache
Impact of configuration size• 1 GHz bus frequency•128-bit memory bus• 512Kbits of configuration size
On a RFU context switch how longto load a new full configuration?
4 microseconds
An estimate of amount of time for theCPU perform a context switch is ~5 microseconds
~2x increase context switch latency!!
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33 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: GARP
CPU RFU
Garp chip
Memory
I-cache D-cache
Configcache
RFUcontrol
(1)Execution(16, 2-bit)
N
PE (Processing Element)
“The Garp Architecture and C Compiler”http://www.cs.cmu.edu/~tcal/IEEE-Computer-Garp.pdf
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34 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench • Coarse granularity
• Higher (higher) level programming
• Reference papers• PipeRench: A Coprocessor for Streaming Multimedia Acceleration
(ISCA 1999): http://www.cs.cmu.edu/~mihaib/research/isca99.pdf• PipeRench Implementation of the Instruction Path Coprocessor
(Micro 2000): http://class.ee.iastate.edu/cpre583/papers/piperench_Micro_2000.pdf
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35 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
Interconnect
8-bit ALU
Reg file
PE8-bit ALU
Reg file
PE8-bit ALU
Reg file
PE
Interconnect
8-bit ALU
Reg file
PE8-bit ALU
Reg file
PE8-bit ALU
Reg file
PE
8-bit ALU
Reg file
PE8-bit ALU
Reg file
PE8-bit ALU
Reg file
PE
Glo
bal b
us
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36 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
3
4
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37 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
0
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
3
4
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38 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
0
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
3
4
0
1
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39 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
0
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
3
4
0
1
0
1
2
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40 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
0
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
3
4
0
1
0
1
2
1
2
3
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41 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
0
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
3
4
0
1
0
1
2
1
2
3
2
3
4
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42 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
0
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
3
4
0
1
0
1
2
1
2
3
2
3
4
0
3
4
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43 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
0
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
3
4
0
1
0
1
2
1
2
3
2
3
4
0
3
4
Cycle
Pipelinestage
1 2 3 4 5 6
0
1
2
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44 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
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45 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
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46 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
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47 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
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48 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
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49 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
PE PE PEPE
PE PE PEPE
PE PE PEPE
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Pipelinestage
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50 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Degree of Integration/Coupling • Independent Reconfigurable Coprocessor
– Reconfigurable Fabric does not have direct communication with the CPU
• Processor + Reconfigurable Processing Fabric– Loosely coupled on the same chip– Tightly coupled on the same chip
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51 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Degree of Integration/Coupling M
ain M
emory
CPU
Fe
tch
De
code
Execute Me
mory
Write
Back
L1 Cache
L2 Cache
MemoryController
DMAController
I/OController
USB PCI PCI-Express SATA
Hard DriveNIC
ALU
FPU
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52 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Degree of Integration/Coupling M
ain M
emory
CPU
Fe
tch
De
code
Execute Me
mory
Write
Back
L1 Cache
L2 Cache
MemoryController
DMAController
I/OController
USB PCI PCI-Express SATA
Hard DriveNIC
ALU
FPU
RPF
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53 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Degree of Integration/Coupling M
ain M
emory
CPU
Fe
tch
De
code
Execute Me
mory
Write
Back
L1 Cache
L2 Cache
MemoryController
DMAController
I/OController
USB PCI PCI-Express SATA
Hard DriveNIC
ALU
FPURPF
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54 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Degree of Integration/Coupling M
ain M
emory
CPU
Fe
tch
De
code
Execute Me
mory
Write
Back
L1 Cache
L2 Cache
MemoryController
DMAController
I/OController
USB PCI PCI-Express SATA
Hard DriveNIC
ALU
FPU
RPF
ConfigI/F
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55 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Degree of Integration/Coupling M
ain M
emory
CPU
Fe
tch
De
code
Execute Me
mory
Write
Back
L1 Cache
L2 Cache
MemoryController
DMAController
I/OController
USB PCI PCI-Express SATA
Hard DriveNIC
ALU
FPU
RPF
ConfigI/F
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56 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Degree of Integration/Coupling M
ain M
emory
CPU
Fe
tch
De
code
Execute Me
mory
Write
Back
L1 Cache
L2 Cache
MemoryController
DMAController
I/OController
USB PCI PCI-Express SATA
Hard DriveNIC
ALU
FPU
RPFI/O
ConfigI/F
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57 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Degree of Integration/Coupling M
ain M
emory
CPU
Fe
tch
De
code
Execute Me
mory
Write
Back
L1 Cache
L2 Cache
MemoryController
DMAController
I/OController
USB PCI PCI-Express SATA
Hard DriveNIC
ALU
FPURFU
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58 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
MP2
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
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59 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
MP2
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
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60 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
MP2
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
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61 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
MP2 Notes• MUCH less VHDL coding than MP1
• But you will be writing most of the VHDL from scratch
• The focus will be more on learning to read a specification (Power PC coprocessor interface protocol), and designing hardware that follows that protocol.
• You will be dealing with some pointer intensive C-code. It’s a small amount of C code, but somewhat challenging to get the pointer math right.
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62 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Lecture 3 notes / slides in progress
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63 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: PipeRench
• Scheduling virtual stage on to physical• Partial/Dynamically reconfig (each cycle)
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64 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Granularity: GARP
• Impact of configuration size on performance• Context switching
• Garp feature• Dynamic reconfigurable• Store multiple configurations in an on chip
cache (4)• One configuration at a time
• Example app mapping to GARP (loop)• Amdahl's Law
The Garp Architecture and C Compiler• http://www.cs.cmu.edu/~tcal/IEEE-Computer-Garp.pdf
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65 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)
Overview• Dimensions
– Price– Granularity– Coupling– To optimize App Performance (compute (throughput, latency),
Power, reliability)• RPF to efficiently implement VICs
– Main picture authors' wants to convey• What’s the point or having a Reconfigure arch
– Example (Increase App performance)• App -> SW/CPU• Profile• ID kernels of intense compute• Design custom hardware/instruction (Amdels law)
– Intel FPL paper, great example for reading by Friday