Instruction Processing

7/27/2019 Instruction Processing

1/23

LC-3 Instruction ProcessingTextbook chapter 4

CMPE 12 Summer 2008

CMPE12 Summer 2008 Slides by ADB 2

Phases of Instruction Processing

Decode instructionDecode instruction

Evaluate addressEvaluate address

Fetch operands from memoryFetch operands from memory

Execute operationExecute operation

Store resultStore result

Fetch instruction from memoryFetch instruction from memory


2/23


Phases of Instruction Processing

Six basic phases of instruction processing F D EA OP EX S

Instruction fetch

Instruction decode

Evaluate address

Fetch operands

Execute

Store result

Notes

Not all phases are needed by every instruction But all instructions will go through F and D

Phases may take more than one clock cycle


Phases: Fetch Load next instruction (at

address stored in PC) from

memory into Instruction

Register (IR).

Copy contents of PC into

MAR.

Send read signal to

memory.

Copy contents of MDR into

IR.

Then increment PC, so that it

points to the next instruction in

sequence.

PC becomes PC+1.

EAEA

OPOP

EXEX

SS

FF

DD


3/23


Phases: Decode

EAEA

OPOP

EXEX

SS

FF

DD

First identify the opcode

In LC-3, this is always the

first four bits of instruction.

A 4-to-16 decoder asserts

a control line

corresponding to the

desired opcode.

Depending on opcode, identify

other operands from the

remaining bits

Example:

for LDR, last six bits is

offset

for ADD, last three bits is

second source

operand


Phases: Evaluate Address

EAEA

OPOP

EXEX

SS

FF

DD

For instructions that

require memory access,

compute address used

for access

Examples:

add offset to baseregister (as in LDR)

add offset to PC

add offset to zero


4/23


Phases: Fetch Operands

EAEA

OPOP

EXEX

SS

FF

DD

Obtain source operandsneeded to perform the

operation

Examples:

load data from memory(LDR)

read data from register file(ADD)


Phases: Execute

EAEA

OPOP

EXEX

SS

FF

DD

Perform the operation,

using the source

operands

Examples:

send operands to ALUand assertADD signal


5/23


Phases: Store Result

EAEA

OPOP

EXEX

SS

FF

DD

Write results to destination

(register or memory)

Examples:

result ofADD is placed in

destination register

result of memory load is

placed in destination

register

for store instruction, data is

stored to memory

write address to MAR,

data to MDR

assert WRITE signal tomemory


LC-3 Data Path

Filled arrow

= info to be processed

Unfilled arrow

= control signal


6/23


Data Path Components: Global Bus

What is a bus? Global bus: Special set of wires that carry a 16-

bit signal to many components

Inputs to the bus are tri-state buffers that only

place a signal on the bus when they are

enabled

Only one device speaks on the bus at any given

time

Control unit decides which signal drives the bus

Any number of components can read the bus

Control unit write-enables the destination device


Tri-State Buffer Tri-state buffer allows some outputs to be turned off

Places them in high-impedance or high-Z state

Outputs can have one of three values

Zero (0)

One (1)

Z (no output)


7/23


Global Bus

What is a bus?


Memory, MAR, MDR Control and data

registers for memory and

I/O devices

MAR (Memory Address

Register)

Holds the last address

accessed

MDR (Memory Data

Register)

Holds the last data

read

Control signal for

read/write


8/23


ALU

Inputs: one of thefollowing

Register file

Immediate field

Sign-extended bits

from IR

Output goes to bus, and

then used by

Condition code logic

Register file

Memory


Register File Two read addresses(SR1, SR2)

One write address (DR)

Inputs: one of thefollowing

Result of ALUoperation

Memory read

Outputs: Two 16-bitoutputs used by

ALUALU instructions

Data for storeinstructions passesthrough ALU


9/23


PC and PCMUX

PC and PCMUX Program Counter and

the PC multiplexer

Input to PC: one of the

following (controlled by

PCMUX)

PC+1 from the fetch

stage

Output of address

adder (for branches

and jumps) Global bus for trap

instructions


MAR and MARMUX Inputs to MAR: one of the

following (controlled by

MARMUX)

Output of address

adder (for loads and

stores)

Zero-extended IR[7:0]

for trap instructions


10/23


Condition Codes

Input The global bus

Output

N, Z, P signals

Registers set only when

control unit enables them

(LD.CC)

Certain instructions

set the codesADD,AND,NOT, LD,

LDI, LDR, LEA


Data Path Components: Finite State Machine On each machine cycle, FSM changes control

signals for next phase of instruction processing

Who drives the bus?

GatePC, GateALU,

Which registers are write-enabled?

LD.IR, LD.REG,

Which operation should the ALU perorm?

ALUK

Logic includes opcode decoder, etc.


11/23


FiniteState Machine

On each machine cycle, FSM

changes control signals for

next phase of instruction

processing

Who drives the bus?

GatePC, GateALU,

Which registers are write-

enabled?

LD.IR, LD.REG,

Which operation should

the ALU perorm?

ALUK

Logic includes opcode

decoder, etc.


Tracing the Data Path Through the LC-3 Example 1

ADD R2, R0, R1

Example 2

STR R3, R5, xB

Example 3

BRz ENDLOOP


12/23


Example 1:1a. Fetch (step 1)

x30A2 add R2,R0,R1

System bus:


Example 1:

1b. Fetch (step 2)x30A2 add R2,R0,R1

System bus:


13/23


Example 1:2. Instruction Decode

x30A2 add R2,R0,R1

System bus:


Example 1:

3. Evaluate Addressx30A2 add R2,R0,R1

System bus:


14/23


Example 1:4. Fetch Operands

x30A2 add R2,R0,R1

System bus:

R0 =

R1 =

R2 =


Example 1:

5. Executex30A2 add R2,R0,R1

R0 =

R1 =

R2 =

System bus:


15/23


Example 1:6. Store Results

x30A2 add R2,R0,R1

System bus:

R0 =

R1 =

R2 =


Example 2:

x3117 STR R3,R5,xB

R3 =

R5 =

1. Instruction fetch

(1st step)


16/23


Example 2:

x3117 STR R3,R5,xB

R3 =

R5 =


(2nd step)


Example 2:

x3117 STR R3,R5,xB

R3 =

R5 =

2. Instruction decode


17/23


Example 2:

x3117 STR R3,R5,xB

R3 =

R5 =

3. Evaluate address


Example 2:

x3117 STR R3,R5,xB

R3 =

R5 =

4. Fetch operands


18/23


Example 2:

x3117 STR R3,R5,xB

R3 =

R5 =

5. Execute


Example 2:

x3117 STR R3,R5,xB

R3 =

R5 =

6. Store results


19/23


Example 3:

x3040 BRZ EndLoop

EndLoop =


(1st step)


Example 3:

x3040 BRZ EndLoop

EndLoop =


(2nd step)


20/232


Example 3:

x3040 BRZ EndLoop

EndLoop =

2. Instruction decode


Example 3:

x3040 BRZ EndLoop

EndLoop =

3. Evaluate address


21/232


Example 3:

x3040 BRZ EndLoop

EndLoop =

4. Fetch operands


Example 3:

x3040 BRZ EndLoop

EndLoop =

5. Execute


22/232


Example 3:

x3040 BRZ EndLoop

EndLoop =

6. Store results


Recommended exercises: Ex 4.8, 4.10

Ex 4.13 and 4.16 (a little bit more

advanced)


23/23


Full LC3 instruct ion set

Instruction Processing

Documents

Transcript of Instruction Processing