Institute of Applied Microelectronics and Computer Engineering College of Computer Science and...

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Spezielle Anwendungen des VLSI-Entwurfs

Special applications of VLSI design

Spezielle Anwendungen des VLSI – Entwurfs


5th Meeting Meeting (report part 3)

Prof. Dirk Timmermann, Frank Sill, Ronald Hecht,Stephan Kubisch, Harald Widiger, Claas Cornelius

Course and contest





Agenda

1. Presentation of first Layout results

2. Some Hints for Optimization

3. ClockTreeSynthesis and PowerAnalyzer Tutorials (by Hagen Sämrow)

4. One new Rule

5. Contest





First Results of Layout (CE - group)

3 - 5 minutes

1. Amit Hingher

2. Predrag Jankovic

3. Vinod Kumar Kothapalli

4. Victor Luyali

5. Kwang Yoal Kim





First Results of Layout (ET/ITTI)3 - 5 minutes

1. Peter Danielis / Peter Kröger

2. Markus Hempel / Tim Eickelberg

3. Martin Siemroth / Mathias Rulf

4. Jens Schulz / Petro Bravermann

5. Andreas Tockhorn / Hagen Sämrow

6. Jiaxi You





2. Some Hints for Optimization (1)

• For everybody: copy new start.sh from ‘/opt/des_kits/UMC/0.18/MD_Vorlagen/adder‘

• File > Import > System Constraints… /home/<user>/cadence_se/gcf/umc_pad_core_clocktiming.gcf

• Place > Cells > Timing Driven Placement> Power Driven Placement

> Optimize > Timing (Options)• Route > WRoute:

> Timing Driven Routing> Incremental Final Route






• After placement: Place > Placement optimizations (Optimize, Resolve Violations)

• After Routing: Route > Post-routing optimizations(Optimize, Resolve Violations, Use RSPF, Resize)

• !!! because new cells can be added > extraction of verilog-file necessarry !!! => File > Export > Verilog=> Output Verilog Filename: adder_top.v=> copy adder_top.v into your Synopsys-folder





New Floorplanning: • At Initialize Floorplan: modify I/O To Core Distance• Next: copy padcell positions etc. from template BUT: don’t copy lines like:

ROW ROW_XX core -251460 244160 N DO 764 BY 1 STEP 660 0 ;

from template

(this rule aims not for lines with: ROW ROW_XX IOSTGRD)






Manual: /opt/cadence/dsmse5.4/doc

=> some html-, pdf files in: sil*, qplace, wroute, ctgenuser, pearluser


Seite 9

Institut für Angewandte Mikroelektronik und Datentechnik

Fachbereich Elektrotechnik und Informationstechnik, Universität Rostock

CTS – Clock Tree Synthesis


Fachbereich Elektrotechnik und Informationstechnik, Universität Rostock Seite 10

Comparison

adder without clocktree adder with clocktree



clock tree

• to solve hold violations• not for increasing speed of the design• for training

• layout in an inverter structure



Preparation

• unzip „ctgen.zip“ in your Cadence SE folder• move „ctgen.constraints“ in the ctgen-folder



ctgen.constraitsbottom of „adder_top.v“:

change the clk pad

change to data input



ctgen.constraits

waveform: clock signal at the root pin

min_delay: minimum allowable insertion delay from the tree root to any leaf

max_delay: maximum allowable insertion delay from the tree root to any leaf

max_skew: maximum allowable skew between the insertion delay of any leaf



CTGEN.Command



Clock Tree Synthesis ( 1 )

• after the placement, before routing!

• need: def of the placed design– File -> Export -> DEF– deactivation of „Cells“ and „Special nets“ – DEF File Name: e.g. …/def/adder_preclk.def– OK



Clock Tree Synthesis ( 2 )

• use a terminal• enter in your CadenceSE-folder: „ctgentool ctgen.cmd“

=> Creation of a DEF-file with a clock tree



Import of the new DEF-file

• import with DEF ECO ( Engeneer Change Order ) because of change of the netlist outside SE

• File -> Import -> DEF ECO• change to the „cadence_se/def“-folder• choose: „adder_postclk.def“• OK



Ready

Clocktree is inserted.

Now you are ready for routing!

Seite 20


Fachbereich Elektrotechnik und Informationstechnik, Universität Rostock

Power Analyzer



Power Analyzer

• after Power Analysis with the Synopsys Design Analyzer• to view the power dissipation on the chip



Preparation

• change in the „dump.vcd“ in the Synopsys-folder:– write „adder_top“ instead of „dut“

• import of the activity file „dump.vcd“• File -> Import -> VCD• change to the Synopsys folder• choose „dump.vcd“• OK



Enter the Power Analyzer ( 1 )

•Report -> Power Analysis…•click on „Options…“ behind „Power“




•enter your .rspf-file ( e.g. „adder.rspf“ )•click on „Simple estimate:“•Change „Voltage per net (v)“ to 1.8•click on „Currently loaded values“•OK




•enable „Interactive“•OK



Power Analyzer

•2 windows will open–overview

–Rail Analysis Results



Rail Analysis Results

•only „Wire Current“, „Wire VDrop“ and „Cell Power Current“ are interesting•to adapt the colours ( for better comparison of the wires and cells ):

–click on „Color Gradient Legend…“

•then „Color Scale Option…“



Color Scale Options



Now you can view your Power Consumptions on your chip!





4. One new Rule

„Everybody fights for himself!“

That means: From now, the ET/ITTI groups are split up!





ContestWe are searching for:

1. The CE-Student with the best PDP

(delay from Cadence Timing Analysis multiplied with power dissipation at this delay)

2. The ET/ITTI-Student with the fastest design

(delay from Cadence Timing Analysis)

3. The ET/ITTI-Student with the best low power design

(power dissipation at 50 MHz)

4. The ET/ITTI with the smallest core-area

(area from row-definition in DEF-file)





Dinner

When?

Wednesday, July 6th at 6 pm.

Where?

Salsarico Mexikanisch (mexican restaurant), Warnemünde





Final meeting: July, 5th

Design hand-over: July, 4th @ 4 pm

each 5 minutes, max. 5 slides, presentation of contest results, picture from PowerAnalyzer

Questions? => Hagen Sämrow, Claas Cornelius, Frank Sill

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and...

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