Information-Flow Models for Shared Memory Allon Adir Hagit Attiya Gil Shurek.

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Information-Flow Information-Flow Models for Shared Models for Shared Memory Memory Allon Adir Allon Adir Hagit Attiya Hagit Attiya Gil Shurek Gil Shurek

Transcript of Information-Flow Models for Shared Memory Allon Adir Hagit Attiya Gil Shurek.

Page 1: Information-Flow Models for Shared Memory Allon Adir Hagit Attiya Gil Shurek.

Information-Flow Information-Flow Models for Shared Models for Shared

MemoryMemory

Allon AdirAllon Adir

Hagit AttiyaHagit Attiya

Gil ShurekGil Shurek

Page 2: Information-Flow Models for Shared Memory Allon Adir Hagit Attiya Gil Shurek.

Final state: R2=2 ?

Prog1 Prog2

load(X, R1) load(Y, R3)

R2 := R1 R3 := R3 + 1

R1 := 1

store(R1, Y) store(R3, X)

Initial state: All=0

Program ExampleProgram Example

Page 3: Information-Flow Models for Shared Memory Allon Adir Hagit Attiya Gil Shurek.

Prog1 Prog2

load(X, R1) load(Y, R3)

R2 := R1 R3 := R3 + 1

R1 := 1

store(R1, Y) store(R3, X)

Initial state: All=0

Final state: Y=R1=1, X=R2=R3=2

Program ExampleProgram Example

Page 4: Information-Flow Models for Shared Memory Allon Adir Hagit Attiya Gil Shurek.

Final state: Y=R1=1, X=R2=R3=2

Prog1 Prog2

load(X, R1) load(Y, R3)

R2 := R1 R3 := R3 + 1

R1 := 1

store(R1, Y) store(R3, X)

Initial state: All=0

PowerPC ConsistencyPowerPC Consistency

Page 5: Information-Flow Models for Shared Memory Allon Adir Hagit Attiya Gil Shurek.

Shared-Memory SemanticsShared-Memory Semantics

Capturing intricate shared-memory behaviors:SpeculationOut-of-Order ExecutionSynchronizationGranularity of Memory Accesses

Without revealing micro-architecture details

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OutlineOutline

What is an Architecture?What is a Computation Model?The FrameworkSequential ConsistencyPowerPC Consistency

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What is an "Architecture"?What is an "Architecture"?

Page 8: Information-Flow Models for Shared Memory Allon Adir Hagit Attiya Gil Shurek.

Elements of an ArchitectureElements of an ArchitectureResources

GranulesStates

InstructionsFormatsOperands

Source/TargetAddressing-Mode

State Transformation

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Elements of an ArchitectureElements of an ArchitectureProgram order

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Computation ModelComputation ModelCan we reach final state s2 by running a program Prog from initial state s1?

Written as Is s1, s2, Progpossible?

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Prog1 Prog2

store(R2, X)R1:=1 R2:=2 store(R1, X) store(R2, X)

Initial state: R1=R2=X=0

Final state: R1=1, R2=2, X=0 X=1 X=2

Example: Sequential ConsistencyExample: Sequential Consistency

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load

store

store

mul

xor

load

Text O

rder

nand

branchcmp

Instruction instances + Text order

Flow-of-Information

Is the flow-of-information allowed by the model?

The FrameworkThe Framework

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Resource X,R

Assignment resource-value pair (X,5)

Operation in-out pair ({(X,5)},{(R,5)})

Instruction ({(X,0)},{(R,0)}), ({(X,1)},{(R,1)}), ...

Program sequence of commands C1,...,Cm

Command an instruction B and a function

next: B [1..m]{}

The ElementsThe Elements

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Program Order: ExampleProgram Order: Example

C1: load(X,R1)

C2: R3 := R1+R2

next(C1)=2

next(C2)=

op1: ({(X,1)},{(R1,1)})

op2: ({(R1,1),(R2,1)}, {(R3,2)})

s1: {(X,1), (R1,1), (R2,1), (R3,1)}

s2: {(X,1), (R1,1), (R2,1), (R3,2)}

Prog Instantiating Prog

Program order: s1 op1 op2 s2

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Reads-From Mapping Reads-From Mapping

s1: All=1

load(X,R1)R3 := R1+R2

s2: R3=2, others=1

R1

R2

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Reads-From Mapping Reads-From Mapping

s1: All=1

load(X,R1)R3 := R1+R2

s2: R3=2, others=1

R1

R2

R1

R2, X

R3

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store(R2,X)store(R1,Y)

s1: All=0 s2 : All=1

load(X,R1) load(Y,R2)

The Reads-From Mapping is not CyclicThe Reads-From Mapping is not Cyclic

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View orders View orders Order the operations in ProgOne for each Progi

Obey architecture-specific rules relating program-orderreads-from mapping

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I(X)

s1

op3

s2op4op2op1

op5

< << <

(x)

O(X)

Sequential ExecutionSequential Execution

Information can not be read from the hidden past

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s1

op3

s2op4op2op1

< << <

Sequential ExecutionSequential Execution

Information can not be read from the future

op5

Relative to which order?

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Sequential ConsistencySequential ConsistencyS1,S2,Prog is sequentially consistent ifProg can be instantiated with a set of operations A and program order

A single view order linearextends the program order

Information flow satisfies the sequential execution conditions relative to view order

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PowerPC ConsistencyPowerPC Consistency

Information flow satisfies the sequential execution conditionsRelative to program orderRelative to view orders

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View orders enforce that

Memory is coherent, except for local stores.Shared resource dependencies are preserved.sync orders operations around it.sync is transitive (sort of…).Branch dependencies are preserved.

PowerPC Consistency: View OrdersPowerPC Consistency: View Orders

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PowerPC Consistency: View Orders IPowerPC Consistency: View Orders I

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PowerPC Consistency: View Orders IIPowerPC Consistency: View Orders II

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Speculation is Visible to ProgramsSpeculation is Visible to Programs

Final state: X=Y=1R1=1,R2=0R3=1,R4=0

Initial state: All=0

Prog1 Prog2 Prog3 Prog4

load(X,R1) load(Y,R3) store(1,X) store(1,Y)sync syncload(Y,R2) load(X,R4)