iNEMI Test and Inspection TIGthor.inemi.org/webdownload/2018/Test_TIG_082118.pdf · iNEMI Test and...

iNEMI Test and Inspection TIG

August 21, 2018

Recording (available up to 6 months after webinar)https://inemi.webex.com/inemi/ldr.php?RCID=b515f6993fd3fa1dc3abbfefebcfe4a6

https://inemi.webex.com/inemi/ldr.php?RCID=b515f6993fd3fa1dc3abbfefebcfe4a6

iNEMI Technology Integration Groups (TIGs)

• The iNEMI Technology Integration Groups (TIGs) are groups of

experts in particular technology areas, drawn from the iNEMI

membership, that propose and lead collaborative programs within

iNEMI to address industry needs and members’ interests

• The TIGs give all iNEMI members an opportunity to influence the

selection and the direction of projects in their particular technology

area of interest

iNEMI TIGs

PackagingTIG

OptoelectronicsTIG

Sustainability TIG

Board AssemblyTIG

Test, Inspection & Measurement

TIG

PCBTIG

M. Tsuriya

H. Fu

S. Payne

D. Godlewski

Smart ManufacturingTIG

Harsh EnvironmentTIG

Active TIGs

Proposed new TIGs (TBC)

D. Godlewski M. Schaffer

M. Benowitz G. O’Malley

iNEMI TIG Responsibilities:

• Discuss and share (pre-competitive) issues relevant to their

technology area. These may required communication with other TIGs

and Roadmap TWGs as needed

• Identify key gaps and challenges in the near and mid-term, with input

from industry and Roadmap, and contribute to developing the iNEMI

technical plan, approx. every 2 years

• Propose and prioritize candidate projects to be addressed in a cross

industry/academic collaborative approach by iNEMI

• Identify resources for these projects from their organizations and

networks

• Collaborate and report on projects

• Identify and help organize workshops or other activities in the TIGs

technology area

5

Product

Needs

Technology

Evolution

GAP

Analysis/

Technical

Plan

Research

Projects

Implementation

Where do TIGs fit in the iNEMI Project Planning Process?

Competitive

Solutions

Roadmap

Project

Completion

Industry Solution

Needed

iNEMI Members involved

in self funded

collaborative projects

championed by the TIGs

No Work

Required or

Outsourced

Available to

Market Place

Global Industry

Participation through

PEGS and TWGs

Information

Gathering

iNEMI membership

identify and drive

collaborative projects

through the TIGS

Analysis

iNEMI TIG Participants Requirements:

• All iNEMI member organizations can participate

• All iNEMI members are asked to nominate representatives to a

TIG

• Representatives from Non-member organizations may be

invited to participate on a case-by-case basis when their

critical expertise is warranted (approval required by VP Ops

and/or CEO and the TIG chairs)

iNEMI TIG Logistics:

• The TIGs will be chaired by iNEMI members, facilitated by an iNEMI staff member

• An iNEMI Technical Committee (TC) member will be assigned as mentor to every TIG, to give guidance and to aid communication between the TC and the TIG

• TIGs will meet (virtually) at least 5 times annually, or as determined by a majority of TIG members

• Special TIG meetings can be called by chairs or VP or CEO

• As appropriate, TIG meetings will try to take advantage of industry conferences and events for possible face-face meetings and networking

iNEMI TIG Outputs:

• TIGs should report to TC every 6 months

• TIGs suggest at least 3 projects proposals annually to iNEMI TC

• TIGs should aim to have at least 1 ongoing iNEMI project at all times

• TIGs will lead the development of the technical plan in their

particular technical area every 2 years, after the biennial roadmap

update

iNEMI TIG Benefits of Participation:

Active cross-industry networking to identify key challenges for

technology development and deployment in your technical areas of

interest

Opportunity to develop and prioritize the iNEMI technical plan to

complement industry and your organizations efforts

Determine the collaborative projects that iNEMI members will be

working on and where your organization can gain benefit from

iNEMI TIG Commitment:

Workload expected: 0.5-1 day every two months

Includes Virtual meetings approximal 5 times per year

Test and Inspection TIG Technical Plan Status

Test and Inspection TIG Background

Objective:

• Improve the effectiveness of the manufacturing, test, and automated

inspection processes and quality of electronic products in a global

manufacturing environment

• Increased explosion of manufacturing in Asia, manufacturing test

responsibility has increased for CMs and ODMs

• This creates an opportunity for OEMs, CMs, ODMs and test &

inspection providers to work together to develop common test

standards, processes, and tools that will increase the quality of

electronic products

Test and Inspection TIG Background

Scope:

• Includes manufacturing test and inspection technology and process

improvement for boards and systems

• Examples include automated test inspection, electrical test,

boundary scan, functional test, system test, AOI, and AXI

• Test areas not included are reliability tests such as Burn In;

HALT/HASS/HASA; and component and design validation testing

13

Completed and In-progress Test TIG Projects

Completed:

• Built-In Self-Test (BIST) Program

• Board Flexure Standardization, Phase 1

• Board Flexure Standardization, Phase 2

• Boundary Scan Adoption, Phase 1

• Functional Test Coverage Assessment Project

• Structural Test of External Memory (Boundary Scan Adoption,

Phase 2)

• Structural Test of External Memory (Boundary Scan Adoption,

Phase 2)

In progress:

• Characterize and Quantify the Production Inspection Capability of

the AXI of HiP (Head in Pillow) Defects

The Access Challenge; One Aspect

Portable NetCom Consumer/Office Automotive

2007 N/A 30 22 30

2009 N/A 30 22 30

2011 N/A 30 12 30

2013 N/A 24 12 / 3* 26

2015 N/A 24 12 / 3* 20

2017 N/A 18 12 / 3* 18

2019 N/A N/A 12 / 3* 18

2021 N/A N/A 12 / 3* 18

2023 N/A N/A 12 / 3* 18

2025 N/A N/A 12 / 3* 18

Table 4: Test pad (min) size in mils

* e.g. Bead Probe

Test Pad Access; Percent of Nets90

0

10

20

30

40

50

60

70

80

90

100

2011 2013 2015 2017 2019 2023

Portable

Medical

High End

Automotive

Office

Defense

Test Gap Analysis; Note: Specific Applications and Products Can be Worse

Board Level

• Focus in on test methodologies for 3D devices – both at

component and system levels, as effective interconnects on all

power and ground plus signal are required on these ultra high

speed applications-------------------------------------------------------------

• Application of holistic SMART Manufacturing in production lines

start to finish --------------------------------------------------------------------

• Characterize and quantify the inspection capability of the AXI on

HoP (head on pillow) and HiP (Head in Pillow) defects --------------

• Develop optimized design rules/DFM/DFT & test methodologies

to support HDI technology ( <2um pitch ) --------------------------------

• BSDL Files Not Being Adequately Validated for Syntax and

Content --------------------------------------------------------------------------

• Need much improved tools for testing (effective and thorough

coverage) of embedded technologies; both passive and active-----

* Assess and develop optimized fine pitch inspection capabilities for

2 micron or less substrates

Functional, System Level

• Lack of DFT standards (BIST) ----------------------------------------------

2017 2019 2021 2023

Manufacturable solutions exist, and are being optimized

Manufacturable solutions are known

Interim solutions are known

Manufacturable solutions are NOT known

Test 5 Year PlanDrivers - Limited board test access - Cost reductions - Process optimization - Test time reduction

- Outsourcing - Environmental Requirements - Time to Market

20232017 2019 2021

Attributes

Evolving fault spectrum

I/O Signal speeds > 20 GHz

Voltage/logic levels 0.6-0.9VDD

High Density Interconnect

BGA pitch – .3mm /.5mm

Nodes – >15k

HF Materials

BSDL Validation

Probe-able Micro Via / Pad Size (mils) – 12/5 (HDI)

Min Test Pad Size (mils) – 20

Attributes


I/O Signal speeds >40 GHz


3D Packages - Starting in 2015


Opto-Electronic Tests


Nodes – >15K

HF Materials

Micro Via / Pad Size (mils) – 12/5 (HDI)

Min Test Pad Size (mils) –18

Attributes




3D Packages


Node access to Embedded Devices

Internal access BIST



Nodes – >15K

HF Materials

Micro Via/Pad Size (mils)– 12/5 HDI

Min Test Pad Size (mils) –16Deployed Technology

Adv. Functional Test Solutions

Adv. Boundary Scan

BIST

Fault Coverage Metrology

Trace Probing Solutions

DDR4 Testability (1581)

Deployed Technology


Adv. Structural Test Solutions

BIST

Virtual Access

BSDL Validation Tools

1149.1 for 3D Technologies

Deployed Technology


Adv. Structural Test Solutions

Adv. BIST (BA-BIST)

Virtual Access

BSDL Validation Tools / Processes

P1687 & 1149.1.2013 for 3D Technologies

Research /Development

Adv. Test Solutions (HDI)

Adv. BIST

Board Flex solutions due to HF

3D Packages + IEEE partnership

Continuous Security concerns / gaps


New test techniques / solutions

HDI PCB Test Solutions

Opto Electronics test strategies

3D Packages + IEEE partnership

Security concerns



Opto Electronics test strategy

Evolution of board defects

Security concerns

Attributes




Evolution of hi-speed board defects

3D Packages


Node access to Embedded Devices



Nodes – >15K

HF Materials

Micro Via/Pad Size (mils)–12/5 HDI

Min Test Pad Size (mils) –14

Deployed Technology

Adv. Test Solutions

Adv. Structural Test

Adv. BIST

Virtual Access

Opto-Electronic Test Solutions


P1838 Solutions

Security Solutions



Evolution of board defects

19

What has changed

• Continuous erosion of test access

• Increased complexity of component packages

• Increasing signal speeds making test more difficult and costly

• Increasing pin count, ball count, decreasing pitch on BGA

packages driving routing issues on boards

• 3D electronic packages are new, and a problem

• Evolution of Silicon technology is threatening established

testability standards

• Lack of standard test solutions for HDI testing

• No standards that can be leveraged from chip to board to system

level Built In Self-Test

• Optical Interconnects are new, and need addressing

20

TIG Plan

Two projects now in place and moving forward:

• Characterize and quantify the inspection capability of the AXI on HoP (head on pillow) and HiP (Head in Pillow) defects

• NEMI Fine Pitch Circuit Pattern Inspection/Metrology Project, Phase 2 – Inspection capabilities for 2um pitch or smaller

• New focus areas – iNEMI opportunity possibilities– Partnership with IEEE to develop test standards for 3D packages

– Design for Functional Test (Board Assist BIST), a new BA-BIST phase

– Structural Test Coverage (Board Assist BIST ), a new BA-BIST phase

– Optical Interconnect test strategies

– Evolution of board defects

– Tighter partnering with JEDEC to drive memory standards and testability

• Concern:

– Help & Leadership needed from EMS & other iNEMI geos (ASIA, Europe) for new focus areas

TIG Plan

New focus areas – Research ( University / Non profit )

– Testing strategies of 3D packages

IEEE P1838: testing of die and testing of board (two challenges).

Protocols may be different. No perception on what to do yet.

FPGA vs memory folks all driving this technology as they see

immediate benefit. This item needs to be addressed by the

standards group IEEE P1838

• Evolution of board defects New / evolving defects because of Optical Interconnects, higher

speeds, 3D, embedded components, security concerns, etc

‾ Develop in depth understanding of Chiplet strategies and potential

deployment and then develop comprehensive test strategies and

capabilities to support

2017 Gap Analysis; All Real, All Very Generic

Priority < 5 Years (Tactical) Gaps/Needs Category

Board Level Issues

H

Application of holistic SMART Manufacturing in production lines start to finish could offer

order of magnitude improvements in both quality and cost order of magnitude

improvements in both quality and cost.

S,D,O

HNeed much improved tools for testing (effective and thorough coverage) of embedded

technologies; both passive and active.D,S,O

H

Focus in on test methodologies for 3D devices – both at component and system levels.

Effective interconnects on all power and ground plus signal are required on these ultra

high speed applications.

S, D

H BSDL Files Not Being Adequately Validated for Syntax and Content. S, O

HCharacterize and quantify the inspection capability of the AXI on HoP (head on pillow) and

HiP (Head in Pillow) defects.O,S

HDevelop optimized design rules/DFM/DFT & test methodologies to support HDI technology

( <2um pitch ).S,D,O

Functional/System Level Issues

H Lack of BIST chip, board and system level standards O, S

H

Assess and develop fine pitch inspection metrology for 2 micron spacing or less

substrates O,D

H=High

M=Med

L=Low

Categories for < 5 years (Tactical Gaps)

Standards = S

Optimization = O

Development = D

Other = NA

2018 Strategic Needs

Priority > 5 Years Strategic Gaps/ Research Needs

H Testing strategies for flex circuits with embedded actives and passives

H Test processes must be developed along with the infrastructure to

implement as optical interconnect becomes deployed at board level.

H Add to research focused studies on the applications and impact for

“Chiplet” strategies

H=High

M=Med

L=Low

24

Summary

• Many key challenges in test

• Good projects in specific areas underway

• Need this team to prioritize the next 1-2 projects

to launch and drive

• Need inputs on leadership for identified projects

TIG Leadership

• Test and inspection TIG needs industry leadership

• Chair position or Co-chairs open

• Contact:

David Godlewski, [email protected]

Or

Masahiro Tsuriya, [email protected]

mailto:[email protected]

mailto:[email protected]

iNEMI Test and Inspection TIGthor.inemi.org/webdownload/2018/Test_TIG_082118.pdf · iNEMI Test and...

Documents

Transcript of iNEMI Test and Inspection TIGthor.inemi.org/webdownload/2018/Test_TIG_082118.pdf · iNEMI Test and...