INA-12063: 1.5 GHz Low Noise Self-Biased Transistor Amplifier · 2006. 7. 19. · INA-12063...

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DescriptionHewlett-Packard’s INA-12063 is aSilicon monolithic self-biasedtransistor amplifier that offersexcellent gain and noise figure forapplications to 1.5 GHz. Packagedin an ultra-miniature SOT-363package, it requires half the boardspace of a SOT-143 package.

The INA-12063 is a unique RFICthat combines the performanceflexibility of a discrete transistorwith the simplicity of using anintegrated circuit. Using a pat-ented bias circuit, the perfor-mance and operating current ofthe INA-12063 can be adjustedover the 1 to 10␣ mA range.

The INA-12063 is fabricated usingHP’s 30 GHz fMAX ISOSAT™Silicon bipolar process whichuses nitride self-alignmentsubmicrometer lithography,trench isolation, ion implantation,gold metalization, and polyimideintermetal dielectric and scratchprotection to achieve superiorperformance, uniformity, andreliability.

1.5 GHz Low Noise Self-BiasedTransistor Amplifier

Technical Data

INA-12063

Features• Integrated, Active Bias

Circuit

• Single Positive SupplyVoltage (1.5 – 5V)

• Current Adjustable, 1 to10mA

• 2 dB Noise Figure at900␣ MHz

• 16 dB Gain at 900 MHz

25 dB Gain at 100 MHz

Applications• Amplifier Applications for

Cellular, Cordless, SpecialMobile Radio, PCS, ISM,and Wireless LANApplications

Surface Mount PackageSOT-363 (SC-70)

Pin Connections andPackage Marking

Equivalent Circuit(Simplified)

Note:Package marking provides orientationand identification.

RF OUTPUTand VC

GND 1

12

Ibias

GND 2

RF INPUT

1

2

3

6

5

4 Vd

RFINPUT

GND 1

RFOUTPUT and Vc

GND 2

Vd

Ibias

RFFEEDBACKNETWORK

ACTIVEBIAS

CIRCUIT

5965-5365E

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INA-12063 Absolute Maximum RatingsAbsolute

Symbol Parameter Units Maximum[1]

Vd Supply Voltage, to Ground V 7

Vc Collector Voltage V 7

Ic Collector Current mA 15

Pin CW RF Input Power dBm 13

Tj Junction Temperature °C 150

TSTG Storage Temperature °C -65 to 150

Thermal Resistance[2]:θj-c = 170°C/W

Notes:1. Operation of this device above any

one of these limits may causepermanent damage.

2. TC = 25°C (TC is defined to be thetemperature at the package pinswhere contact is made to thecircuit board).

Electrical Specifications, TC = 25°C, Vd = 3 V, unless notedSymbol Parameters and Test Conditions Units Min. Typ. Max. Std.Dev.[3]

GP Power Gain (|S21|2) f = 900 MHz[1] dB 14.5 16 0.36f = 250 MHz[2] 19

NF Noise Figure f = 900 MHz[1] dB 2.0 2.6 0.2f = 250 MHz[2] 5.0

P1dB Output Power at 1 dB Gain Compression f = 900 MHz[1] dBm 0f = 250 MHz[2] -7

IP3 Third Order Intercept Point f = 900 MHz[1] dBm 15f = 250 MHz[2] 2

Idd Device Current[4] 900 MHz LNA[1] mA 5 7 0.6250 MHz IF Amp[2] 1.5

Notes:1. See Test Circuit in Figure 32.2. See Test Circuit in Figure 33.3. Standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during

the initial characterization of this product, and is intended to be used as an estimate for distribution of the typicalspecification.

4. Idd is the total current into Pins 1, 4, and 6 of the device, i.e. Idd = Ic + Ibias + Id.

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INA-12063 Typical Performance, 900 MHz LNA (900 MHz Test Circuit, see Figure 32)TC = 25°C, ZO = 50 Ω, Vd = 3 V, IC = 5 mA, unless noted

Vd (V)

Figure 7. Supply Current vs. Voltage and Temperature.

0

2

4

6

10

8

SU

PP

LY

CU

RR

EN

T (

mA

)

0.1 0.5 0.7 0.9 1.10.3 1.3 1.71.5 1.9

FREQUENCY (GHz)

Figure 1. Gain vs. Frequency.

-10

0

-5

10

5

15

20

GA

IN (

dB

)

1 2 3 4 5

Vd (V)

Figure 4. Gain at 900 MHz vs. Voltage and Temperature.

14.8

15.6

15.2

16.4

16.0

16.8

17.2

GA

IN (

dB

)

0.1 0.5 0.7 0.9 1.10.3 1.3 1.71.5 1.9

FREQUENCY (GHz)

Figure 2. Input Return Loss vs. Frequency.

-20

-10

-15

-5

0

RE

TU

RN

LO

SS

(d

B)

0.1 0.5 0.7 0.9 1.10.3 1.3 1.71.5 1.9

FREQUENCY (GHz)

Figure 3. Output Return Loss vs. Frequency.

-20

-10

-15

-5

0

RE

TU

RN

LO

SS

(d

B)

TA = +85°CTA = +25°CTA = –40°C

TA = +85°CTA = +25°CTA = –40°C

1 2 3 4 5

Vd (V)

Figure 5. Noise Figure at 900 MHz vs. Voltage and Temperature.

1.7

2.2

1.95

2.45

2.7

NO

ISE

FIG

UR

E (

dB

)

+85°C

+25°C

–40°C

1 2 3 4 5

Vd (V)

Figure 6. Output P1dB at 900 MHz vs. Voltage and Temperature.

-2

0

-1

2

1

3

4

P1d

B (

dB

m)

TA = +85°CTA = +25°CTA = –40°C

10 2 3 4 5

DEVICE CURRENT (mA)

Figure 8. Output P1 dB at 900MHz vs. Device Current for Vd = 3 V.

-6

-3

0

3

9

6

P1

dB

(d

Bm

)

42 6 8 10

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INA-12063 Typical Scattering Parameters[1], IC = 1.5 mATC = 25°C, ZO = 50 Ω, Vd = 3.0 V

Freq. S11 S21 S12 S22GHz Mag. Ang. dB Mag. Ang. dB Mag. Ang. Mag. Ang.0.1 0.93 -8 12.6 4.26 172 -42.2 0.01 86 0.99 -30.2 0.92 -16 12.5 4.20 164 -36.2 0.02 79 0.99 -70.3 0.90 -24 12.3 4.11 157 -32.8 0.02 73 0.98 -100.4 0.89 -32 12.0 4.00 149 -30.5 0.03 69 0.96 -130.5 0.83 -38 11.7 3.83 141 -29.1 0.04 64 0.94 -160.6 0.79 -45 11.3 3.69 135 -27.9 0.04 60 0.93 -190.7 0.75 -52 10.9 3.49 128 -26.8 0.05 56 0.91 -210.8 0.72 -58 10.4 3.32 122 -26.1 0.05 53 0.89 -230.9 0.69 -64 10.1 3.18 116 -25.5 0.05 50 0.87 -261.0 0.65 -69 9.6 3.03 111 -24.9 0.06 47 0.86 -281.1 0.61 -74 9.2 2.89 106 -24.5 0.06 45 0.84 -301.2 0.59 -80 8.7 2.72 102 -24.2 0.06 43 0.83 -321.3 0.55 -84 8.4 2.64 97 -23.9 0.06 41 0.82 -341.4 0.52 -89 8.1 2.54 92 -23.6 0.07 40 0.81 -351.5 0.49 -94 7.7 2.43 88 -23.3 0.07 38 0.80 -371.6 0.47 -98 7.3 2.33 84 -23.2 0.07 36 0.79 -391.7 0.44 -103 7.0 2.23 80 -22.9 0.07 35 0.78 -401.8 0.42 -107 6.6 2.15 77 -22.9 0.07 35 0.77 -421.9 0.40 -112 6.4 2.08 73 -22.5 0.07 34 0.77 -442.0 0.38 -116 6.0 1.99 69 -22.3 0.08 33 0.76 -452.1 0.36 -120 5.7 1.93 66 -22.1 0.08 32 0.75 -472.2 0.34 -124 5.3 1.83 63 -22.0 0.08 29 0.74 -492.3 0.31 -129 5.2 1.82 59 -21.9 0.08 30 0.74 -512.4 0.31 -133 4.7 1.72 57 -22.0 0.08 29 0.73 -522.5 0.29 -137 4.6 1.70 54 -21.7 0.08 31 0.73 -542.6 0.28 -144 4.3 1.65 50 -21.4 0.08 30 0.73 -562.7 0.27 -149 4.1 1.60 47 -21.0 0.09 29 0.72 -582.8 0.25 -154 3.7 1.54 44 -20.7 0.09 27 0.71 -602.9 0.23 -156 3.5 1.50 41 -20.9 0.09 24 0.70 -613.0 0.24 -162 3.5 1.49 39 -21.0 0.09 28 0.71 -63

Note:1. Reference plane per Figure 31 in Applications Information section.

0.1 0.9 1.7 2.5

FREQUENCY (GHz)

0

10

5

20

15

25

30

GA

IN (

dB

)

MAG

MSG

|S21|2

Typical Noise Parameters @ 900 MHz, IC = 1.5 mAFmin (dB) Γopt Mag. Γopt Ang. RN (Ω)

1.4 0.6 36 23

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INA-12063 Typical Scattering Parameters[1], IC = 2.5 mATC = 25°C, ZO = 50 Ω, Vd = 3.0 V



0.1 0.9 1.7 2.5

FREQUENCY (GHz)

0

10

5

20

15

25

30

GA

IN (

dB

)

|S21|2

MSG

MAG

Typical Noise Parameters @ 900 MHz, IC = 2.5 mAFmin (dB) Γopt Mag. Γopt Ang. RN (Ω)

1.5 0.54 36 20

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INA-12063 Typical Scattering Parameters[1], IC = 5 mATC = 25°C, ZO = 50 Ω, Vd = 3.0 V



0.1 0.9 1.7 2.5

FREQUENCY (GHz)

0

10

5

20

15

25

30

GA

IN (

dB

) MSG

|S21|2

MAG

Typical Noise Parameters @ 900 MHz, IC = 5 mAFmin (dB) Γopt Mag. Γopt Ang. RN (Ω)

1.8 0.41 38 16

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INA-12063 Typical Scattering Parameters[1], IC = 8 mATC = 25°C, ZO = 50 Ω, Vd = 3.0 V



0.1 0.9 1.7 2.5

FREQUENCY (GHz)

0

10

5

20

15

25

30

GA

IN (

dB

) MAG

|S21|2

MSG

Typical Noise Parameters @ 900 MHz, IC = 8 mAFmin (dB) Γopt Mag. Γopt Ang. RN (Ω)

2.0 0.30 41 15

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INA-12063 ApplicationsInformationIntroductionThe INA-12063 is a unique RFICconfiguration that combines theperformance flexibility of adiscrete transistor with thesimplicity of using an integratedcircuit.

The INA-12063 is an integratedcircuit that combines threefunctions: (1) a silicon bipolar RFtransistor, (2) an RF feedbacknetwork, and (3) a patented[1]

bias regulation circuit. A simpli-fied schematic diagram of theINA-12063 is shown in Figure 9.The result is a versatile gain stagethat can be operated from a single+1.5 to +5 volt power supply withthe device current set by the user.

The INA-12063 is designed for usein battery powered equipmentdemanding high performancewith low supply voltages andminimal current drain. Typicalapplications for the INA-12063include low noise RF amplifiers,IF amplifiers, gain and bufferstages through 2 GHz. TheINA-12063 is an excellent choicefor use in cellular and cordlesstelephones, PCS, W/LAN’s, RFmodems and other commercialwireless equipment.

RFINPUT

GND 1

RFOUTPUT and Vc

GND 2

RFTRANSISTOR

Vd

Ibias

RFFEEDBACKNETWORK

ACTIVEBIAS

CIRCUIT

Figure 9. INA-12063 Schematic.

DescriptionThe active bias circuit solvesthree problems normally encoun-tered with traditional approachesfor biasing discrete transistors.First, as an active bias circuit, theemitter of the RF transistor is DCgrounded. This permits thecollector current to be controlledwithout the need for resistorsand/or bypass capacitors in theemitter that may degrade RFperformance.

Second, the internal bias circuitgreatly simplifies the design taskscommonly associated with bias-ing transistors, such as accuratelyregulating the collector current,allowing for variations in hFE,making a non-intrusive DCconnection to the base of thetransistor, and stabilizing currentover temperature.

And, third, the integrated biascircuit eliminates the cost, partscount, and associated PCB spacerequired for as many as 8 addi-tional DC components.

The integrated bias control circuitis very easy to use. For mostapplications, the collector currentfor the RF transistor can be setwith a single resistor.

The geometry of the integratedRF transistor is designed toprovide an excellent balancebetween low noise figure, highgain, and good dynamic rangewhile retaining practical imped-ance matching levels. The operat-ing current is typically in the 1 to10 mA range.

The integrated RF feedbackcontains an inductive element inthe emitter circuit of the RFtransistor. This series feedback

configuration is of the type oftenimplemented in discrete transis-tor designs for the purpose ofimproving stability and bringingthe optimum noise match at theinput of the transistor closer to50␣ Ω. The result is that for manyapplications, a simple, seriesinductor is often all that is neededto adequately match the input ofthe INA-12063 to 50 Ω.

In contrast to amplifiers that useresistive feedback to achievebroadband 50 Ω input and outputmatches, the INA-12063 leavesthe designer with the flexibility ofoptimizing performance for aparticular frequency band. Forexample, frequency selectiveinput and output impedancematching circuits can be used totune for optimum NF, maximumoutput power, low input VSWR,or to tailor the passband responseto eliminate undesirable gainresponses.

Setting the Bias CurrentThe integrated, active bias circuitis a 10:1 current mirror. Thecurrent mirror forces the collec-tor current in the RF transistor tobe approximately 10 times thecurrent supplied to the Ibias pin.

In normal use, a voltage between+1.5 and +5 volts, is applied toboth the Vd and Vc terminals ofthe INA-12063. Although normallyconnected to the same supplyvoltage, it is not necessary thatboth Vd and Vc be at the samevoltage.

The collector current of the RFtransistor is then set by injectinga small control current into theIbias pin that is approximately1/10 of the desired collectorcurrent.

1 U.S. Patent Number 5436595

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The following “10-step” programis suggested as the design se-quence:

1. Determine performance goals.2. Select the bias condition.3. Choose PCB material.4. Check stability.5. Determine required DC

connections.6. Design the input impedance

matching network.7. Design the output impedance

matching network.8. Layout the printed circuit

board.9. Computer optimization and

performance verification.10. Fabricate, assemble, and test.

Each of these steps in the designsequence will now be discussedin the following sections.

Step 1. Establish PerformanceGoalsThe first step in the design of anINA-12063 amplifier stage is toestablish performance goals. Itmay be necessary to considerperformance tradeoffs betweensome amplifier parameters, suchas Noise Figure, Input VSWR,Gain, Output Power, OutputVSWR, Stability, and DC powerconsumption.

Some of these parameters arecounterposed, for example,increased output power requiresgreater DC power consumption.The tradeoff decisions mayrequire consideration of thechoice of DC bias which isdiscussed in the next section. Thefinal design will often be abalance between system-criticalperformance and those param-eters of lesser significance.

Step 2. Choose BiasConditionsThe second step of the designprocess is to choose the biasconditions, i.e., the RF transistoroperating voltage (Vc) andcurrent (Ic). The bias conditionsare chosen at this step in thedesign sequence since many ofthe RF design characteristics(e.g., S-parameters and noiseparameters) are dependent oncurrent and/or voltage.

The choice of bias voltage is oftenpreemptive as it is normally fixedby available system resources,such as a battery voltage orsystem power supply. TheINA-12063 will operate fromsupply voltages from 1.5 to5␣ volts, with +3 volts consideredto be the typical operatingvoltage.

Although noise figure and gainare somewhat insensitive todevice voltage as an independentvariable, some increase in outputpower can be realized with higherdevice voltages.

The bias current has the greatesteffect on RF performance and thefollowing tradeoffs should beconsidered:

Noise Figure increases withdevice current. The data in theTypical Noise Parameter tablesshows an increase in Fmin of from1.4 dB at 1.5 mA of bias current to2.0 dB at 8 mA.

Gain – Transducer gain, |S21|2,increases significantly in propor-tion to device current.

Output Power – One of thebenefits of increased devicecurrent is greater output power. Atypical increase in current from1.5 to 8 mA results in a corre-

While there are any number ofmeans of supplying the Ibiascontrol current, the simplest wayis to merely place a resistorbetween the Vd and Ibias termi-nals, shown as “Rbias” inFigure␣ 10. R bias will be suffi-ciently high to act as a currentsource. The value for Rbias iscalculated as follows:

Rbias = 10 ( Vd – 0.8) (1) Ic

where Vd is the device voltage, Icis the desired collector current,and Rbias is the value of the biasdetermining resistor. For ex-ample, for a desired collectorcurrent of 1.5 mA and a powersupply of 2.7 volts, the value ofRbias would be 12.7 KΩ.

Power DownA power-down function for theINA-12063 can be convenientlyimplemented by switching theIbias current. This method has theadvantage of switching only avery small current since Ibias istypically only a fraction of a mA.

RFINPUT

GND 2

Vd

Vc

Ic

Ibias

Rbias

RFTRANSISTOR

GND 1

RF OUTPUT

SUPPLYVOLTAGE

RFFEEDBACK

CIRCUIT

ACTIVEBIAS

CIRCUITBIAS

ISOLATION

Figure 10. Single-Resistor BiasCircuit.

Amplifier ApplicationGuidelinesThis section describes the generalapproach for designing amplifiersusing the INA-12063. This is ageneric design approach and isapplicable for most low noise RFor IF amplifiers or for generalpurpose gain and buffer stages.

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sponding increase in P1dB of-5.2␣ dBm to +4.6 dBm. The datasheet curve in Figure 8 character-izes the P1dB - Ic tradeoff.

Impedance Match – While it isnot a parameter per se, thedegree of difficulty of impedancematch may also be a consider-ation in the selection of biascurrent. Generally, the higher thedevice current, the less “severe”the impedance match, i.e., Γopt,Γms, Γml are all closer to 50 Ω.

Step 3. Selection of PCBMaterialIf the selection of PCB materialhas not been preordained byother factors (e.g., system stan-dards) then it should be chosen atthis stage of the design process.The printed circuit board materialis chosen at this step since it willhave an effect on the next step ofthe stability analysis and on thesubsequent design of the imped-ance matching networks.

Key factors to consider in theselection of board material aredielectric constant, RF losscharacteristics, board thickness,and cost.

The dielectric constant and boardthickness together contribute tothe physical geometry of thecircuit, an important consider-ation for miniaturization. Higherdielectric constant materialenables the construction of morecompact circuits since thephysical dimensions of transmis-sion lines are smaller.

In addition to transmission linewidths, PCB board thickness alsoinfluences the quality of groundvias. Ground vias in excessivelythick PCBs result in high induc-tance paths to ground. For someactive devices, poor grounding

can result in performance degra-dation or reduced stability.

Dielectric loss is not a significantfactor for the moderate frequencyranges over which the INA-12063is normally used. Low loss, lowdielectric constant “microwave”type materials are usuallyreserved for applicationsdemanding the very lowest noisefigures (minimum circuit loss)and/or for frequencies above2␣ GHz.

An overall good choice for mostlow cost wireless applicationsusing devices such as theINA-12063 is a fiberglass-epoxymaterial such as FR-4 or G-10with a thickness in the range of0.020 to 0.031 inches.

Step 4. Stability AnalysisA stability analysis is the nextstep in the design process. Thepurpose of this step is to examinethe circuit’s tendency to oscillate.A linear CAD program, such asHewlett-Packard’s Touchstoneshould be used to calculate thestability factor, K, and stabilitymeasure, B1. The factors K andB1 are both derived from theS-parameters for the INA-12063 atthe previously established biasvoltage and current. The condi-tions for unconditional stabilityare:

K > 1 and B1 > 0

While a simple analysis basedonly on the S-parameters is oftenadequate at this point, a slightlymore rigorous analysis is recom-mended that includes the para-sitic elements in the device’s pathto ground. At this stage in thedesign, a reasonable estimation(guess) of this electrical path andthe construction of the groundvias are adequate. For theINA-12063, bear in mind that

Pin␣ 5 of the package is the criticalconnection for “RF” grounding. Atypical RF path to ground con-sists of a short length of transmis-sion line terminated in one ormore ground vias. (The length ofthe PCB pad between theINA-12063 ground pin and theground should be modeled as amicrostripline (“MLIN” in Touch-stone), and the plated throughground holes as “VIA” elements.)

When evaluating stability, it is agood practice to calculate K andB1 over the full frequency rangefor which S-parameters areavailable. The reason for this isthat even though K and B1 mayindicate stability over the fre-quency band of interest, thepossibility exists for a circuit tooscillate at frequencies that arefar outside of the band of interest.

While unconditional stabilityrequires a positive, non-zerovalue of B1, most of the followingstability analysis will focus on theK factor since the value of Kindicates the degree of stability.What should the minimum valueof K be to ensure stability? WhileK=1.001 is stable, some margin isprudent to allow for componenttolerances, temperature effects,and manufacturing variations.Typical rules of thumb suggestthat K should be at least 1.2 to1.5.

There are three possible casesresulting from the CAD analysis:

• Case 1 – K>1 over the entirefrequency range.

• Case 2 – K>1 within the bandof interest and K

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If the CAD analysis indicatesthere is a potential instabilityissue (K < 1 and/or B1 ≤ 0 for anyfrequency) as in Case 2 or Case 3above, then some stabilitycountermeasures will be needed.

There are four basic techniquesfor handling potential instability:

(a) Live with it. If the source andload impedances that will bepresented to the amplifier arewell defined, the finesseapproach of using stability circlesmay be used. Stability circles(calculated by a program such asTouchstone) are plotted on aSmith chart and define regions ofloads that could cause a circuit tooscillate. An amplifier is safefrom oscillation if the expectedamplifier terminations lie welloutside of the unstable regions onboth the input and output imped-ance planes. Since the possibilityof oscillation could exist at anyfrequency for which theINA-12063 has gain, stabilitycircles must be checked atfrequencies over a widefrequency range when thismethod is used.

(b) Resistive feedback. The use ofresistive feedback is often used tocreate stable, wideband, amplifi-ers. While effective in stabilizingactive devices, this method willnot be considered here since asignificant penalty is often paid indegraded NF, less gain, andlowered output powerperformance.

(c) Lossless feedback. Reactivefeedback elements can also beused to stabilize amplifiers. TheINA-12063 already incorporatesone type of reactive feedback inthe emitter of the RF transistor,with a resulting improvement instability. Further use of the

lossless feedback technique is notsuggested for most INA-12063amplifier applications since thismethod adds considerable designcomplexity as well as additionalparts count and board space tothe circuit.

(d) Resistive loading. Resistiveloading can be used at either theinput or output of the INA-12063to create an unconditionallystable amplifier. This is the brute-force method of ensuring stabil-ity. It is fairly fail-safe and is alsothe simplest to implement. Theaddition of a resistive element toeither the amplifier input oroutput creates RF loss whichmanifests itself as lower gain pluseither increased NF (if theresistance is added to the input)or lower output power (if theresistance is placed at theoutput.)

In keeping with the goals of lowcost (i.e., circuit simplicity), theresistive loading method is thetechnique suggested for produc-ing an unconditionally stableamplifier for most applications ofthe INA-12063.

The resistive loading can beapplied in either series or shuntand can be added to either theinput or output of the amplifier.The choice of series or shuntresistive load may be dictated bywhether the real part of theoutput impedance of the amplifierdevice is greater or less than50␣ Ω. The logical choice is to usea shunt resistor when the ampli-fier impedance is >50␣ Ω and aseries resistor for the case of>50␣ Ω. This technique will bringthe overall impedance closer to50␣ Ω, thus simplifying the match.In some cases, excessive voltagedrop across the stabilizingresistor due to the DC current

into the device may preclude theuse of the series configuration.Shunt resistance is usually themost straightforward solution toimplement since it can be easilybypassed to ground with acapacitor without disturbing thebias.

For gain or buffer stages requir-ing maximum output power, theloading is applied to the amplifierinput. If the performance goal islow noise figure, the resistiveloading is implemented on theoutput side of the INA-12063 asshown in Figure 11.

RFINPUT

RFOUTPUT

STABILIZINGRESISTOR

INA-12063

Figure 11. Shunt Stabilizing Resistorfor LNA.

A simple manual optimizationmay be used to determine astarting value for the stabilizingresistor. By adding a shuntresistor to the output of theINA-12063 in the circuit file usedin the previous stability analysis,K may be observed while adjust-ing the value of the resistor. Theshunt resistor should be thehighest value that will adequatelystabilize the circuit.

The three possible cases resultingfrom the stability analysis willnow be considered.

Case 1 (K>1 over the entirefrequency range) is always thehoped for situation since it is theeasiest to deal with. If K is greaterthan unity by a comfortablemargin, then no further action isneeded at this point.

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Case 2 (K>1 within the band ofinterest; K1 in the bandof interest, little or no perfor-mance tradeoffs may be neededto make the amplifier uncondi-tionally stable.

By using R-C or R-L combina-tions, frequency selective resis-tive loading can be applied onlyover the frequency range forwhich K < 1 in order to stabilizethe amplifier without adverselyaffecting in-band performance.

Case 3 (K 1,the CAD circuit file from designStep 4, including any stabilizingresistors, is used to calculate Γms.

For most communication systemsoperating over relatively smallbandwidths, a single frequencymatch approach is usuallyadequate. As a general rule, theselection of high pass networksfor the input (and output) match-ing circuits is desirable to reduceexcess gain at low frequencies.

As a final note in the choice of theinput matching structure, the useof a series C element is possibleat the input of the INA-12063since the internal bias circuitobviates the need for an externalDC connection to the input.

The choice of using either lumpedelement or distributed (transmis-sion line) matching elements ismainly dictated by size andfrequency constraints as well asby cost considerations. Whiledistributed elements are “free”since they are etched onto thePCB, they usually use more boardspace than an equivalent lumpedelement (chip) component.

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Before proceeding to the nextstep, circuit stability and out-of-band gain should be re-checked.

Step 7. Designing the OutputMatchThe output of the INA-12063 isnormally matched for maximumpower transfer (maximum gainand lowest output VSWR.)Maximum power transfer occurswhen the output is matched tothe conjugate of Γml. Γml iscomputed from the same CADcircuit file as used for determin-ing Γms in the design of the inputmatching network in the previousstep. A typical LNA is matchedfor Γopt at the input and Γml at theoutput.

Note: The small signal match formaximum power transfer shouldnot be confused with matchingthe output of the INA-12063 forthe highest output power. Asoutput power is increased, thedevice becomes nonlinearresulting in a shift away from theΓml match. While various loadpull types of measurements existto determine the optimumimpedance match for maximumoutput power under nonlinearconditions, these tests are fairlytedious and an empirical tuningapproach is often more expedientto arrive at a solution. The Γmlmatch may be used as a startingpoint in tuning for maximumoutput power.

The same comments regardingsingle frequency match, high passnetworks, and lumped vs. distrib-uted elements referred to in theinput matching step above areapplicable to the output matchingcircuit.

Once again, out-of-band gain andstability should be checked.

Step 8. RF LayoutUp to this point, we have com-pleted the RF electrical design,the choice of circuit boardmaterial, and the DC circuit. Thenext step is to lay out the printedcircuit board. While the layout isnot critical, some precautionsshould be considered.

A recommended PCB pad layoutfor the miniature SOT-363 (SC-70)package used by the INA-12063 isshown in Figure 12 (dimensionsare in inches). This layout pro-vides ample allowance for pack-age placement by automatedassembly equipment withoutadding parasitics that could impairthe high frequency RF perfor-mance of the INA-12063. Thelayout is shown with a footprint ofa SOT-363 package superimposedon the PCB pads for reference.

0.026

0.035

0.075

0.016

Figure 12. PCB Pad Layout forINA-12063 Package(dimensions in inches).

Starting with the package padlayout in Figure 12, an RF layoutsimilar to the one in Figure 13 issuggested as a starting point forthe INA-12063 amplifier.

34

16

Figure 13. RF Layout.

This layout shows the directgrounding of Pin 5 (the device RFground) which should be con-nected to ground through as shorta path as practical, unless addi-tional shunt feedback is desired.Capacitive bypasses should beplaced on the DC connections atPins 1 and 4 to prevent possiblefeedback and/or oscillation in theactive bias circuit. Multiple viasare used to ensure good RFgrounding.

It is recommended that the PCBpads for the two ground pins notbe connected together. Eachground pin should have its ownseparate path to ground, other-wise, unintentional feedbackcould lead to potential instabilityin the RF transistor or internalbias circuit.

Step 9. Final CAD Analysisand OptimizationFollowing the completion of theamplifier electrical design andlayout, it is advisable to do a finalCAD analysis and circuit optimi-zation. The analysis at this pointwill take into account such thingsas component parasitics (e.g.,series L in chip caps), actualtransmission line dimensions andinterconnections, effects ofground vias, etc.

The circuit should be analyzedover the full range of the providedS-parameters to re-verify amplifierstability and ensure well-behavedout-of-band performance. Withthe full circuit parasitics andlosses taken into account, it maybe necessary to adjust the valueof the shunt stabilizing resistor.

The results of this final analysisand optimization are then used tomake final adjustments to compo-nent values and the PCB layout as

6-129

well as to ensure that the perfor-mance goals in Step 1 will be met.

Step 10. Build and TestThe final step is to fabricatecircuit boards and assembleamplifiers for testing and verifica-tion of performance. Someadjustment in component valuesand transmission lines may bedone at this step to allow forimperfections in the computersimulation. This completes theamplifier design.

900 MHz LNA Design ExampleAs an application example, thedesign of a low noise amplifierstage for 900 MHz using theINA-12063 will be described. Thisamplifier design would be repre-sentative for use in many low-cost, battery power receiverapplications such as LNAs forcellular telephones or 900 MHzISM/spread spectrum systems.

This example will follow theabove design sequence.

1. Performance goals. As areceiver front end stage, theprimary design goals for thisexample amplifier are: (1) noisefigure less than 2 dB, and, (2) ainput 3rd order intercept (IP3)point of at least -10 dBm. Second-ary goals are low output VSWRand minimum DC current drain.The resulting input VSWR andstage gain will be accepted. Lowcost is always a design goal.

Results of this step:

Constrain:

NF ≤ 2 dBInput IP3 ≥ -10 dBmLow cost

Optimize:

Minimize output VSWRMinimize DC power

Accept:

GainInput VSWR

2. Select bias conditions. Forthis example, the supply voltageis constrained by an assumedbattery supply of 3 volts, leavingdevice current as the only remain-ing bias variable. The current isselected based on output powerwhich is driven by the IP3 require-ment. The table of ElectricalSpecifications provides a startingpoint. Using the typical gain of16␣ dB and a difference of 15 dBbetween the output IP3 and P1dB,the design goal of an input 3rdorder intercept point of -10 dBmis translated to a 1-dB com-pressed output power require-ment of -9 dBm. Figure 8 indi-cates a current of 2.5␣ mA willmeet this P1dB requirement withadequate design margin.


Bias: 3 volts, 2.5 mA

3. Choose PCB material. FR-4with a thickness of 0.031 inches ischosen as the printed circuitboard material. FR-4 meets therequirement of low cost whileproviding acceptable low lossperformance at 900 MHz.

A thickness of 0.031 inches issuitable for the miniaturization ofmicrostriplines and thin enoughto allow for low inductanceground vias. With a relativedielectric constant (εr) of 4.8, thewidth of a 50 Ω microstripline on0.031 inch FR-4 is 0.056 inches,which is a convenient size formounting chip components.


PCB Material: 0.031-inch FR-4

4. Evaluate stability. Stabilityfactor is calculated from the setof S-parameters closest to thechosen bias condition, which inthis example is 3 volts and2.5␣ mA. For the required accuracyin the stability analysis, a shortlength of transmission line(0.030-inch long, 0.015-inch wide)is added to connect the RFground pin (Pin 5) of theINA-12063 to a 0.025-inch diam-eter ground via.

Hewlett-Packard’s TouchstoneCAD program was used tocalculate the stability factor (K),stability measure (B1), and gainover the full S-parameter fre-quency range of 0.1 to 3.1 GHz.The results show a value of K50␣ Ω, a resistor in the shuntconfiguration is used to move theoverall impedance closer to 50␣ Ω.

RFINPUT

W = 0.015L = 0.030

0.025" DIA.GROUND VIA

RFOUTPUT

R1GND 1(PIN 5)

INA-12063

Figure 14. Stabilizing Resistor onOutput.

6-130

The Touchstone circuit file forthis step is shown in Figure 15.

DIM FREQ GHZ RES OH LNG IN CKT MSUB ER=4.8 H=0.031

T=0.001 RHO=1 RGH=0 S2P 1 2 3 TYP25B.S2P MLIN 3 4 W=0.015 L=0.030 VIA 4 0 D1=0.025

D2=0.025 H=0.031T=0.001

RES 2 0 R=600 ! R1 DEF2P 1 2 INA12 TERM Z0 = 50 OUT INA12 K INA12 B1 INA12 DB[S21] INA12 DB[GMAX] ! INA12 MAG[GMN] ! INA12 ANG[GMN] ! INA12 MAG[GM2] ! INA12 ANG[GM2] FREQ SWEEP 0.1 3.1 0.1

Figure 15. CAD File for StabilityAnalysis and Conjugate Match.

The value of the shunt resistor,R1, is varied while observing theresulting K. While a 600 Ω resistoris found to stabilize the circuit at900 MHz (K=1.46), there stillexists a possibility of oscillationat 100 MHz with the worst casevalue of K = 0.72. There are twooptions at this point: (a) lowerthe value of the shunt resistor,which trades additional stabilityfor circuit gain and output power,or (b) use a frequency selectivecircuit to resistive load the deviceonly at lower frequencies.

In the interest of circuit simplicity(meeting the objective of lowcost) the shunt resistor value was

lowered to 290 Ω. This valueresulted in a K > 1 over the fullfrequency range at a trade-off ingain of 1.7 dB. (The stabilitymeasure criteria, B1 > 0, was alsoverified.)


A 290 Ω shunt resistor was addedto the output of the INA-12063 forstability.

5. Allow for DC connections.The required DC connections tobe made to this example amplifierare: +3 volts to the RF Outputand Vd terminals (Pins 4 & 6), asuitable bias current into Ibias(Pin 1), and Pins 2 and 5 toground. The RF Input (Pin 3) andRF Output should have blockingcapacitors if the amplifier is to becascaded with stages that do nothave a DC open circuit.

To set the INA-12063 operatingcurrent to 2.5 mA, a 9.1␣ K Ωresistor will be connected be-tween the +3 volt supply and theIbias pin. The DC schematic forthe LNA is shown in Figure 16.

Figure 16. 900 MHz LNA DCSchematic.


The DC connections were identi-fied and will be considered inchoosing the input & outputmatching circuits.

6. Design of the input imped-ance matching network.Commensurate with the primarydesign objective of low noisefigure, the 50 Ω input to theamplifier stage will be matched tothe conjugate of Γopt. The valueof Γopt, 0.53 ∠+36°, is found inthe table of Typical Noise Param-eters for a bias current of 2.5 mA.(Alternatively, a slightly moreaccurate Γopt could also havebeen calculated using the CADcircuit file in Figure 15, whichincludes the RF ground parasiticsand stabilizing resistor.) Theconjugate of Γopt, 0.53 ∠−36°, isplotted on the Smith chart asPoint A in Figure 17. Since PointA is not sufficiently close to theR=1 or G=1 circles on the Smithchart, a single series or shuntelement will not provide an exactmatch. (For less critical NFperformance, a simple seriesinductor would be adequate forthe input match.) A two-elementmatching network will thereforebe required.

Impedances in this region of theSmith chart can be matched to50␣ Ω by either of two possible L-Ccombinations, either a shuntC-series L or a shunt L-series C.Normally, the shunt L-series Cwould be a good choice since itshigh pass filter characteristicwould help roll off excess lowend gain. However, a DC blockingcapacitor would be requiredbetween the INA-12063 and thematching network. Placingextraneous components withinmatching network is usually notrecommended. The shunt C-seriesL network is therefore chosen asthe input matching topology.

6-131

A

1

C

C (50 Ω) B A (Γopt*)

2

1

-2

B

0.5

0.5

0.2

-0.2

0.2 2

-0.5

-1

RFInput L1 C1

Figure 17. Input Impedance Match.

As shown in Figure 17, a shuntcapacitor of 0.59 pF will moveΓopt * at Point A to a position onthe unit conductance circle (G=1)at Point B. A 11.2 nH seriesinductor then completes thematch to 50 Ω by moving theimpedance at Point B to thecenter of the chart.

The value of the shunt capacitoris small enough that a shortlength of open-circuit transmis-sion line could be used in place ofthe lumped element capacitor.This saves the expense of a chipcomponent with the tradeoff of asmall amount of additional circuitboard space. A 0.20-inch length ofopen-circuit 50 Ω line is onechoice that would be equivalentto the 0.59 pF shunt capacitor.The input matching circuit isshown in Figure 19.


The input circuit is:

RFINPUT

11.2 nH

0.59 pF

Figure 18. Input Circuit.

7. Design of the outputimpedance matching network.Using the circuit file from step 4(Figure 15), Touchstone was usedto calculate the load impedanceΓml (0.62 ∠+35°) of the INA-12063to achieve maximum powertransfer. The conjugate of Γml,Γml* (0.62 ∠-35°), is plotted asPoint A on the Smith chart inFigure 19.

A

1

C

B

2

1

-2

B

0.5

0.5

0.2

-0.2

0.2 2

-0.5

-1

RFOutputC2L2

C (50 Ω)A (Γml*)

Figure 19. Output Impedance Match.

The two possible L-C networksthat can be used to match Γml* to50 Ω are either a shunt C-series Lor a shunt L-series C circuit. Bychoosing the shunt L-series Ccircuit, two of the DC consider-ations from Step 5 can be satis-fied: the shunt L can be bypassedand used to apply the +3 voltsupply to the RF output terminal,and the series C will serve doubleduty as the DC blocking capacitor.

Referring again to Figure 19, ashunt inductance of 10.8 nHmoves Γml* at Point A to Point Bwhich is on the G1 circle of theSmith chart. The addition of1.9␣ pF of series capacitancecompletes the impedance trans-formation to Point C at the centerof the chart. The output matchingcircuit is shown in Figure 20.


The output circuit is:

RFOUTPUT11.2 nH

0.59 pF

Figure 20. Output Circuit.

The circuit values from this stepand from Step 6 will be used as astarting point to be refined inStep 9 when the circuit is ex-panded to take practical intercon-nections and parasitics intoaccount.

8. PCB Layout. The results ofthe preceding steps and the PCBlayout guidelines in design Step 8were used to draft the circuitboard layout shown in Figure 21.Since parasitic effects are mini-mal, the current source resistor,R2, can be conveniently placeddirectly from the RF output to theIbias connection. A bypass capaci-tor is added to the shunt stabiliz-ing resistor, R1 and matchinginductor, L2, on the output. A DCblocking capacitor, C1, is in-cluded at the input to completethe amplifier.

Figure 21. PCB Layout of 900 MHzLNA.


PCB layout completed.

6-132

9. Final CAD simulation andoptimization. With reference toFigure 21 the CAD circuit filefrom step 4 is embellished toinclude the effects of componentmounting pads, lengths of trans-mission lines used to intercon-nect components, ground vias,bypass and blocking capacitors,etc. (Since 900 MHz is a fairlymoderate frequency, extremelyfine detail is not required.)

Using the previous elementvalues for the matching circuitsas a starting point, Touchstonewas used to optimize the circuitfor noise figure and output match,which were the primary designgoals from Step 1. The input andoutput matching elements wereused as variables for the optimi-zation. Following the optimiza-tion, the value of the stabilizingresistor, R1, was also reviewedand it was found that an increaseto 330 Ω was sufficient to makeK>1 over the entire frequencyrange of the S-parameters. TheTouchstone circuit file for thecomplete amplifier is shown inAppendix A and the simulationresults in Appendix B.

The schematic for the completeINA-12063 amplifier circuit isshown in Figure 22.

A final simulation using optimizedcomponent values predictedperformance of the amplifier at900 MHz to be:

NF = 1.6 dBGain = 13.4 dBMAG = 14.1 dBInput RL = 8.4 dBOutput RL = 31 dB


Optimization of circuit andverification of performance goals.

10. Assemble and test. Acircuit based on the PCB layoutwas assembled using componentswith standard values that wereclosest to those resulting fromthe circuit optimization.

The test results compared wellwith the computer simulationsfrom the previous step. For thisparticular circuit, it was deter-mined experimentally that lessshunt capacitance was required atthe input than predicted by theCAD analysis. As a result, theshunt, open circuit stub near Pin 3was shortened to tune the circuitfor minimum noise figure. Thefinal LNA is shown in Figure␣ 23.

Figure 23. Completed 900 MHz LNA.

6-133

Actual, measured test results areshown in Figures 24 through 28.Output power for 1 dB of gaincompression (P1dB) at 900 MHzwas measured as -4.6 dBm.

FREQUENCY (MHz)

0

5

10

20

15

GA

IN (

dB

)

850800 900 950 1000

Figure 24. Measured Gain of Example900 MHz LNA.

FREQUENCY (MHz)

0

1

2

4

3

NO

ISE

FIG

UR

E (

dB

)

850800 900 950 1000

Figure 25. Measured Noise Figure ofExample 900 MHz LNA.

FREQUENCY (MHz)

-35

-15

-10

0

-5Input

Output

-30

-25

-20|Sii|

2 (d

B)

850800 900 950 1000

Figure 26. Measured Input andOutput Return Loss of Example900␣ MHz LNA.

FREQUENCY (MHz)

-5

5

10

20

15

0

GA

IN (

dB

)500100 900 1300 1700 2100

Figure 27. Measured Gain of Example900 MHz LNA for Extended Frequency.

FREQUENCY (MHz)

-20

-15

-10

0

-5

|Sii|

2 (d

B)

500100 900 1300 1700 2100

Input

Output

Figure 28. Measured Input and OutputReturn Loss of Example 900␣ MHz LNAfor Extended Frequency.

Results of this step:A prototype circuit was built andperformance goals verified bymeasurement. The following900␣ MHz data was measured onthe example LNA:

NF = 1.9 dBGain = 14.7 dBP1dB (output) = -4.6 dBmInput Return Loss = 9.6 dB

(Input VSWR = 2.0 : 1)Output Return Loss = 20.4 dB

(Output VSWR = 1.2 : 1)DC Power = 8 mW

(3 volts, 2.55 mA)

Hints and Troubleshooting• OscillationEven though a design may beunconditionally stable (K > 1 andB1 > 0) over its full frequencyrange, other possibilities existthat may cause an amplifiercircuit to oscillate. One thing tolook for, is oscillation in biascircuits. It is important to capaci-tively bypass the connections toactive bias circuits to ensurestable operation. In multistagecircuits, feedback through biaslines can also lead to oscillation.

Components of insufficientquality for the frequency range ofthe amplifier can sometimes leadto instability. Also, componentvalues that are chosen to be muchhigher in value than is appropri-ate for the application canpresent a problem. In both ofthese cases, the components mayhave reactive parasitics that maketheir impedances very differentthan expected. Chip capacitorsmay have excessive inductance,or chip inductors can exhibitresonances at unexpectedfrequencies.

In systems with high gain cas-cades, another possible feedbackpath that could lead to oscillationis radiation. Feedback via radia-tion is most frequently encoun-tered in situations where a largecavity housing is used in combi-nation with multiple gain stages.One solution to minimizingradiation feedback is to designthe housing so that it is wellbelow its equivalent waveguidecutoff frequency. Another solu-tion is to use shielding to parti-tion the gain.

6-134

• A Note on Supply LineBypassingWhen multiple bypass capacitorsare used throughout the powersupply lines in a wireless system,consideration should be given topotential resonances. It is impor-tant to ensure that the capacitors,when combined with additionalparasitic L’s and C’s on the circuitboard, do not form resonantcircuits. The addition of a smallvalue resistor in the bias supplyline between bypass capacitorswill often “de-Q” the bias circuitand eliminate resonance effects.

SMT AssemblyReliable assembly of surfacemount components is a complexprocess that involves manymaterial, process, and equipmentfactors, including: method ofheating (e.g., IR or vapor phasereflow, wave soldering, etc.)circuit board material, conductorthickness and pattern, type ofsolder alloy, and the thermalconductivity and thermal mass ofcomponents. Components with alow mass, such as the SOT-363package, will reach solder reflowtemperatures faster than thosewith a greater mass.

The INA-12063 is has beenqualified to the time-temperatureprofile shown in Figure 29. Thisprofile is representative of an IRreflow type of surface mountassembly process.

After ramping up from roomtemperature, the circuit boardwith components attached to it(held in place with solder paste)passes through one or morepreheat zones. The preheat zonesincrease the temperature of theboard and components to preventthermal shock and begin evapo-rating solvents from the solderpaste. The reflow zone brieflyelevates the temperature suffi-ciently to produce a reflow of thesolder.

The rates of change of tempera-ture for the ramp-up and cool-down zones are chosen to be lowenough to not cause deformationof the board or damage to compo-nents due to thermal shock. Themaximum temperature in thereflow zone (TMAX) should notexceed 235°C.

These parameters are typical fora surface mount assemblyprocess for the INA-12063. As ageneral guideline, the circuit

board and components should beexposed only to the minimumtemperatures and times neces-sary to achieve a uniform reflowof solder.

Statistical ParametersSeveral categories of parametersappear within this data sheet.Parameters may be describedwith values that are eitherminimum or maximum, “typical,”or standard deviations.

The values for parameters arebased on comprehensive productcharacterization data, in whichautomated measurements aremade on of a minimum of 500parts taken from 3 non-consecu-tive process lots of semiconduc-tor wafers. The data derived fromproduct characterization tends tobe normally distributed, e.g., fitsthe standard bell curve.

Parameters considered to be themost important to system perfor-mance are bounded by minimumor maximum values. For theINA-12063, these parameters are:Power Gain (|S21|2), Noise Figure(NF), and Device Current. Eachof these guaranteed parameters is100% tested.

Values for most of the parametersin the table of Electrical Specifi-cations that are described bytypical data are the mathematicalmean (µ), of the normal distribu-tion taken from the characteriza-tion data. For parameters wheremeasurements or mathematicalaveraging may not be practical,such as S-parameters or NoiseParameters and the performancecurves, the data represents anominal part taken from thecenter of the characterizationdistribution. Typical values areintended to be used as a basis forelectrical design.

TIME (seconds)

TMAX

TE

MP

ER

AT

UR

E (

°C)

00

50

100

150

200

250

60

PreheatZone

Cool DownZone

ReflowZone

120 180 240 300

Figure 29. Surface Mount Assembly Profile.

6-135

To assist designers in optimizingnot only the immediate circuitusing the INA-12063, but to alsooptimize and evaluate trade-offsthat affect a complete wirelesssystem, the standard deviation(σ) is provided for many of theElectrical Specifications param-eters (at 25°C) in addition to themean. The standard deviation is ameasure of the variability aboutthe mean. It will be recalled that anormal distribution is completelydescribed by the mean andstandard deviation.

Standard statistics tables orcalculations provide the probabil-ity of a parameter falling betweenany two values, usually symmetri-cally located about the mean.Referring to Figure 30 for ex-ample, the probability of aparameter being between ± 1σ is68.3%; between ± 2σ is 95.4%; andbetween ± 3σ is 99.7%.

68%

95%

99%

Parameter Value

Mean (µ), typ

-3σ -2σ -1σ +1σ +2σ +3σ

Figure 30. Normal Distribution.

Phase Reference PlanesThe positions of the referenceplanes used to specify S-param-eters and Noise Parameters forthe INA-12063 are shown inFigure 31. As seen in the illustra-tion, the reference planes arelocated at the point where thepackage leads contact the testcircuit.

TEST CIRCUIT

REFERENCEPLANES

Figure 31. Phase Reference Planes.

Test CircuitsThe test circuit shown in Fig-ure␣ 32 is used for 100% testing ofthe guaranteed RF and DCparameters that are shown in theTable of Electrical Specifications.

RFINPUT

RFOUTPUT

8.2 nH

5.6 kΩ

10 nF 100 pF

8.2 nH500 Ω

1 nF

1 nF

2.2 pF

+3 V

+3 V

+3 V

12

Figure 32. 900 MHz Test Circuit.

The test circuits in Figures 32 and33 were used to generate thecharacterization data and perfor-mance curves for 900 MHz and250 MHz.

RFINPUT

RFOUTPUT

180 nH

150 Ω

5.6 pF

16 kΩ

10 nF 100 pF

39 nH330 Ω

1 nF

1 nF

5.6 pF

+3 V

+3 V

+3 V

12

Figure 33. 250 MHz Test Circuit.

Electrostatic SensitivityRFICs are electro-static discharge(ESD) sensitivedevices. Although theINA-12063 is robust in design,permanent damage may occur tothese devices if they are sub-jected to high energy electrostatic

discharges. Electrostatic chargesas high as several thousand volts(which readily accumulate on thehuman body and on test equip-ment) can discharge withoutdetection and may result indegradation in performance,reliability, or failure.

Electronic devices may besubjected to ESD damage in anyof the following areas:

• Storage and handling• Inspection and testing• Assembly• In-circuit use

The INA-12063 is a ESD Class 1device. Therefore, proper ESDprecautions are recommendedwhen handling, inspecting,testing, assembling, and usingthese devices to avoid damage.

The in-use aspect of potentialESD damage is sometimes over-looked. One such example ofpossible damage is in the use ofan ESD sensitive device as thefront-end LNA stage in personalcommunication equipment, suchas cellular telephones, PCS, or RFmodems.

The input to receiver LNAs arefrequently connected to externalantennas that are subject tohuman contact and exposure toother potentially damaging levelsof ESD. If this type of conditionexists, some type of circuitprotection may be needed. Onesimple method of preventing ESDdamage is to add a DC returnpath (e.g., a shunt inductor) tothe input of the receiver. Thistype of protection may be inte-grated into other parts of thereceiver front end, such as in aT/R switch, filter, or the inputmatching network to the LNA.

6-136

Appendix A - Touchstone Circuit File.

! Hewlett-Packard CMCD! Bob Myers 20 Sept 1996!! HP Touchstone circuit file! INA-12063 Single Stage LNA! fc = 900 MHz, Vc = 3.0 V, Ic = 2.5 mA! Input Matched for NF

DIM FREQ GHZ RES OH CAP PF IND NH LNG IN ANG DEG

VAR! Input match L1# 0 12.6477 20 A1# 0 0.201808 0.4 ! Length of MLOC! C1# 0 0.636904 10! Output match L2# 0 9.25249 20 C2# 0 2.56665 10

CKT MSUB ER=4.8 H=0.031 T=0.001 RHO=1 RGH=0 MLIN 1 2 W=0.056 L=0.300 CAP 2 3 C=300 ! Input DC block MLIN 3 4 W=0.056 L=0.100 IND 4 5 L^L1 ! L1 in Input match MLOC 5 W=0.04 L^A1 ! Z1 in Input match! CAP 5 0 C^C1 ! Alternate shunt C MLIN 5 6 W=0.04 L=0.020 S2P 6 7 8 C:\SPARA\A120633B.S2P RES 7 0 R=9100 ! R1 bias resistor MLIN 8 9 W=0.020 L=0.035 ! Z2 in RF ground VIA 9 0 D1=0.025 D2=0.025 H=0.031 T=0.0015 W=0.04 MLIN 7 10 W=0.06 L=0.100 RES 10 12 R=330 ! R2 Stabilizing R MLIN 10 11 W=0.056 L=0.065 IND 11 12 L^L2 ! L2 in Output match MLIN 11 15 W=0.056 L=0.050 CAP 12 13 C=300 ! Bypass C MLIN 13 14 W=0.050 L=0.020 VIA 14 0 D1=0.025 D2=0.025 H=0.031 T=0.001 W=0.04 CAP 15 16 C^C2 ! C2 in Output match MLIN 16 17 W=0.056 L=0.300 DEF2P 1 17 INA12

TERM Z0 = 50

OUT INA12 NF GR3 INA12 DB[S21] GR1 INA12 DB[S11] GR2 INA12 DB[S22] GR2 INA12 DB[GMAX] GR1

6-137

INA12 K ! Stability factor (K > 1) INA12 B1 ! Stability Measure (B1 > 0)

FREQ SWEEP 0.1 3.1 0.02

GRID FREQ 0.8 1.0 0.05! FREQ 0.1 3.1 0.1 GR1 0 20 5 ! Gain GR2 0 -40 10 ! Return loss GR3 0 4 1 ! NF

OPT FREQ 0.85 0.95 INA12 NF

6-138

INA-12063 Part Number Ordering Information Part Number Devices per Container Container

INA-12063-TR1 3000 7" reel

INA-12063-BLK 100 tape strip inantistatic bag

Package DimensionsOutline 63 (SOT-363/SC-70)

2.20 (0.087)2.00 (0.079)

1.35 (0.053)1.15 (0.045)

1.30 (0.051)REF.

0.650 BSC (0.025)

2.20 (0.087)1.80 (0.071)

0.10 (0.004)0.00 (0.00)

0.25 (0.010)0.15 (0.006)

1.00 (0.039)0.80 (0.031)

0.20 (0.008)0.10 (0.004)

0.30 (0.012)0.10 (0.004)

0.30 REF.

10°

0.425 (0.017)TYP.

DIMENSIONS ARE IN MILLIMETERS (INCHES)

6-139

Tape Dimensions and Product OrientationFor Outline 63

Device Orientation

USERFEED DIRECTION

COVER TAPE

CARRIERTAPE

REEL END VIEW

8 mm

4 mm

TOP VIEW

12 12 12 12

Fyd

A4

F

J

E

DC

P

P

P0

P2

FW

C

D1

D

E

A0

8° MAX.

t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS)

5° MAX.

B0

K0

DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)

LENGTHWIDTHDEPTHPITCHBOTTOM HOLE DIAMETER

A0B0K0PD1

2.24 ± 0.102.34 ± 0.101.22 ± 0.104.00 ± 0.101.00 + 0.25

0.088 ± 0.0040.092 ± 0.0040.048 ± 0.0040.157 ± 0.0040.039 + 0.010

CAVITY

DIAMETERPITCHPOSITION

DP0E

1.55 ± 0.054.00 ± 0.101.75 ± 0.10

0.061 ± 0.0020.157 ± 0.0040.069 ± 0.004

PERFORATION

WIDTHTHICKNESS

Wt1

8.00 ± 0.300.255 ± 0.013

0.315 ± 0.0120.010 ± 0.0005

CARRIER TAPE

CAVITY TO PERFORATION(WIDTH DIRECTION)

CAVITY TO PERFORATION(LENGTH DIRECTION)

F

P2

3.50 ± 0.05

2.00 ± 0.05

0.138 ± 0.002

0.079 ± 0.002

DISTANCE

WIDTHTAPE THICKNESS

CTt

5.4 ± 0.100.062 ± 0.001

0.205 ± 0.0040.0025 ± 0.00004

COVER TAPE

List of Figures1. Gain vs. Frequency2. Input Return Loss vs. Frequency3. Output Return Loss vs. Frequency4. Gain at 900 MHz vs. Voltage and Temperature5. Noise Figure at 900 MHz vs. Voltage and Temperature6. Output P1dB at 900 MHz vs. Voltage and Temperature7. Supply Current vs. Voltage and Temperature8. Output P1 dB at 900MHz vs. Device Current for Vd = 3 V9. INA-12063 Schematic.10. Single-Resistor Bias Circuit11. Shunt Stabilizing Resistor for LNA12. PCB Pad Layout for INA-12063 Package13. RF Layout14. Stabilizing Resistor on Output15. CAD File for Stability Analysis and Conjugate Match16. 900 MHz LNA DC Schematic17. Input Impedance Match18. Input Circuit19. Output Impedance Match20. Output Circuit21. PCB Layout of 900 MHz LNA22. 900 MHz Amplifier Schematic23. Completed 900 MHz LNA24. Measured Gain of Example 900 MHz LNA25. Measured Noise Figure of Example 900 MHz LNA26. Measured Input and Output Return Loss of Example 900 MHz LNA27. Measured Gain of Example 900 MHz LNA for Extended Frequency28. Measured Input and Output Return Loss of Example 900 MHz 29. Surface Mount Assembly Profile30. Normal Distribution31. Phase Reference Planes32. 900 MHz Test Circuit33. 250 MHz Test Circuit

FeaturesApplicationsEquivalent CircuitSurface Mount Package SOT-363Pin Connections and Package MarkingDescriptionINA-12063 Absolute Maximum RatingsElectrical SpecificationsINA-12063 Typical PerformanceINA-12063 Typical Scattering Parameters [1] , IC = 1.5 mATypical Noise Parameters @ 900 MHz, IC = 1.5 mAINA-12063 Typical Scattering Parameters [1] , IC = 2.5 mATypical Noise Parameters @ 900 MHz, IC = 2.5 mAINA-12063 Typical Scattering Parameters [1] , IC = 5 mATypical Noise Parameters@ 900 MHz, IC= 5 mAINA-12063 Typical Scattering Parameters [1] , IC = 8 mATypical Noise Parameters @ 900 MHz, IC = 8 mAINA-12063 Applications InformationDescriptionSetting the Bias CurrentPowerDownAmplifier Application Guidelines900 MHz LNA Design Example

Hints and TroubleshootingPhase Reference PlanesTest CircuitsElectrostatic SensitivityAppendix A - Touchstone Circuit FileAppendix B – Touchstone Output FileINA-12063 Part Number Ordering InformationPackage Dimensions

INA-12063: 1.5 GHz Low Noise Self-Biased Transistor Amplifier · 2006. 7. 19. · INA-12063...

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Transcript of INA-12063: 1.5 GHz Low Noise Self-Biased Transistor Amplifier · 2006. 7. 19. · INA-12063...