I.MX INDUSTRY-LEADING PROCESSOR SOLUTION FOR …€¦ · System Control Boot ROMs Security HAB,...
Transcript of I.MX INDUSTRY-LEADING PROCESSOR SOLUTION FOR …€¦ · System Control Boot ROMs Security HAB,...
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COMPANY CONFIDENTIAL
I.MX INDUSTRY-LEADING PROCESSOR
SOLUTION FOR AUTOMOTIVE
APPLICATIONS
NXP Technology Day - Paris
November 21st, 2019
Julie Duclercq
EMEA i.MX Automotive Business Development Director
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i.MX Explosive Growth to Date i.MX 8 is more Scalable, Safe and Secure
Ease of Development for Future Auto Cockpit New Capabilities for HMI and Vision
Over 600M i.MX shipped.
Over 200M i.MX shipped in vehicles since 2007.
#1 in Auto Infotainment Applications Processors
#1 in Reconfigurable Clusters
Growth with scalable ruggedized solutions, well-
trusted for HMI, machine vision, machine
learning, and industrial control solutions.
Additional Auto usage in Telematics, V2X,
Smart Antenna, Driver Monitoring, Surround
View, HMI, Gateway, ADAS (GM Super Cruise)2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
i.MX i.MX Auto
Scalability, Trusted Supply & Best Support
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i.MX8QuadMax device Dual-A72Quad-
A53
CCI
HSIO
LSIO Audio
DMAVPU
Disp#0
Imaging
GPU#0
GPU#1
Disp#1
SCU
Conn.
DBLogCM4
#0
CM4#1
DRC#0
DRC#1
Switch matrix
• Each device in i.MX8 family has
− 1x switch matrix (DB – DRAM Bus) where all subsystems are plugged-in
− 1x SCU (System Controller Unit) which manages boot, resource partitioning and access control, power, clock and reset, IO configuration and muxing, thermal of the device
− Up to 16x subsystems (including SCU)
− 1x or 2x DRAM controller(s)
• All devices in i.MX8 family are following the same structure
− Subsystems are scaled or replaced
• Maximum SW reuse
▪ Reused subsystem have same address mapping, same interrupt mapping…
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i.MX 8 Family of Automotive Applications Processors
So
ftwa
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om
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Pin
Co
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atib
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Op
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VX
an
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I Vis
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Acce
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Family of Scalable Automotive Multimedia Processors
eCockpit
Infotainment
Graphical Instrument Clusters
8QuadMax
8QuadPlus
• Dual Core GPU
• 16 Vec4 Shaders
• Up to 128 GFLOPS
• 64 execution units
• High Speed
• Tessellation / Geometry
Shaders
• Dual Core GPU
• 16 Vec4 Shaders
• Up to 80 GFLOPS
• 64 execution units
• Full Speed
• Tessellation/Geometry
Shaders
8
8
Audio DSP
Audio DSPUp to 4 displays
Up to 4 displays
total pixels
total pixels
SoC Level
OS
OS
OSSoC
Core
SoC Level
OS
OS
OSSoC
Core
HiFi 4
ARM CPU
Cortex-M4 | Cortex-A53 | Cortex-A72
Display DSP Option VirtualizationGPU
8
8
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i.MX 8QuadMax i.MX 8QuadPlus
i.MX 8 Family – Block Diagrams
1x8 Shader
OGL, Vulkan
VX Extensions
1x8 Shader
OGL, Vulkan
VX Extensions
Documentation available on nxp.com
48 KB L1-I
Feature
Package29x29 Flip-Chip BGA
0.75mm pitch29x29 Flip-Chip BGA
0.75mm pitch
DMIPS (Cortex-A) 32k 23k
ARM® Core
Complex 14x Cortex-A53 4x Cortex-A53
ARM® Core
Complex 22x Cortex®-A72 1x Cortex-A72
Display Controller 2x 2x
GPU2x GC7000 XS/VX High
Speed2x GC7000 XS/VX Full Speed
MIPI CSI 2x 4-lane 2x 4-lane
MLB150 1x 1x
HDMI In 1x 1x
HDMI/eDP Out 1x 1x
DDR 2x x32 2x x32
PCIe 2x PCIe 3.0 2x PCIe 3.0
SATA 1x SATA3 1x SATA3
Ethernet 2x 1Gb w/AVB 2x 1Gb w/AVB
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INTERNAL/PROPRIETARY 8
ECOCKPIT SOLUTION
WITHOUT HYPERVISOR
BASED ON I.MX 8QM
HARDWARE PARTITIONING
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Resource Partitioning Concept on i.MX 8
How Partitioning Works:
• The system controller commits
peripherals and memory regions
into a specific domains.
(This is customer defined)
• Any communication between domains
are forced to use messaging protocols
• If a domain peripheral tries to access
other domains illegally, a bus error will occur.
Benefits of Partitioning:
• Reporting of immediate illegal accesses helps
track down hard to find race conditions before
they go to production. (AKA Sandbox Methods)
• Provides security on a finished product: protects
system critical SoC peripherals from less trusted
apps
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NXP eCockpit solution objective
• NXP eCockpit solution leverages i.MX 8QM HW partitioning capabilities and
allows to run on the same SoC, without using a SW Hypervisor solution, several
concurrent OS based applications (Instrument Cluster, Infotainment, Vehicle
Services, SafeAssure Display/Camera), fully utilizing all cores and IP’s of the i.MX
8QM SoC.
• These applications run within their own domain, have a set of IP’s and peripherals
assigned to their exclusive usage, and can be started and rebooted independently
from each other.
• The eCockpit solution is fully scalable and allows to create partitioned domains
required by the selected eCockpit architecture.
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NXP AND ART TURBOCHARGE A
COMPLETELY IMMERSIVE
INFOTAINMENT EXPERIENCE IN
LUXURY SPORTS CARS
ARTIST 8 Development
platform uses i.MX 8QuadMax
• Secure domain partitioning
• Unique deployment of multi-OS
platforms on a single processor
• Advanced automotive
dashboard graphics
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Advanced Domain Separation with i.MX 8QuadMax/QuadPlusIndustry Standard Hypervisor Solutions for Maximum Flexibility
A53
CPU1
A53
CPU2
Platform 1 Platform 2
A53
CPU3
A53
CPU4
A72
CPU0
A72
CPU1
GPU 0 GPU 1
Display 1Display 0
Periph
Periph
Periph
Periph
Periph
Periph
Periph
Periph
Challenging Graphics
and Display Tasks can
be Separated into
Resource Domains
i.MX 8QM/QP
Hypervisors + SMMU on i.MX 8 = thin, light, let hardware do the underlying work
i.MX 8’s SMMU Architecture and
Independent GPU & Display Control
Eases Hypervisor Implementations
• Hypervisors allow flexibility in sharing
ARM A-CPU resources
• Dual 3D GPUs and Display Controllers
can operate independently
• Multiple developments in progress at
3rd parties
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Advanced Domain Separation with i.MX 8QuadMax/QuadPlusIndustry Standard Hypervisor Solutions for Maximum Flexibility
A53
CPU1
A53
CPU2
Platform 1 Platform 2
A53
CPU3
A53
CPU4
A72
CPU0
A72
CPU1
GPU 0 GPU 1
Display 1Display 0
Periph
Periph
Periph
Periph
Periph
Periph
Periph
Periph
Challenging Graphics
and Display Tasks can
be Separated into
Resource Domains
i.MX 8QM/QP
Hypervisors on i.MX 8 = thin, light, let hardware do the underlying work
• NXP releasing also
opensource XEN, KVM,
Jailhouse - porting on
i.MX8/8x MEK boards
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i.MX 8X Family of Applications ProcessorsS
oftw
are
Co
mp
atib
ility
Pin
Com
pa
tibility
8QuadXPlus
• Single Core GPU
• 4 Vec4 Shaders
high performance
• 16 execution units
• OpenGL ES 3.1
• OpenCL Embedded
USBGPU ARM CPU
Cortex-A35 + M4
8DualXPlus
• Single Core GPU
• 4 Vec4 Shaders
high performance
• 16 execution units
• OpenGL ES 3.1
• OpenCL Embedded
Video DSP
HiFi 4
DDR
x32
DDR3L-1866
(ECC option)
LP-DDR4-2400
(no ECC)
x32
DDR3L-1866
(ECC option)
LP-DDR4-2400
(no ECC)HiFi 4
4
4
Displays
Up to 3
2x 1080p1x WVGA
Up to 3
2x 1080p1x WVGA
+ Legacy
+ Legacy
Family of Scalable Automotive Multimedia Processors
Display Audio Applications
Graphical Instrument Clusters
Telematics and V2X
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Display & Camera I/O
i.MX 8X Family Block Diagram
System Control
Boot ROMs
Security
HAB, SRTC, SJTAG, TrustZone
AES256, RSA4096, SHA-512
Flashless SHE, ECC
Tamper detection, Inline Enc Engine
3DES, ARC4, MD-5
Power Control, Clocks, Reset
Connectivity
4x SAI, ESAI, MQS
MOST 25/50
3x CAN/CAN FD
2x Gbit Ethernet
1 or 2x USB2 OTG w/PHY
4x UART
3.3V / 1.8V GPIO
4x SPI
PCIe 3.0 with L1 Substate (1-lane)
Memory
DDR3 @933 MHz (ECC Option)
LPDDR4 @ 1200 MHz (no ECC)
2x SDIO3.0/eMMC5.1
2x Quad / 1x Octal SPI
PMIC interface (dedicated I2C)
Resource Domain Partitioning
8x I2C
Core Complex 1
512KB L2 w/ECC
32KB L1-D4x Cortex-A53
32KB L1-I 32KB L1-D32KB L1-D2-4x Cortex-A35
32KB L1-I 32KB L1-D
16KB L1 I-cache
1x Cortex-M4F
16KB L1 D-cache
1x I2C
Core Complex 2
Multimedia
VPU
Video: h.265 dec 4k
h.264 dec/enc 1080p
GPU
4- Shaders
OpenGL ES 3.1 Vulkan®
1x Tensilica®
HiFi 4 DSP
512 KB SRAM 64KB TCM
32KB I
Audio
2 x MIPI-DSI/LVDS Combo PHY*
4x PWM
4x4 Keypad
RAW NAND – BCH62 1x USB3 OTG w/PHY
1x 12-bit ADC
2x ASRC, SPDIF
1x Parallel Display
48KB D
Display Processor w/ SafeAssure®
1x MIPI CSI
1x Parallel CSI
256KB SRAM
1x UART
6x GPIO
1x TPM Timer
* Each single PHY can either be a 1×4 lane MIPI-DSI or a 1×1 channel LVDS interface for a total of 2 display interfaces.
In combination, the two PHYs can be configured to be a single 2-channel LVDS interface.
Varies by device
1x 10/100 Ethernet
*21x21, 0.8p package only.
17x17, 0.8p package variant will have 16-bit memory interface.
Feature
ARM® Core
2 x Cortex-A35 (i.MX 8DualXPlus)
4 x Cortex-A35 (i.MX 8QuadXPlus)
2 x Cortex-A35
ARM® Core 1 x Cortex-M4F 1 x Cortex-M4F
DSP Core Tensilica® HiFi 4 DSP Tensilica HiFi 4 DSP
DRAM*32-bit DDR3L (ECC option)/
LPDDR4 (no ECC)
16-bit DDR3L (no ECC) LPDDR4
(no ECC)
GPU1 x GC7000Lite
High Performance
1 x GC7000Lite
Power Optimized
VPU4K h.265 dec, 1080p h.264
enc/dec
1080p h.264 enc/dec
Ethernet 2 x Gigabit with AVB1 x Gigabit with AVB
1 x 10/100
USB with
PHY
1 x USB 3.0 (or USB 2.0)
1 x USB 2.02 x USB 2.0
i.MX 8DualXPlus /
i.MX 8QuadXPlusi.MX 8DualX
Documentation available on nxp.com
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INTERNAL/PROPRIETARY 17
LOW END eCOCKPIT
on i.MX 8X
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i.MX 8X Family of Applications ProcessorsS
oftw
are
Co
mp
atib
ility
Pin
Com
pa
tibility
8QuadXPlus
• Single Core GPU
• 4 Vec4 Shaders
high performance
• 16 execution units
• OpenGL ES 3.1
• OpenCL Embedded
USBGPU ARM CPU
Cortex-A35 + M4
8DualXPlus
• Single Core GPU
• 4 Vec4 Shaders
high performance
• 16 execution units
• OpenGL ES 3.1
• OpenCL Embedded
Video
8DualX
• Single Core GPU
• 4 Vec4 Shaders
poweroptimized
• 16 execution units
• OpenGL ES 3.1
• OpenCL Embedded
DSP
HiFi 4
DDR
x32
DDR3L-1866
(ECC option)
LP-DDR4-2400
(no ECC)
x32
DDR3L-1866
(ECC option)
LP-DDR4-2400
(no ECC)
x16
DDR3L-1866
(no ECC)
LP-DDR4-2400
(no ECC)
HiFi 4
HiFi 4
4
4
Displays
Up to 3
2x 1080p1x WVGA
Up to 3
2x 1080p1x WVGA
Up to 3
2x 1080p1x WVGA
+ Legacy
+ Legacy
+ Legacy
4
Family of Scalable Automotive Multimedia Processors
Display Audio Applications
Graphical Instrument Clusters
Telematics and V2X
2-3 Display eCockpit Enablement using SafeAssure ASIL-B
application framework on Cortex M4 CPU combined with NXP
eXtended Resource Domain Control (XRDC) hardware IP
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SafeAssure Software – Enabling Low End eCockpit on i.MX 8X
Cortex-A35 Cortex-M4
RPC
NXP
Framework
G2D
LIB
Cluster
(2D)
Instrument Cluster rendered by M4
using G2D including safety elements
with 3D Window from IVI in Center
IVI rendered by A35 / Open OS using
OpenGLES 3D with SARVC active
Cluster Display IVI Display
CRC
i.MX 8DXP/QXP
IVI
(3D)
Linux DRM
Android SF
QNX Screen
GPU
Cluster
(3D/2D)
DPU 2D Blitter
• Cortex-M4 running NXP
proprietary SafeAssure
Framework and XRDC IP
allows Cortex-A35 and 3D
GPU to write to displays
• CRC checks and monitoring
performed by M4
• Camera and Safety Critical
elements rendered by M4
and 2D blitter
• Currently licensing and
supporting QNX, Linux and
Android use cases
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SafeAssure Display
• Provide a robust display for instrument clusters
− High level of isolation: does not depend on the Cortex-A OS, protected by firewall.
− Can operate independently if Cortex-A or GPU is crashed or stuck, for example.
• Display control is protected inside the safety partition:
− Cortex-A OS can’t misconfigure display resolution, format, timing.
• Simpler software rendering fallback, in case of GPU or Cortex-A failure
• Guarantees that safety-critical information are still displayed. In an error case, the
M4 can render text and draw PRNDL and tell-tales via simple lines and shapes,
and/or static graphics/bmp/png in a carved out area of the cluster.
• Cortex-A OS no longer need to be certified RTOS
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Software,
Professional Support
& Services
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Complimentary Support
NXP Development and Reference Boards
NXP Communities
Technical Information Center
Systems Engineering (Apps) Organization
Distributor and Field Application Engineering
Software Products /
Technology
AVB, Miracast, HDCP2.x, TRLE, TEE,
Home Kit, CarPlay, Android Auto,
AUTOSAR MCAL, GPU Driver
optimizations, AGL, Genivi, XBMC, HAB
Complimentary Software & Tools
Kinetis Design Studio, Software Development Kit, Pin
Config, Power Estimator/Analyzer, Bootloader, RTOS,
Linux & Android BSPs, Manufacturing tools…
Professional Support
Risk Reduction
Fast Answers
Hot Fixes
Professional Services
Managing Skills Gaps & Engineering Capacity
Global Staffing Capability
Vested Interest in Mutual Success
Graphic, Security, Linux/Android, Cloud.
Hardware Services
1st Time Boot
Schematics & Layout Review
Design Simulation
Software, Professional Support & Services
Embedded Processing
Solutions
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NXP Scalable Edge Processing Continuum
Functional Integration
Pe
rfo
rma
nce
Software compatibility
Ease-of-use
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• ARM Cortex-A class
and Cortex-M cores
• 600 MHz to 2 GHz performance
• Rich HMI experience
• Full open-source OS platforms
APPLICATIONS PROCESSORS
i.MX
MCUs
KINETIS & LPC
• ARM Cortex-M cores
• Performance
up to 300 MHz
• Embedded memory
• Easy to use tools
• RTOS support
Best OfBoth Worlds
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CROSSOVER PROCESSORS
i.MX RT
• ARM Cortex-M cores
• GHz performance
• High integration
• Deterministic instructions
• Short latency
• Easy to use tools
• RTOS support
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i.MX RT Series Portfolio
800+MHzPremium
600MHz Balanced
500MHzEntry
Cortex-M7, 32K/32K L1
512KB SRAM
8/16-bit EMI (SDRAM/SRAM)
LCD / CSI / 2D acceleration
Standard Security
Cortex-M7, 32K/32K L1
Cortex-M4, 16K/16K L1
2MBSRAM
8/16/32-bit EMI (SDRAM/SRAM)
Mipi CSI/DSI / 2D acceleration
Automotive, Security
Cortex-M7, 16K/16K L1
256KB SRAM
16-bit EMI (SDRAM/SRAM)
Standard Security
ENET, CAN, USB
Cortex-M7, 32K/32K L1
1MB SRAM
8/16-bit EMI (SDRAM/SRAM)
LCD / CSI / 2D acceleration
Standard Security
Cortex-M7, 16K/16K L1
128KB SRAM
Flex SPI
Standard Security
USB
RT1060 + 4MB QSPI Flash
Cortex-M7, 16K/8K L1
128KB SRAM
Flex SPI
Standard Security
USB
i.MX RT1170
i.MX RT1050
i.MX RT1020 i.MX RT1015
i.MX RT1060 i.MX RT1064
i.MX RT1010
2017 2018 2019
196BGA 196BGA 196BGA
144LQFP
100LQFP
100LQFP 80LQFP
289 BGA
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i.MX RT1170 Crossover MCUs
Market SegmentsFeatures
MCU
i.MX RT1170
Performance1GHz Cortex-M7 with 512KB TCM
400MHz Cortex-M4 with 256KB TCM
6468 total CoreMarks
Advanced SecurityEdgeLock™ 400ASecure Boot
High-Performance Crypto
On-The-Fly Memory Encryption & Decryption
Tamper Detection
Rich Feature Set2MB SRAM
2D GPU and 2D accelerator
2x 1Gbps Ethernet
MIPI CSI / DSI
Industrial, consumer and auto-grade
Low Power28nm FD-SOI Process
Optimized for both active power & leakage power
Industrial IoTFactory automation
Programable Logic controller
Unmanned vehicles
Smart retail
Access control
Consumer/HealthcareSmart home
Professional audio equipment
Patient monitoring equipment
AutomotiveIn-vehicle HMI
Two-wheel motorcycle/scooter cluster
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i.MX RT1170 Crossover MCU Family • Specifications
− Process: SEC 28FD-SOI− Core Voltage: 1.0V− Package: MAPBGA289, 14x14mm, 0.8mm pitch− Temperature: -40C to 125C (Tj)
• Key Features and Advantages− Arm Cortex-M7 processor, 1 GHz, 32KB/32KB L1
Cache, 512KB TCM− Arm Cortex-M4 processor, 400MHz, 16KB/16KB L1
Cache, 256KB TCM− 2MB on-chip SRAM (including TCM for CPU core)− Parallel LCD Display up to WXGA (1280x800) − 8/16-bit Parallel Camera Sensor Interface− 2-lane MIPI CSI and 2-lane MIPI DSI− 2D Graphics Acceleration & OpenVG Acceleration− 8/16/32-bit SDRAM controller up to 200MHz− 8/16-bit Parallel NOR FLASH / NAND FLASH / PSRAM− 2x QSPI NOR FLASH / HyperRAM / HyperFLASH
Interface− 2x eMMC 5.0/SD 3.0/SDIO Port− 2x USB 2.0 OTG, HS/FS, Device or Host with PHY− Audio: 4x I2S/SAI, 1x S/PDIF Tx/Rx, ASRC, digital
microphone input− 3x ENET: 1Gbps ENET w/ AVB + 10/100 ENET w/
IEEE 1588 + 1Gbps ENET w/ TSN − 3x 12-bit ADC, 2Msample/s, up to 24 input channels
total− 8x Analog comparator, 2x DAC− Full PMU Integration, DCDC+LDOs− Secure Boot, TRNG, RSA4096, Tamper Detection,
Secure Key Storage• Enablement
− MCUXpresso, FreeRTOS with SDK − Autosar
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EdgeLock™ 400AHW Root of Trust and Cryptography
• Secure Boot
− Chip firmware in ROM (HAB) w/ Hardware Root of Trust for Secure Boot and Hardware Unique Key
• Chip lifecycle management
− Immutable protected eFuses
• Cryptography Accelerators & RNG
− Symmetric Cryptography with 256bit Key Strength
− Asymmetric Cryptography in hardware supporting large curve sizes
− TRNG and PRNG in hardware
− Hash engine with SHA-256 and SHA-512
• Secure Time
− RTC providing trusted system time
Chip Lifecycle Management
Chip Lifecycle
Management
Secure Time
Secure Boot
EdgeLock™ 400A
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MCUXpresso SDKRuntime software including peripheral
drivers, middleware, RTOS, demos
and more
MCUXprersso IDEEdit, compile, debug and optimize in
an intuitive and powerful IDE
MCUXpresso Config ToolsOnline and desktop tool suite for system
configuration and optimization
Industry leading support and intuitive
software configuration tools to
accelerate application development.
NXP and partner solutions for
hardware debugging solutions.
Comprehensive Ecosystem
MCUXpresso Software & Tools Partner Software and Toolchains Probe and Programming Tools
LPC-Link2
https://www.nxp.com/support/developer-resources/software-development-tools/mcuxpresso-software-and-tools/mcuxpresso-software-development-kit-sdk:MCUXpresso-SDKhttps://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools/mcuxpresso-integrated-development-environment-ide:MCUXpresso-IDEhttps://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools/mcuxpresso-config-tools-pins-clocks-peripherals:MCUXpresso-Config-Tools