Improvement of Electrical Properties in a Novel Partially Depleted SOI MOSFET With Emphasizing on...

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON ELECTRON DEVICES 1

Improvement of Electrical Properties in a NovelPartially Depleted SOI MOSFET WithEmphasizing on the Hysteresis Effect

Mohammad K. Anvarifard, Student Member, IEEE, and Ali Asghar Orouji, Member, IEEE

Abstract— A novel structure is presented to suppress thehysteresis effect due to the floating body effect (FBE) in a par-tially depleted silicon-on-insulator (SOI) MOSFET. The proposedstructure, including a Si1−xGex tunnel diode on the source side,provides a proper path for transferring the accumulated holesin order to diminish the FBE. Indeed, the SiGe tunnel diode canbe introduced as a body contact for the proposed structure. Thenew structure, named the SiGe tunnel diode body contact SOI(SG-TDBC SOI), is compared with a conventional SOI MOSFET(C-SOI) structure. Also, the proposed structure improves othermain characteristics such as short channel effects, breakdownvoltage, subthreshold swing, gate-induced floating body effectand gate-induced drain leakage. Extracted numerical resultsshow that the SG-TDBC SOI structure can be considered asa candidate to replace the conventional SOI structure.

Index Terms— Floating body effect (FBE), hysteresis effect,SiGe tunnel diode, silicon-on-insulator (SOI).

I. INTRODUCTION

IN RECENT device research, silicon-on-insulator (SOI)MOSFET has been considered as a candidate to replace

conventional MOSFET technology. The basic features of theSOI MOSFET such as good frequency performance throughreduced capacitance [1], reduced short channel effects (SCEs),latch-up immunity and higher driving capability [2] haveselected it as a commercial candidate to replace the bulkMOSFET. It has been seen that the harmful effects such as theSCEs occur due to reduction of the channel length. Variousstudies have been performed to suppress the SCEs [3]–[6].

Unlike the fully depleted SOI (FD-SOI), the partiallydepleted SOI (PD-SOI) suffer from the accumulated holes inthe neutral region inside the channel. This main concern forthe PD-SOI is related to being released the holes by the impactionization mechanism and trapping them in the neutral regionof channel named as the floating body effect (FBE) [7].

Nowadays, study of the FBE mechanism and presentation ofthe novel structures to reduce the FBE are the interesting topicsof research papers. Several structures have been proposed tosuppress the FBE. Structures such as body contact SOI [8],

Manuscript received August 10, 2012; revised February 17, 2013; acceptedAugust 11, 2013. The review of this paper was arranged by EditorS. Deleonibus.

The authors are with the Electrical and Computer EngineeringDepartment, Semnan University, Semnan 35196–45399, Iran (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2013.2278627

T-gate SOI [9], and I-gate SOI [10] are desirable structuresfor reduction of the FEB. It is worth noting that theseproposed structures suffer from the large area and complexityof fabrication processes. The hysteresis effect due to theFBE can make device design problematic in the PD-SOIMOSFETs and it has a negative effect on the device perfor-mance [11]–[13].

In this paper, a novel SOI MOSFET with a SiGe tunneldiode on the source side is introduced to suppress the hys-teresis effect. This new structure called the SG-TDBC SOIincludes P+–N+ regions inside the source region that play akey role in suppression of the FBE. The proposed structurehas suppressed the FEB with focusing on the hysteresis effectsuccessfully. Also, other improvements such as higher break-down voltage (BV), reduced SCEs, lower threshold voltagevariations, lower subthreshold swing, and reduced leakagecurrent are achieved in the SG-TDBC SOIs that cannot beeasily seen in other structures. A comprehensive study for theSG-TDBC SOI and a conventional SOI (C-SOI) shows thatthe proposed structure can be considered as a candidate toreplace the C-SOI structure.

II. DEVICE STRUCTURE AND SIMULATION

A schematic cross-sectional view of the SG-TDBC SOIstructure implemented in this paper has been shown in Fig. 1.As Fig. 1 shows, a Si1−xGex tunnel diode with Ge molefraction x = 20% is inserted inside the source. Both P+ andN+ sides of the tunnel diode are degenerate. It is important tonote that the depth of both the P+ and N+ sides are identical.Typical parameters of the SG-TDBC SOI structure are listedin Table I. All the structural parameters of SG-TDBC SOIand C-SOI structures are identical unless otherwise stated.It is important to mention that the SG-TDBC SOI is analyzedin 0.13 μm SOI CMOS technology. All simulation resultshave been extracted by ATLAS 2-D and two-carrier devicesimulator [14].

To reach a realistic result, the simulator is calibrated withexperimental data [15]. Therefore, the output characteristicsof a simulated and fabricated C-SOI device is illustrated atgate voltage VG = 0.8 V in 0.13 μm technology as shown inFig. 2. It is clearly seen from the figure that there is a closeproximity between the experimental and simulated data usingthe ATLAS simulator.

0018-9383 © 2013 IEEE


2 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 1. Schematic cross-sectional view of the SG-TDBC SOI structure.

TABLE I

TYPICAL PARAMETERS OF THE SG-TDBC SOI STRUCTURE

III. PHYSICAL MECHANISMS IN THE SG-TDBCSOI STRUCTURE

This paper presents a novel device including the SiGetunnel diode on the source side to focus on the hysteresiseffect. Therefore, the role of SiGe tunnel diode has beenhighlighted to describe the main physical mechanisms, whichare responsible for reduction of the hysteresis effect.

Tunnel current density in the SiGe material is introducedas a main factor in suppression of the FBE. An analyticalexpression evaluating the tunnel current density (Jt) in P+/N+junction is given by Sze [16] according to (1)

Jt =√

2q3m∗1/2ξ Va

4π2η2 E1/2g

exp

(−4

√2m∗ (

Eg − ηω)3/2

3qηξ

)(1)

where q is electron charge, m∗ is the carrier effective mass,ξ is the maximum junction electric field, Va is the appliedreverse voltage, η = h/2π is Planck’s constant, Eg is bandgap for semiconductor, and ηω is the phonon energy. Mainparameters such as effective mass, band gap, and maximuminternal electric field are design variables to maximize thecurrent density in (1). The main idea of the proposed structure

0.0 0.2 0.4 0.6 0.8 1.00.00

0.05

0.10

0.15

ATLAS Simulator Experimental Data [15]

Dra

in C

urre

nt (m

A/µ

m)

Drain Voltage (V)

LG = 130 nmVG = 0.8 V

Fig. 2. Calibration of ATLAS simulator with experimental data [15].

is to push the body accumulated holes into the source regionto diminish the FBE. The SiGe material has lower band gapand lower effective mass compared with the Si material. Onesignificant result is that the tunnel current density increases in


ANVARIFARD AND OROUJI: IMPROVEMENT OF ELECTRICAL PROPERTIES IN A NOVEL PARTIALLY DEPLETED SOI MOSFET 3

(a)

(b)

Fig. 3. Band diagram of the SG-TDBC SOI structure along the (a) cut lineA–A′ and (b) cut line B–B′.

the proposed device according to (1). Increase in the tunnelcurrent density is most important factor in the SG-TDCB SOIstructure for suppressing the hysteresis effect. Because theaccumulated holes of the body region can be easily releasedusing the SiGe diode tunnel current. Therefore, one of the keyroles of SiGe tunnel diode is related to releasing the accumu-lated holes. Consequently, the SG-TDBC SOI structure willsuppress the FBE with help of the aforementioned importantmechanisms.

In another view, two mechanisms help together to suppressthe hysteresis effect in the proposed structure successfully.First, the SiGe material in the proposed structure creates adiscontinuity in valance band, which causes holes to easilyflow to the source side due to the reduced barrier height.For better understanding, the valance band diagram of theSG-TDBC SOI structure has been shown along the cut lineA–A′ located at 90 nm from surface of the SG-TDBC SOIstructure in Fig. 3(a). The barrier height is so small that theholes can easily flow to source side. The second importantmechanism is related to P+- and N+- embedded regions inthe SiGe tunnel diode. Since these regions have been heavilydoped, then both regions will form an Esaki tunnel diode.In Fig. 3(b), the energy band diagram of the SiGe tunnel diodeis illustrated along the cut line B–B′ located at 45 nm fromthe source side of the SG-TDBC SOI structure. As shownin Fig. 3(b), due to the small tunneling width of the SiGetunnel diode, holes can easily tunnel. As a consequent, holesare released by the tunnel current of SiGe tunnel diode in theSG-TDBC SOI structure. Indeed the most important contri-bution of the SiGe tunnel diode to the proposed structure isrelated to releasing the accumulated holes.

In Fig. 4, the hole current density of both structures in logscale has been illustrated at bias voltages VG = 1 V andVD = 1 V in order to graphically show the physical mech-anism, which is responsible for suppressing the hysteresiseffect. As shown in the figure, the maximum value of currentdensity of the SG-TDBC SOI structure is 6.56 A/cm2 whereas

(a)

(b)

Fig. 4. Hole current density for the (a) C-SOI structure and (b) SG-TDBCSOI structure.

it is 0.542 A/cm2 for the C-SOI structure. High hole currentdensity of the SG-TDBC SOI structure tell us that the FBE ofthe proposed structure is less than that of the C-SOI structure.Also, the SG-TDBC SOI structure shows a much crowdingof, the hole current density on side of the SiGe tunnel diodewhereas it has not been seen in the C-SOI structure. Thismuch crowding in the SG-TDBC SOI is made of the releasedholes by the Esaki tunnel diode. Therefore, holes caused bythe FBE, easily flow to the P+ region of the SiGe and thenare released by the Esaki tunneling at the SiGe tunnel diode.According to the mentioned mechanisms above, a proper pathwill be created to move the accumulated holes from the bodyregion to the source thus suppressing the hysteresis effect.

IV. SIMULATION RESULTS AND DISCUSSION

Holes generated by impact ionization are accumulated inthe body region and will degrade the device performance.In Fig. 5, the logarithm of hole concentration has been



Fig. 5. Hole concentrations for both C-SOI and SG-TDBC SOI structures.

illustrated along the channel and at location which is 20 nmfar away from the device surface for the SG-TDBC SOI andC-SOI structures at VG = 1 V and VD = 1 V. Accord-ing to the figure, the hole concentration near source of theSG-TDBC SOI structure is less than that of the C-SOIstructure. Hence, it is a rational evidence to describe the holescaused by the FBE are absorbed by the SiGe and then arereleased by the Esaki tunnel current of the SiGe tunnel diode.The proposed structure shows less FBE due to reduction ofthe hole concentration compared with the C-SOI structure. Thehysteresis effect which is related to the FBE can be seen inthe PD-SOI MOSFETs when a transient voltage is applied togate electrode. It is worth noting that drain currents at forwardand reverse gate voltage sweeps of a partially SOI are notthe same and there is a main difference between them namedas the hysteresis effect. Drain current has been illustrated atforward and reverse gate voltage sweeps for the C-SOI andthe SG-TDBC SOI structures as shown in Fig. 6. The drainbias VD = 1 V is applied to both the structures. It is worthnoting that the applied transient gate voltage curve has beeninserted in inset of the figure for both the structures. It canbe clearly observed from Fig. 6 that the drain current of theSG-TDBC SOI structure upon forward and reverse gate volt-age sweeps is nearly identical whereas it is not identical inthe C-SOI structure.

A comparison between these curves shows that the hystere-sis effect in the SG-TDBC SOI structure is much less thanthat in the C-SOI structure. In another effort, the reason forthe further decrease in drain current of the proposed structure(as clearly observed in Fig. 6) is explained. It can be statedthat the tunneling mechanism in the source region is themain reason why the drain current of SG-TDBC SOI structurefurther falls compared with that of the C-SOI structure. In theC-SOI structure, electrons which enter the channel from thesource side build the drain current, whereas in the SG-TDBCSOI structure due to high tunneling density, a few number ofchannel electrons which are responsible for constituting thedrain current will compensate the required tunneled electrons

Fig. 6. Drain current versus forward and reverse sweeps of gate voltage forthe SG-TDBC SOI and C-SOI structures.

Fig. 7. Drain current versus drain voltage for the C-SOI and SG-TDBC SOIstructures.

in the SiGe region. Consequently, the drain current of theSG-TDBC SOI structure is reduced when compared with thatof the C-SOI structure.

We have also examined the SiGe tunnel diode influenceon the BV of the C-SOI and SG-TDBC SOI structures. Fig. 7illustrates the drain current curve as a function of drain voltageat VG = 0 V. The BV is defined as the drain voltage wherethe drain current reaches 1 μA/μm at VG = 0 V. It can beconcluded from the figure that the BV of the SG-TDBC SOIstructure is more than that of the C-SOI structure. Indeedthe described physical mechanisms improve the BV of theSG-TDBC SOI structure.

For more accurate examination, the BV has been demon-strated as a function of the channel length in Fig. 8. Twointeresting results can be comprehended from the figure. Thefirst result is related to the absolute value of the BV. It isclear that the value of BV for the SG-TDBC SOI transistoris more than that for the C-SOI transistor at all the channel



Fig. 8. Breakdown voltage as a function of channel length for the C-SOIand SG-TDBC SOI structures.

Fig. 9. Threshold voltage versus channel length for the C-SOI and SG-TDBCSOI structures.

lengths. Regarding higher BV, the other main result which hasbeen explored in the SG-TDBC SOI structure is related to BVvariations upon the channel length. It can be seen from Fig. 8that the BV variations of SG-TDBC SOI structure is less thanthose of the C-SOI structure.

With reduction of the channel length, the undesirable effectscalled the SCES will be exhibited and will degrade the deviceelectrical performance. The threshold voltage variations anddrain-induced barrier lowering (DIBL) are taken into consid-eration for the description of the SCEs. The threshold voltageof the SG-TDBC SOI and C-SOI structures has been illustratedas a function of the channel length at VD = 0.05 V as shown inFig. 9. As shown in the figure, the threshold voltage variationsof the SG-TDBC SOI structure is less than those of theC-SOI structure. It is worth noting that the threshold voltageis extracted by calculating the maximum slope of the ID/VG

curve, finding the intercept with the axis and then subtractinghalf of the applied drain bias [14]. Also the DIBL curvehas been brought for both structures in Fig. 10. The DIBL

Fig. 10. DIBL curve as a function of channel length for the C-SOI andSG-TDBC SOI structures.

Fig. 11. Subthreshold swing as a function of channel length for the C-SOIand SG-TDBC SOI structures.

can be extracted with subtracting the threshold voltages atbiases VD = 0.05 and VD = 0.6 V, according to (2) [7] asfollows:

DIBL = VTH (VD = 0.05 V) − VTH (VD = 0.6 V). (2)

Regarding lower threshold voltage variations, reduced DIBLvalue for the presented structure in this paper will promiseVLSI circuits designers that the SG-TDBC SOI structure canbe considered as a robust device to the SCEs in comparisonwith the conventional SOI structure.

Investigation of the subthreshold swing is very importantwhen the structures go to standby mode. The subthresholdswing is defined as follows:

Subthreshold swing (S) = �VG

�Log (ID). (3)

Fig. 11 shows the subthreshold swing (S) as a function ofthe channel length. The value of swing (S) is calculated atapplied biases VD = 0.8 V and VG = 0 V. It can be seen



Fig. 12. Leakage current versus channel length for the C-SOI and SG-TDBCSOI structures.

Fig. 13. Voltage gain gm /gd versus channel length for the C-SOI andSG-TDBC SOI structures.

from the figure that the subthreshold swing of the SG-TDBCSOI structure is less than that of the C-SOI structure. Also theother improvement which is comprehended from this figureis about the subthreshold swing variations. It is clearly seenthat the subthreshold swing variations in the SG-TDBC SOIstructure is less than those in the C-SOI structure.

For better understanding, the leakage current has beenillustrated as a function of the channel length in log scalein Fig. 12. The leakage current is defined as the drain currentwhere the drain voltage reaches value of 1 V at VG = 0 V.As the figure shows, the leakage current of the SG-TDBC SOIstructure is less than that of the C-SOI structure. Therefore, theproposed structure has less power dissipation compared withthe C-SOI structure when it is working in the standby mode.

One of the other main parameters that influence on the per-formance of the SG-TDBC SOI device is voltage gain gm/gd .

Fig. 14. Drain current as a function of gate voltage for the C-SOI andSG-TDBC SOI structures.

Drain conductance (gd) is extracted from the slope of VD–ID

curve between VD = 0.4 V and VD = 1 V at VG = 0.8 Vfor the both structures. Since gm and gd should be consideredsimultaneously, gm/gd has been selected in order to comparethe analog performance of both structures as shown in Fig. 13.It is evident from the figure that the higher voltage gain ofthe proposed structure can make it more flexible than theC-SOI, structure for detecting the weak signals in small-signalapplications.

Gate-induced drain leakage (GIDL) as another undesirableeffect was improved in the proposed structure. The VG–ID

curves of the SG-TDBC SOI and C-SOI structures are illus-trated at VD = 1 V in Fig. 14 in log scale. The figureclearly shows that the GIDL of the SG-TDBC SOI structureis less that of the C-SOI Structure. Neutral body region of theC-SOI structure has a positive potential and produces furthervertical electric field compared with that of the SG-TDBC SOIstructure. Since the vertical electric field of the SG-TDBC SOIdevice is less than that of the conventional sample then only afew number of electron-hole pairs will be created in depletedgate-drain overlap region resulting in reduction of the GIDLin the proposed structure.

In ultrathin gate oxide thicknesses, the impact of gateto body current on the FB potential in FB PD SOI struc-ture due to direct tunneling mechanism results in the gate-induced floating body effect (GIFBE) [17]. This mechanismis related to direct tunneling of inversion layer (electrons)to the gate oxide. Regarding the PD-SOI devices, one ofimportant characteristics concluded from the GIFBE is thesharp transconductance peak available (as the second maxi-mum transconductance) [18]. In Fig. 15, the transconductanceof the C-SOI and SG-TDBC SOI devices are plotted versusthe gate voltage at VD = 0.1 V.

It is worth noting that gate width (W ) is chosen to be 1 μm(W = 1 μm). It can be seen from the figure that there is asharp transconductance peak (as shown in the figure with acircle) in the gm curve of the C-SOI structure whereas it hasbeen completely removed in the proposed structure. Indeed,



TABLE II

PERFORMANCE COMPARISON BETWEEN THE SG-TDBC SOI AND THE TG-BC SOI STRUCTURES

Fig. 15. gm as a function of gate voltage at VD = 0.1 V for the C-SOI andSG-TDBC structures.

the SiGe tunnel diode on the source side mitigates the GIFBEin the SG-TDBC SOI device.

T-Gate Body Contact SOI (TG-BC SOI MOSFET) has beenintroduced as a good device to suppress the FBE and it is acandidate to replace the conventional SOI device [15].

Nevertheless, the proposed structure has better performancesuperiority than the TG-BC SOI structure.

For more clarification, a comparison has been performedamong the C-SOI, TG-BC SOI [15], and SG-TDBC SOI (thispaper) structures with the gate width 10 μm (W = 10 μm).The obtained results from simulations have been listed inTable II. The maximum drain current hysteresis (maximum ID

hysteresis), the BV, the breakdown voltage variations (�BV),and the subthreshold swing (S) are evaluated variables in thestructures in order to compare the performance of structures.It is important to point out that the drain current hysteresis(ID hysteresis) is calculated with subtracting the drain currentsat forward and reverse sweeps of drain voltage [12]. Accordingto Table II, the investigated variables of proposed structuresuch as the BV, the �BV, and the subthreshold swing (S)have been improved compared with those of the TG-BCSOI and the C-SOI structures. Regarding the aforementionedimprovement in our structure, one of main drawbacks of theTG-BC SOI is related to fabrication processes. There are twoshortcomings in the TG-BC SOI device: larger device areaand lower effective device width [19]. These problems do notexist in the SG-TDBC SOI device. Therefore, all the obtainednumerical results show that the SG-TDBC SOI device can beconsidered as a candidate to replace the C-SOI and TG-BCSOI devices.

V. CONCLUSION

A novel SOI MOSFET with the SiGe tunnel diode(SG-TDBC SOI) has been successfully presented to suppressthe FBE. Holes generated by impact ionization easily flow toP+ region inside the source due to the small barrier height andthen are released by Esaki tunnel current of the SiGe tunneldiode inserted in the source region. The hysteresis effect hasbeen completely eliminated in the SG-TDBC SOI structure,and marvelous improvements on the breakdown voltage andits variations were obtained.

The SiGe Tunnel diode on the source side has successfullycontrolled other main characteristics such as the SCEs, thesubthreshold swing, the leakage current, the GIDL, and theGIFBE. All the obtained results show that the SG-TDBCSOI structure can be considered a candidate to replace theconventional SOI (C-SOI) and TG-BC SOI devices. Therefore,it is expected that the proposed structure provide an incentivefor experimental verification.

REFERENCES

[1] S. N. A. Marshall, SOI Design: Analog, Memory and Digital Techniques.Norwell, MA, USA: Kluwer, 2003.

[2] T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, “Experimental0.25-μm-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique,” IEEE Trans. Electron Devices, vol. 42,no. 8, pp. 1481–1486, Aug. 1995.

[3] A. O. Adam, K. Higashi, and Y. Fukushima, “Analytical thresholdvoltage model for ultrathin SOI MOSFETs including short-channel andfloating body effects,” IEEE Trans. Electron Devices, vol. 46, no. 4,pp. 729–737, Apr. 1999.

[4] L. Vancaille, V. Kilchytska, D. Levacq, S. Adriaensen, H. Van Meer,K. De Meyer, G. Torrese, J.-P. Raskin, and D. Flandre, “Influence ofHALO implantation on analog performance and comparison betweenbulk, partially depleted and fully depleted MOSFETs,” in Proc. IEEEInt. SOI Conf., Oct. 2002, pp. 161–163.

[5] M. J. Kumar and A. Chaudhry, “Two-dimensional analytical modeling offully depleted DMG SOI MOSFET and evidence for diminished SCEs,”IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 569–574, Apr. 2004.

[6] J.-P. Colinge, “Multiple-gate SOI MOSFETs,” Solid-State Electron.,vol. 48, no. 6, pp. 897–905, Jun. 2004.

[7] J. P. Colinge, Silicon-on-Insulator: Materials to VLSI, 3rd ed. Norweel,MA, USA: Kluwer, 2004.

[8] K. Yo-Hwan, C. Jin-Hyeok, N. Myung-Hee, and Y. Ji-Woon, “Bodycontacted SOI MOSFET structure with fully bulk CMOS compati-ble layout and process,” IEEE Electron Device Lett., vol. 18, no. 3,pp. 102–104, Mar. 1997.

[9] B. W. Min, L. Kang, D. Wu, D. Caffo, J. Hayden, and M. A. Mendicino,“Reduction of hysteretic propagation delay with less performance degra-dation by novel body contact in PD SOI application,” in Proc. IEEE Int.SOI Conf., Oct. 2002, pp. 169–170.

[10] W. Chieh-Lin, Y. Chikuang, H. Shichijo, and K. O. Kenneth, “I-gatebody-tied silicon-on-insulator MOSFETs with improved high-frequencyperformance,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 443–445,Apr. 2011.

[11] J. Damiano and P. D. Franzon, “Integrated dynamic body contact forH-gate PD-SOI MOSFETs for high performance/low power,” in Proc.IEEE Int. SOI Conf., Oct. 2004, pp. 115–116.



[12] J. Luo, J. Chen, J. Zhou, Q. Wu, Z. Chai, and X. Wang, “Temperaturedependence of hysteresis effect in partially depleted silicon-on-insulatorMOSFETs,” IEEE Trans. Device Mater. Rel., vol. 12, no. 1, pp. 63–67,Mar. 2012.

[13] A. A. Orouji and M. Mehrad, “The best control of parasitic BJT effect inSOI-LDMOS with SiGe window under channel,” IEEE Trans. ElectronDevices, vol. 59, no. 2, pp. 419–425, Feb. 2012.

[14] Device Simulator ATLAS, Silvaco Int., Sanata Clara, CA, USA, 2012.[15] J. Chen, J. Luo, Q. Wu, Z. Chai, T. Yu, Y. Dong, and X. Wang, “A tunnel

diode body contact structure to suppress the floating-body effect inpartially depleted SOI MOSFETs,” IEEE Electron Device Lett., vol. 32,no. 10, pp. 1346–1348, Oct. 2011.

[16] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York, NY,USA: Wiley, 1981.

[17] C. H. Dai, T. C. Chang, A. K. Chu, Y. J. Kuo, S. C. Chen, C. C. Tsi,S. H. Ho, W. H. Lo, G. Xia, O. Cheng, and C. T. Huang, “On the originof hole valence band injection on GIFBE in PD SOI n-MOSFETs,”IEEE Trans. Electron Devices, vol. 31, no. 6, pp. 540–542, Jun. 2010.

[18] A. Nishiyama, O. Arisumi, and M. Yoshimi, “Suppression of float-ing body effect in PD SOI MOSFETs with SiGe source structureand its mechanism,” IEEE Trans. Electron Devices, vol. 44, no. 12,pp. 2187–2192, Dec. 1997.

[19] A. Daghighi, M. Osman, and M. Imam, “An area efficient body contactfor low and high voltage SOI MOSFET devices,” Solid-State Electron,vol. 52, no. 2, pp. 196–204, Feb. 2008.

Mohammad K. Anvarifard (S’12) is currentlypursuing the Ph.D. degree with the Department ofElectrical Engineering, Semnan University.

His research interests include investigation ofnovel structures in nanoscale SOI MOSFETs, analyt-ical approaches for evaluation of the SOI MOSFETs,and VLSI circuits.

Ali Asghar Orouji (M’05) received the Ph.D.degree from the Indian Institute of Technology,Delhi, India, in 2006.

He has been with Semnan University, Semnan,Iran, as a Faculty Member, since 1992.

Improvement of Electrical Properties in a Novel Partially Depleted SOI MOSFET With Emphasizing on...

Documents

Transcript of Improvement of Electrical Properties in a Novel Partially Depleted SOI MOSFET With Emphasizing on...