Important Bits and Answersfor CSC

8/3/2019 Important Bits and Answersfor CSC

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Important Bits

for CSC Company

- baapek


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The OR gate can be converted to the

NAND function by adding----gate(s)tothe input of the OR gate.

a) NOT

b) AND

c) NOR

d) XOR


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For 1MB memory, the number ofaddress lines required

a)12 b)16 c)20 d)32There is a circuit using 3 nand gates

with 2 inputes and 1 output,f ind the

output.a) AND b) OR c) XOR d) NAND


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.what is done for push operation

a) SP is incremented and then the

value is stored. b) PC is incremented and then the

value is stored.

c) PC is decremented and then thevalue is stored.

d) SP is decremented and then the

value is stored.
http://www.freshersworld.com/placementweek/showpaper.asp?cid=224&pid=12555&pgcount=1&prio=3http://www.freshersworld.com/placementweek/showpaper.asp?cid=224&pid=12555&pgcount=1&prio=3


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Memory allocation of variablesdeclared in a program is ------

a) Allocated in RAM b) Allocated in ROM

c) Allocated in stack

d) Assigned in registers.


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purpose of PC (program counter)in amicroprocessor is ----

a)To store address of TOS(top ofstack)

b) To store address of next

instructions to be executed c) count the number of instructions

d) to store the base address of the

stack.


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In 8085 which is called as Highorder / Low order Register? -

Flag is called as Low order register &Accumulator is called as High orderRegister.


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What happens when HLTinstruction is executed inprocessor? -

The Micro Processor enters into Halt-State and the buses are tri-stated.

Stack pointer is a special purpose 16-bit register in the Microprocessor,

which holds the address of the top ofthe stack.


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Which interrupt is not level-sensitive in 8085? -

RST 7.5 is a raising edge-triggeringinterrupt.

In 8085 ,three RST pins are available, suchas RST 7.5 ,RST 6.5 , RST 5.5. RSTrepresents Restart Interrupts. These arevectored interrupts that transfer the


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conditional results after execution ofan instruction in a microprocess isstored in

a) register b) accumulator c) flagregister d) flag register part of PSW(program status word)


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In8051microcontroller,------has a dual

function. a) port 3

b) port 2 c) port 1

d) port 0


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What are Hardware interrupts?

- TRAP, RST7.5, RST6.5, RST5.5,

INTR.

Which interrupt has the highest

priority? -TRAP has the highestpriority.

What is clock frequency for


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A positive going pulse which isalways generated when 8085 MPUbegins the machine cycle.

a) RD b) ALE c) WR d) HOLD

when a ----- instruction of 8085 MPUis fetched , its second and third bytesare placed in the W and Z registers.

a) JMP b) STA c) CALL d) XCHG


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what is defined as one subdivision ofthe operation performed in one clockperiod.

a) T- State b) Instruction Cycle c)Machine Cycle d) All of the above


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At the end of the following code,what is the status of the flags.

LXI B, AEC4H

MOV A,C

ADD B

HLT

a) S = 1, CY = 0, P = 0 , AC = 1

b) S =0 , CY = 1, P = 0,AC = 1


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The repeated execution of a loop of codewhile waiting for an event to occur iscalled ---------.The cpu is not engaged in

any real productive activity during thisperiod,and the process doesnt progresstowards completion.

a) dead lock

b) busy waiting

c) trap door

d) none.


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microprocessor is ----

a) To store address of TOS(top of stack)

b) To store address of next instructions to beexecuted

c) count the number of instructions

d) to store the base address of the stack.


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conditional results after execution ofan instruction in a microprocess isstored in

a) register

b) accumulator

c) flag registerd) flag register part of PSW (program

status word)


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In 8085 MPU what will be the statusof the flag after the execution of thefollowing chunk of code.

MVI B,FFH

MOV A,B

CMAHLT

a)S = 1, Z = 0, CY = 1 b)S = 0,

Z = 1, CY = 0


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which of the following instruction isused to load 2050h address toHLregister pair?

a.LOD H 2050HB.LOAD H 2050HC.LXIH 2050H

D.LDAH 2050H


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.what will be the value of theaccumalator having AAH afterexecuting RLC instruction twice?

a.55hb.abhc.bah

d.aah


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List the branch related addressingmode:

Intra segment Direct

Intra segment Indirect

Inter segment Direct

Inter Segment Indirect


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List the functions of Bus InterfaceUnit in 8086.

Sends out addresses

Fetches instructions from memory

Reads data from ports and memory

Writes data to port and memory


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Write any two advantages ofsegment registers in 8086

a. It allows the memory capacity tobe 1MB even though the address

associated with individualinstructions are 16 bits wide.

b. It allows the instruction,data, orstack portion of a program to bemore


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Define Inter segment addressingmode:

It replaces the contents of IP withpart of the instruction and thecontents

of CS with another part of theinstruction.


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Define XLAT instruction used in 8086.

It translates a byte in AL using a table inmemory. The offset address is

calculated by adding the 8 bit contents of theAL register and the contents of

BX register. BX register contains the starting

offset address of the Lookup table. After execution , corresponding data memory

contents of the lookup table

are loaded into the AL register.


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What is difference between DIV andIDIV instruction in 8086 ?

DIV : It operates only on unsignednumber.

IDIV : It operates only on signednumbers.


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What is the value of AL afterexecuting the following instructions.

MOV AL,35H

ADD AL,49H

DAA

Ans : AL= 84


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Define LAHF and SAHF instructions in8086. LAHF : Load the 8085equivalent flags into the AH register.

SAHF: Store the AH register into thelow order byte of the flag register.

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