IMPLEMENTATION OF ORTHOGONAL FREQUENCY...

Vol 05, Article 08393, November 2014 International Journal of VLSI and Embedded Systems-IJVES

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IMPLEMENTATION OF ORTHOGONAL FREQUENCY

DIVISION MULTIPLEXING TRANSCEIVER ON FPGA AMRUTHA A

1, SUNIL JACOB

2, VRINDA V GOPAL

3

1M.Tech, VLSI and Embedded Systems,

2 3 Associate Professor, Electronics and Communication

1 2 3 SCMS school of engineering and technology, Karukutty, Ernakulum, India

[email protected], [email protected]

2, [email protected]

3

ABSTRACT

Orthogonal Frequency Division Multiplexing (OFDM) is a multi carrier modulation technique which divides

the available spectrum into many carriers. OFDM uses the spectrum efficiently compared to FDMA by spacing

the channels much closer together and making all carriers orthogonal to one another to prevent interference

between the closely spaced carriers. OFDM provides high bandwidth efficiency because the carriers are

orthogonal to each others and multiple carriers share the data among themselves. The main advantage of this

transmission technique is their robustness to channel fading in wireless communication environment. The main

objective of this project is to design and implement a base band OFDM transmitter and receiver using FPGA.

This project focuses on the core processing block of an OFDM system, which are the Fast Fourier Transform

(FFT) block and the Inverse Fast Fourier Transform (IFFT). The work also includes in designing a mapping

module, serial to parallel and parallel to serial converter module. The 128 points CORDIC based IFFT / FFT

decimation-in-frequency (DIF) with radix-2 algorithm is analyzed in detail to produce a solution that is suitable

for FPGA implementation. The FPGA implementation of the project is performed using Very High Speed

Integrated Circuit (VHSIC) Hardware Descriptive Language (VHDL). This performance of the coding is

analyzed from the result of timing simulation using Xilinx.

Keywords: - FFT/IFFT, CORDIC, FPGA, OFDM, VHDL

[1] INTRODUCTION

Multicarrier modulation is a technique used for the data transmission which divides the high bit rate data

streams into several parallel low bit data streams, and these low bit data streams are used to modulate many

carriers. There are many useful properties of the multicarrier transmission such as spectral efficiency, delay

spread tolerance. Orthogonal frequency division multiplexing [OFDM] is one of the multicarrier modulation

technologies which are widely used in emerging wired and wireless communication system [1]. Recent trend

says that orthogonal frequency division multiplexing gained lot of popularity among the broadband community.

OFDM is implementing in many emerging communication protocols due to several advantages over the

traditional multiplexing technique frequency division multiplexing [FDM]. OFDM transforms a frequency

selective wideband channel into a group of non selective narrowband channels, by preserving orthogonality in

the frequency domain, OFDM makes robust against the large delay spreads. The Fast Fourier Transform [FFT]

and Inverse Fast Fourier Transform [IFFT] are the two important key points in the OFDM system. FFT is a fast

way to calculate the Discrete Fourier Transform [DFT], which transforms data from time domain to frequency

domain where as IFFT transforms data from frequency domain to time domain. The hardware implementation

of FFT/IFFT approaches is a challenging issue where the digital signal processors (DSPs) and field

programmable gate array (FPGA) chips are two considering designing environments for implementing different

schemes of FFT approaches. Recently, the FPGA technology is used as due to fast progress in very large scale

integration (VLSI) technology. The FPGA devices provide complete programmable system on chip

environments by incorporating the programmability of programmable logic devices and the architecture of gate

arrays. They consist of thousands of logic gates and some configurable logic blocks which make them

appropriate solution for prototyping the application specific integrated circuits(ASIC) with dedicated

architectures for specified digital signal processing applications[2]. This paper presents the design and

implementation of OFDM transceiver on FPGA. The proposed design is simulated using Xilinx and then it is

implemented on FPGA. This system implements a CORDIC based 128 point FFT to reduce the circuit

complexity. The system obtains high throughput and high data rate at low frequency. In this paper the code is

developed using VHDL and simulated using modelsim.

[2] RELATED WORKS

According to the literature survey various design and implementations have been done for OFDM transceiver

[3]. In paper [4] discussed about the 32 point FFT architecture using radix-2 algorithm, which uses direct

mathematical design. In paper [2] discussed about four FFT approaches such as Cooley Tukey, Good Thomas,

Radix-2 FFT and showed among them radix-2 method uses least number of slices. [5] discuss about the

CORDIC based architecture in FFT. In [6] describe the basic idea about CORDIC. Most of the hardware

implementation has been done either on vertex based FPGA or on ASICs [3]. ASIC based designs suffer from

mailto:[email protected]:[email protected]:[email protected]





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more time to market factor, high cost and provide less flexibility. FPGA uses parallel processing to realize

functions in an unlimited only limited by resources. In this work an OFDM Transceiver system is designed on a

low cost FPGA Sparten3E to improve both speed and area at a time, by utilizing less number of resources in

terms of slices, LUTs and multipliers of target FPGA to provide high performance cost effective solution for

wireless communication applications [7].

[3] PROPOSED DESIGN

Orthogonal frequency division multiplexing is the enhanced technology of the frequency division multiplexing

in which the total available bandwidth is divided into N non-overlapping frequency sub-channels which are

orthogonal to each other. Each sub-channel is modulated with a separate symbol stream.

Fig 1 Proposed design

Fig 1 shows the proposed design for OFDM transmitter and receiver. In receiver serial input data is given to a

QAM ROM, which having address bits of 7 bit each address line contain the data value. The values for the

modulation are selected from the ROM according to the address line. Selected values are then given to a serial

to parallel converter (SIPO). Parallel output given to 128 point CORDIC based FFT. In order to reduce the inter

carrier interference (ICI) cyclic prefix is added, in this design 3 bit of LSB is added to MSB. Then the output is

given to the channel.

At receiver, removing of cyclic prefix is the first step then the serial data is converted to parallel data. The

parallel data then given to the 128 point FFT. According to the output of the FFT serial data select the QAM

output. Receiver output is the address line which is given as input.

[3.1] FFT/IFFT

The OFDM transmitter and receiver contain Inverse Fast Fourier Transform (IFFT) and Fast Fourier Transform

(FFT), respectively [7]. The IFFT/FFT algorithms are chosen due to their execution speed, flexibility and

precision. For real time systems the execution speed is the main concern. The IFFT block provides orthogonality

between adjacent subcarriers. The orthogonality makes the signal frame relatively secure to the fading caused by

natural multipath environment. As a result OFDM system has become very popular in modern

telecommunication systems. In this system 128 point FFT is developed by using, 8 point CORDIC based radix2

algorithm.

Basic equation of the FFT is,

= 2

1

=1

, = 0,1 . . 1 (1)

On the other hand, the inverse FFT equation is

=1

2 1

=1

, = 0,1 1 (2)

where N is the transform size or the number of sample points in the data frame. X(k) is the frequency output of

the FFT at kth point where k=0, 1, , N-1 and x(n) is the time sample at nth point with n=0, 1,, N-1 [8].

[3.1.1] Implementation of 8 point radix-2 FFT The implementation of IFFT is simple as compared to DFT and its 8-point DIF output is derived from the input

directly [5]. The figure shows the implementation can be done in three stages as shown in Fig 2. In each stage, it

has four butterflies for both real and imaginary values. Each butterfly consists of upper wing and lower wing.

The first stage accepts the input data directly from QAM modulator which consists of real and imaginary values.





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The output of first stage is feed as the input to the second stage. The output of second stage is feed as the input

to the third stage.

The implementation of an 8 Point IFFT processor is done by using components like adders, subtractions,

multipliers and buffers[5]. In IFFT the twiddle factor values are of unsigned values which have to be converted

into binary form for the multiplication purpose. In first stage the computation of upper wings is done by using

adders and the results are stored in buffers. The computation of lower wings is done by using subtractions and

multipliers.

Fig 2 8 point IFFT (DIF)

Here for every computation of lower wing there is a different twiddle factor which has to be multiplied. After

the computation of both upper and lower wings the results are stored in buffers which are feed as input to the

second stage. The computation of second stage is also similar to that of first stage but the difference is that for

the four lower wings there are only two twiddle factors in common. Here Again the computation results are

stored in buffers and are feed to the third stage. The computation of third stage is also similar to that of first

stage but the difference is that there is only one common twiddle factor to be multiplied.

[3.2] FFT using CORDIC algorithm

CORDIC (coordinate rotation digital computer) algorithm was first introduced by Jack E. Volder in the year the

1959 for the computation of Trigonometric functions, Multiplication, Division, Data type conversion, Square

Root and Logarithms. It is a highly efficient, low-complex, and robust technique to compute the elementary

functions. CORDIC algorithm provides advantages in speed, accuracy, simplicity in design and other aspects of

performance requirements; it has been widely used in several fields such as the fast Fourier transform (FFT),

DTC and other signal processing [9]. CORDIC basically operates in vectoring mode or rotation mode. In this

paper rotation mode CORDIC is developed. If a vector V with coordinates (x, y) is rotated through an angle

then the new vector V can be obtained with coordinates (x, y) where x and y can be obtained using x, y and

. The desired angle is decomposed into several combinations of micro rotations. These micro rotations are

based on standard which is referred as reference angle [6].

x = cos (x y tan ) (3)

y = cos (y + x tan ) (4)

Xi+1 = Ki[xi yi di 2-i] (5)

Yi+1 = Ki[yi + xi di 2-i] (6)

Ki = cos (arctan(2-i)) and di = 1 (7)

Ki = cos = 1/(1+tan()) = 1/(1+tan(arctan(2-i))) = 1/(1+(2-i)) (8)

K = ki

n1

i=0

(9)

Where, each micro rotation is represented by i, for n times rotation.

= cos 0 cos 1 . . cos 1

1

=0

(10)

Removing the scale constant from the iterative equations a shift and add algorithm for vector rotation can be

used. The product approaches 0.6073 as the number of iterations goes to infinity. The exact gain depends on the

number of iterations. The initial angle Z0 = desired angle, after n iterating times, the final angle becomes 0 and

hence this mode is called rotation mode. FFT is method to calculate DFT. Here twiddle factor involves complex

number which can be generated using CORDIC. Twiddle factor is computed for 360o in case of FFT, where as

the CORDIC can be generating for maximum rotation of900. [3.2.1] Architecture for CORDIC

Figure 3 shows system block diagram which shows the CORDIC and FFT block. 128 point FFT is developed

from the 8 point FFT. CORDIC block reads angle input from memory and performs operation in order to

generate sine and cosine (twiddle factor). The CORDIC block works on pipeline architecture to produce first





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output after a few clock cycles and later at every clock cycle output is produced one after another for the entire

input angle saved in memory. The output of CORDIC block is saved in memory elements for future

computation. The accuracy depends upon the number of iterations used, as iteration increases accuracy

increases.

Fig 3 implementation of FFT

The speed requirement for FFT can be meet by using pipelined structure. Figure 4 shows the diagram of

pipelined CORDIC.

Fig 4 pipelined CORDIC structure

[4] SIMULATION RESULTS

The presented OFDM system is shown in the above is designed using VHDL and synthesized using modelsim

tools, simulation results are verified by using ISE simulator .The simulated wave form of OFDM transmitter is

shown in fig5. After one clock cycle the transmitted data output will changes from 0 to transmitted data. In this

paper ,clock cycle considered as 140 ns.

Fig5 waveform of OFDM transmitter





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The simulated waveform of OFDM receiver is shown in fig6. After 270ns the received output will changes as

the transmitted output.

Fig 6 waveform of OFDM receiver

[5] CONCLUSION The design of IFFT/FFT for OFDM is implemented by using Xilinx ISE design suite. The design can be

extended to implement the total OFDM transmitter and receiver with different modulation techniques like PSK,

and QAM etc. A transceiver of an OFDM system is analyzed and implemented on FPGA using a low cost

Sparton3e target device. A concept of 128 point CORDIC based FFT/IFFT architecture is used in order to

reduce circuit complexity and space. In this work area and speed are optimized also compared with previous

work and showed that the proposed design optimized in the area factor in terms of multipliers.

ACKNOWLEDGMENT The authors would like to thank for the support of Department Electronics and Communication Engineering

SSET, Karukutty, Ernakulum, India.

REFERENCES

[1]Mounir Arioua, VHDL Implementation of an optimized 8-point FFT/IFFT processor on pipeline

architecture for OFDM systems. IEEE , 978-1-61284-732-0/11,2010 .

[2]Arman Chahardahcherik. Implementing FFT Algorithms on FPGA IJCSNS International Journal of

Computer Science and Network Security, VOL No.11, November 2011 .

[3]Manjunath Lakkannavar, Design and Implementation of OFDM using VHDL and FPGA IJEAT ISSN:

2249-8958, volume-1,Issue-6, August 2012.

[4]Design of an OFDM Transmitter and Receiver using FPGA, Loo Kah Cheng, UTM, 2004.

[5]Benjamin Heyne, A pure CORDIC based FFT for reconfigurable digital signal processing.

[6]Volder J. E., The CORDIC trigonometric computing technique, IRE Trans. Electronic Computing,

Volume EC-8, pp 330 - 334, 1959.

[7]Shaminder Kaur. FPGA Implementation of OFDM Transceiver using FFT Algorithm International Journal

of Engineering Science and Technology (IJEST) ISSN : 0975-5462 Vol. 4 No.04 April 2012.

[8]Ahmed Saeed, M.Elbably, G.Abdelfadeel, and M.I.Eladway, Efficient FPGA Implementation of FFT/IFFT

Processor, International Journal of Circuits, Systems and Signal Processing.

[9]Volder J. E., The CORDIC trigonometric computing technique, IRE Trans. Electronic Computing,

Volume EC-8, pp 330 - 334, 1959.

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