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Implementation of high speed digital channel
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IMPLEMENTATION OF HIGH SPEED DIGITAL CHANNEL
High Speed Digital System LabSpring 2009
1 semester project
Instructor: Mony Orbach Students: Pavel Shpilberg Ohad Fundoianu
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Definition Theoretical Background Project targets Block diagram Schematic diagram Programmable parameters Time table
Topics
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Examining Stratix card ability of GX (protocols and parameters).
Testing the channel by checking the distortion of signals along the lines using high speed scope.
Implementation of High Speed Serial channel on Stratix 2 GX board.
Definition
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Serial Out
Transceiver – used for transmitting/receiving data in the PHY.
PHY – The physical layer of the OSI model consists of PCS, PMA and PMD - physical medium.
Theoretical background
PMAAnalog Section
PCSDigital Section
n
nFPGA
m
m
Applications – Gigabit Ethernet systems, wireless network routers, fiber optic and communication systems.
Serial In
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Noise In Digital ChannelAmplitude dependent Noise:
CrossTalk: Capacitive & Inductive Coupling Shared Signal Return
ISI: Reflections, Oscillations, Inertial Delay.
Timing: Skew, Jitter.
Power Suppluy Noise.
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Independent Noise:
Skin Effect
Ohmic Loss
Dielectric Loss
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SerilizerEncoding
PLL
Channel:• rate: 6.1Gbps
I/O :• 8 bit bus• max rate: 710
Mbps
Block diagram
DeserilizerDecoding8
8 8
8
4
input
output
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ReceiverTransmitterPLL
Memory
2
MemoryHS
Scope
Outputclock
Schematic diagram
88
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8/10 B Transmit Buffer Pre-Emphasis Receiver Input Buffer Equalizer PLL/CRU Clock
Programmable parameters
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23/12
30/12
6/12
14/1
21/1
30/1
5/2
Learning how to use high speed scope, and labs board.
Implementing the HS channel at highest speed, with out 10/8 bit .
Examining Programmable Parameters
Generating Distortions Using Lab's Boardand Analyzing them on scope
Final Presentation and Project Book
Time table