Slide 1

Implementation of a Low Leakage Standard Cell Library based on materials from UMC 65nm technology Themistokles Haniotakis Comp. Engineering & Informatics University of Patras Greece haniotak@ceid.upatras.gr George Alexiou Comp. Engineering & Informatics University of Patras Greece alexiou@ceid.upatras.gr Theodoros Simopoulos Comp. Engineering & Informatics University of Patras Greece simopoulos@ceid.upatras.gr Slide 2 CEID STD LIB There are others Reasons to implement a Standard Cell Library 1.To have the know how 2.To alter the layout 3.Able to implement custom cells Slide 3 MACRO CEID STD LIB MACRO CHARACTERISTICS The CEID STD LIB is: Complete Combinational Cells Sequential Cells Support Cells Ready to synthesis Timing characterized Area characterized Cell Name Driving Strength X1X2X4 AOI21 AOI211 AOI22 OAI21 OAI211 OAI22 Cell Name Driving Strength X1X2X4 INV INVEN BUF BUFEN NAND2 AND2 NOR2 OR2 Cell Name Driving Strength X1X2X4 XOR2 XNOR2 FA1 HA1 MUX2 MUX4 MUX2B Cell NameCell Description QDLATEPositive Enable triggered D type Latch QDLATNENegative Enable triggered D type Latch QDLATER Positive Enable triggered D type Latch with Reset QDLATNENR Negative Enable triggered D type Latch with negative Reset QDLATENS Positive Enable triggered D type Latch with negative Set QDLATNENS Negative Enable triggered D type Latch with negative Set QDLATESR Positive Enable triggered D type Latch with Set and Reset QDLATNESR Negative Enable triggered D type Latch with Set and Reset LATCHES Cell NameCell Description QDFFCPositive clock triggered D type Flip-Flop QDFFNCNegative clock triggered D type Flip-Flop QDFFCR Positive clock triggered D type Flip-Flop with Reset QDFFNCNR Negative clock triggered D type Flip-Flop with negative Reset QDFFCS Positive clock triggered D type Flip-Flop with Set QDFFNCNS Negative clock triggered D type Flip-Flop with negative Set QDFFCSR Positive clock triggered D type Flip-Flop with Set and Reset QDFFNCNSR Negative clock triggered D type Flip-Flop with negative Set and Reset DFFs Total 81 Cells Cell Name Driving Strength Cell Description X1 X2X4 TIE0 Output is tight to logic 0 TIE1 Output is tight to logic 1 FILL Placement gap filler cells Slide 4 MICRO CEID STD LIB MICRO CHARACTERISTICS The CEID STD LIB CELLS: Are implemented on CMOS Logic Support 6 Views Most have 3 driving strengths X1 => nmos 150nm, pmos 300nm X2 => nmos 300nm, pmos 600nm X4 => nmos 600nm, pmos 1.2um 1/2 AOI22 INVINVX2 INVX4 X1 Slide 5 MICRO CEID STD LIB MICRO CHARACTERISTICS The CEID STD LIB CELLS: Have height 2.3 um (snap bounding box) 2.52um (from rail to rail) Height is smallest possible to support only two metal layers to support horizontal & vertical expantion 2/2 Slide 6 CEID STD LIB CELL EXPANTION INVERTER Vertical expantion from X1 to X2 Horizontal expantion from X2 to X4 (Due to LIB usage target) Slide 7 CEID STD LIB CELL ABUTMENT Horizontal abutment Vertical abutment Layout grid result 0.14um (1 pitch = 28nm) Slide 8 CEID STD LIB MACRO GENERATION Macro Synthesis Placing and Routing a Macro Importing the Layout of a Macro 16 Bit Set-Reset register, Area: 222um 2 (a) 16 Bit Adder-Subtracter unit, Area: 744um 2 (c) 16 Bit Shift functions unit, Area: 0.0012mm 2 (e) 32 Bit Cortex M0DS, Area: 0.046 mm 2 (f) Slide 9 CEID STD LIB LIBRATY VERIFICATION Test design : a Hierarchical 16 Bit ALU Slide 10 DOWNLOAD THE LIBRARY http://www.ceid.upatras.gr/webpages/courses/vlsilab/ceidStdLib.html Slide 11 OUR FUTURE WORK 1.Second Variation Cells expands only horizontaly More metal levels inserted v2 Lib targets projects 2.A Memory Library is on the way (First results are estimated) Slide 12 Slide 13