Implementation and Test of the First- Level Global Muon Trigger of the CMS Experiment Hannes Sakulin...

Implementation and Test of the First-Implementation and Test of the First-Level Global Muon TriggerLevel Global Muon Triggerof the CMS Experimentof the CMS ExperimentHannes Sakulin1), 2), Anton Taurok2) 1) CERN2) Institute for High Energy Physics, Vienna, Austria

11th Workshop on Electronics for LHC Experiments Heidelberg13th September, 2005

URL of this presentation: URL of this presentation: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/GMT_LECC_13Sep2005.pdfhttp://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/GMT_LECC_13Sep2005.pdf

Hannes SakulinCERN / HEPHY Vienna

Implementation and Test of the First-Level Global Muon Trigger of

CMS2

LECC 2005Heidelberg, 13th September 2005

CMS Detector and the Muon SystemCMS Detector and the Muon System

Drift-Tube chambers (DT)Drift-Tube chambers (DT) - 4 stations in muon barrel- 4 stations in muon barrel - 12 (8) DT layers per station- 12 (8) DT layers per station

Cathode Strip Cathode Strip Chambers (CSC)Chambers (CSC)- 4 stations in 4 stations in muon endcaps muon endcaps

- 6 CSC layers per 6 CSC layers per station station

Resistive Plate Chambers Resistive Plate Chambers (RPC)(RPC) - 6 layers in muon barrel- 6 layers in muon barrel

- 4 layers in muon endcaps- 4 layers in muon endcaps

Iron YokeIron YokeSuperconducting CoilSuperconducting Coil

TrackerTracker

Electromagnetic Electromagnetic CalorimeterCalorimeter

HadronicHadronicCalorimeterCalorimeter



CMS3


CMS Level-1 TriggerCMS Level-1 Trigger

Optimal CombinationOptimal CombinationCancel out duplicatesCancel out duplicatesBest four muonsBest four muonsCalo confirmation + isolationCalo confirmation + isolation

Trigger Algorithms (max. 128 in parallel)Trigger Algorithms (max. 128 in parallel)

11, 2, 2, 1, 1+1e, 1e, 2e, +1e, 1e, 2e, +j …topological+j …topologicalOnly place where thresholds are appliedOnly place where thresholds are appliedmax. 100 kHz L1 Accept

Pip

elin

ed

40

MH

z,

La

ten

cy <

3.2

s

HFHF HCALHCAL ECALECAL RPCRPC CSCCSC DTDT

DT local trigger

CSC local trigger

DT TrackFinder

CSC TrackFinder

Patterncomparator

triggerGlobalCalorimeter

Trigger

Global Muon Trigger

L1 Global Trigger

RegionalCalorimeter

Trigger

4 4 4 4 4+4 4+4

4 4 (with MIP/ISO bits)(with MIP/ISO bits)

MIP+MIP+Quiet bitsQuiet bits

e/e/, j, E, j, ETT, E, Ettmissmiss, …, …

Calorimeter TriggerCalorimeter Trigger Muon TriggerMuon Trigger



CMS4


Global Muon Trigger Overview Global Muon Trigger Overview

Output:Output:8 bit8 bit, 6 bit , 6 bit , 5 bit p, 5 bit pTT, ,

2 bits charge/synch, 3 bit 2 bits charge/synch, 3 bit quality,quality, MIP bit, Isolation bitMIP bit, Isolation bit

Output:Output:8 bit8 bit, 6 bit , 6 bit , 5 bit p, 5 bit pTT, ,

2 bits charge/synch, 3 bit 2 bits charge/synch, 3 bit quality,quality, MIP bit, Isolation bitMIP bit, Isolation bit

Inputs:Inputs:8 bit 8 bit , 6 bit , 6 bit , 5 bit p, 5 bit pTT, ,

2 bits charge, 3 bit quality,2 bits charge, 3 bit quality,1 bit halo/1 bit halo/ fine-coarse fine-coarse

Inputs:Inputs:8 bit 8 bit , 6 bit , 6 bit , 5 bit p, 5 bit pTT, ,

2 bits charge, 3 bit quality,2 bits charge, 3 bit quality,1 bit halo/1 bit halo/ fine-coarse fine-coarse

Best 4 Best 4

4 4 RPC brl RPC brl

4 4 DT DT

4 4 CSC CSC

4 4 RPC fwd RPC fwd

252 MIP bits252 Quiet bits

RPCbrl

RPCfwd

CSC

DT

SY

NC

cancel CSC

cancel DT

sortstage1barrel

sortstage1forwd

sortstage2

BarrelMuon Merger Unit

ForwardMuon Merger Unit

Match & PairDT/brlRPC

Match & PairCSC/fwdRPC

SY

NC

SY

NC

SY

NC

Convert& Rank

to GT

Convert& Rank

Convert& Rank

Convert& Rank

Forward MIP & ISOAssignment Unit

SY

NC

QuietMIP

brlBarrel MIP & ISOAssignment Unit

MIPQuiet

SY

NC

fwd

Match & PairDT/CSC

Match & PairCSC/brlRPC

Match & PairDT/fwdRPC

cancel brlRPC

cancel fwdRPC

v

v

CDL

Cancel-Out Units

CDL

CDL

Merge MethodSelector (brl)

Merge MethodSelector (fwd)



CMS5


Global Muon Trigger Tasks Global Muon Trigger Tasks

Synchronizing Matching (based on ,)

& Pairing ofDT & brlRPC, CSC & fwdRPC

Merging parameters Converting scales () Detecting ghosts, fake triggers Canceling out duplicated

candidates in the overlap region Propagating to calorimeter for

MIP bit assignment / to vertex for ISO bit assignment

Ranking & Sorting

RPCbrl

RPCfwd

CSC

DT

SY

NC

cancel CSC

cancel DT

sortstage1barrel

sortstage1forwd

sortstage2





SY

NC

SY

NC

SY

NC

Convert& Rank

to GT

Convert& Rank

Convert& Rank

Convert& Rank


SY

NC

QuietMIP


MIPQuiet

SY

NC

fwd

Match & PairDT/CSC



cancel brlRPC

cancel fwdRPC

v

v

CDL

Cancel-Out Units

CDL

CDL





CMS6


RPCbrl

RPCfwd

CSC

DT

SY

NC

cancel CSC

cancel DT

sortstage1barrel

sortstage1forwd

sortstage2





SY

NC

SY

NC

SY

NC

Convert& Rank

to GT

Convert& Rank

Convert& Rank

Convert& Rank


SY

NC

QuietMIP


MIPQuiet

SY

NC

fwd

Match & PairDT/CSC



cancel brlRPC

cancel fwdRPC

v

v

CDL

Cancel-Out Units

CDL

CDL



Global Muon Trigger Simulation Global Muon Trigger Simulation

Cancel ghostsCancel ghostsbarrel / endcap overlap regionbarrel / endcap overlap region

Optimal combinationOptimal combination

Project to CalorimeterProject to Calorimeterassign MIP, ISOassign MIP, ISO

DetermineDeterminebest four muonsbest four muonssort by ranksort by rank

5%5%

<0.1%<0.1%

m

uo

n, c

alo

pT

GMTselection

Rate

kHz

at 14 GeV/c

OR 98.1 5.4

SMART 97.3 2.9

AND 87.4 2.0

rates for L=2x1033 cm-2s-1



CMS7


VME Boards & Data flowVME Boards & Data flow

PSB-9UPSB-9UPipeline Synchronizing BufferPipeline Synchronizing Buffer

GMT-9UGMT-9U16 STP cables, SCSI connectors16 STP cables, SCSI connectors

512 bit @ 40 MHz512 bit @ 40 MHz

Muon candidates (16)Muon candidates (16)

MIP and Quiet bitsMIP and Quiet bits

RPC-TriggerRPC-Trigger

CSC TriggerCSC Trigger

DT TriggerDT Trigger

RPC TriggerRPC Trigger

backplane GTL+backplane GTL+52 bit @ 80 MHz52 bit @ 80 MHz

Best 4 muonsBest 4 muonsGlobal Global TriggerTrigger

Backplane connectionBackplane connectionGTL+, 360 bit @ 80 MHzGTL+, 360 bit @ 80 MHz

point-to-pointpoint-to-point

GlobalGlobalCalorimeterCalorimeterTriggerTrigger

12 cables x 2 pairs12 cables x 2 pairs252 bit @ 80 MHz252 bit @ 80 MHz

sent on 1.4 Gbit/s serial linkssent on 1.4 Gbit/s serial links

backplane serial linkbackplane serial linkmax. 28 bit @ 40 MHzmax. 28 bit @ 40 MHz

sent at 280 MHzsent at 280 MHz

Event records Event records (3072 bits / trigger)(3072 bits / trigger)

to DAQto DAQvia front-via front-end cardend card



CMS8


GMT 9U VME BoardGMT 9U VME Board



CMS9


GMT 9U VME BoardGMT 9U VME BoardVME 64xVME 64xInterfaceInterface

Altera ACEXAltera ACEX

SORTSORTVirtexII-2000VirtexII-2000

ROP&ROP&ControlControlVirtexII-2000VirtexII-2000

LogicLogicfwdfwdVirtexII-3000VirtexII-3000

LogicLogicbrlbrlVirtexII-3000VirtexII-3000

MIP/ISOMIP/ISObrlbrlVirtexII-3000VirtexII-3000

MIP/ISOMIP/ISOfwdfwdVirtexII-3000VirtexII-3000

InputInputfwdRPCfwdRPCVirtexII-1500VirtexII-1500

InputInputCSCCSCVirtexII-1500VirtexII-1500

InputInputDTDTVirtexII-1500VirtexII-1500

InputInputbrlRPCbrlRPCVirtexII-1500VirtexII-1500

Input BoardInput Board12 SCSI12 SCSIconnectorsconnectors

LVDS LVDS receiversreceivers

10x Xilinx10x XilinxVirtex-II FPGAVirtex-II FPGA

on mezzanineson mezzanines

XC18V04 PROMsXC18V04 PROMsmounted undermounted underthe mezzaninesthe mezzanines

up to 4 per FPGA up to 4 per FPGA

JTAG XilinxJTAG Xilinx

JTAG AlteraJTAG Altera

Channel LinkChannel Linkfor readoutfor readout

Power SupplyPower Supply+Cooling+Cooling

Clock Clock distributiondistribution

Readout Processor Readout Processor VME InterfaceVME InterfaceJTAG via VMEJTAG via VME

Simu & Spy ControlSimu & Spy ControlBoard ControlBoard Control



CMS10


Mezzanine board for BF957Mezzanine board for BF957

For Xilinx Virtex-II-2000,-3000, -4000

Connectors 2x Samtec MIT-076-L-D

(up, down) 2x Samtec MIT-095-L-D

(left, right) 50 impedance

Used for all FPGAs on the GMT Logic Boardexcept Input FPGAs



CMS11


Front PanelFront Panel



CMS12


Input Board + Front PanelInput Board + Front Panel

Edge connectorsEdge connectorsB25 Z-pack 2 mmB25 Z-pack 2 mm

(Tyco AMP)(Tyco AMP)



CMS13


GMT in the Global Trigger CrateGMT in the Global Trigger Crate

In three slots In three slots behind the behind the

GMT front panelGMT front panel

GMT Logic BoardGMT Logic Board 3 Pipeline3 PipelineSync. BoardsSync. Boards

Global Trigger CrateGlobal Trigger Crate

Special wide input board Special wide input board parallel to front panelparallel to front panel

Global Trigger Boards and Global Trigger Boards and Trigger Control SystemTrigger Control Systemhoused in same cratehoused in same crate

Space for cablesSpace for cables



CMS14


FPGA DevelopmentFPGA Development

GMT LUT XGMT LUT X

Lookup MethodLookup Method

Cadence NCSIMCadence NCSIM

Cadence NCSIMCadence NCSIM

Xilinx ISE Xilinx ISE 6.36.3

Synplify Synplify 7.37.3

VHDL VHDLVHDL

Behavioral simulationBehavioral simulation

Gate level simulationGate level simulation

Chip configurationChip configuration

VHDL generated byVHDL generated byLUT FrameworkLUT Framework

SynthesisSynthesis

ImplementationImplementation

Concurrent Versions SystemConcurrent Versions Systemto manage VHDL codeto manage VHDL code

CVS ServerCVS Server

““Build System”Build System”most of design flow most of design flow scripted with Makefilesscripted with Makefiles

Automated testsAutomated testsverify functionality after every changeverify functionality after every changecross-check with C++ simulationcross-check with C++ simulation

look-up tableslook-up tablesC++C++

GMT LUT XGMT LUT XLookup MethodLookup Method



CMS15


FPGA DevelopmentFPGA Development

Example: Forward Logic FPGA Xilinx XC2V3000 464 chip inputs/outputs

used 92/96 18 kbit memory blocks used 75 % of chip resources

used

Developed VHDL Cross-checked with

C++ simulation Synthesized + Implemented Verified on-board

Design of all 10 FPGAs now finished

GMT Forward Logic FPGA



CMS16


GMT functional tests (I)GMT functional tests (I)

Test features in hardwareSimulation RAMs in Input FPGAs

(and in MIP/ISO Assignment FPGAs)Spy RAMs in Sort FPGASynchronous start through ROP & Control chipCan test sequences at 40 MHz

Bitwise compatible C++ simulationPart of CMS simulation software (ORCA)Can save simulated GMT input and GMT output in hardware

representation Common configuration of simulation model and hardware

Configuration of simulation model can be transformed into hardware configuration (look-up-table and register contents)

Hardware test with simulated physics samples



CMS17


GMT Online Software OverviewGMT Online Software Overview

GMTDriver

Hardware Access Library

JTAG Access Library

GMTBoard

GMTChip

Board/Chip structure

GMTChipGMTChip

GMTConfigurator

GMTTester

GMTTestGMTTestGMTTest GMTMonitorMain GMT

Functionslevel

GMTFirmwareLoader

GMTLUTHandler GMTBoardController

GMTSimuSpyHandlerGMTConfigRegHandler

GMTInputMonitor

GMTErrorMonitor

Basicservices

level

Facade

GMTEvent

GMTEventReader

L1MuGMTLUT

Used by command line interface or by Trigger Supervisor



CMS18


GMT functional tests (II)GMT functional tests (II)

SORTSORT

ROP&ROP&ControlControl

LogicLogicfwdfwd

LogicLogicbrlbrl

MIP/ISOMIP/ISObrlbrl

MIP/ISOMIP/ISOfwdfwd

InputInputfwdRPCfwdRPC

InputInputCSCCSC

InputInputDTDT

InputInputbrlRPCbrlRPC

Simulated dataSimulated datasequencesequenceloaded intoloaded intosimulationsimulationRAMsRAMs

4k events4k events(by VME)(by VME)

Result “spied”Result “spied”in Spy RAMin Spy RAM

(by VME)(by VME)

Muon DataMuon Dataconnectionsconnections

testedtested

Cancel-outCancel-outlinks testedlinks tested

VME accessVME accessto all chipsto all chips

testedtested

Simulated Simulated MIP/ISO bitsMIP/ISO bits(assignment result)(assignment result)

SynchronousSynchronoustest start test start

controlled bycontrolled by

ROP&ControlROP&Control



CMS19


GMT functional test resultsGMT functional test results

VME access to all chips tested Hardware timing verified

Test works at 40 MHz Main muon data path tested

Input FPGAs Logic FPGAs Sort FPGAsSeveral bad connections (single bits) identified

Due to soldering problems at mezzanine connectorsMost problems solved (re-soldering)

Remaining/future problems can be fixed by re-routing through spare signal lines between FPGAs

To be tested …Data path Input FPGAs MIP/ISO Assignment FPGAsMIP/Quiet bits from PSBs to GMT (over backplane)GMT result to GT (over backplane)Readout records to Frontend Card (over backplane)



CMS20


CSC-GMT Interconnection TestCSC-GMT Interconnection TestVienna, January 2005Vienna, January 2005

ObjectiveTest connection between CSC Trigger Muon Sorter and GMTTest GMT input stage

SetupCommon clock source: TTCex module with optical outputs (in 6U crate)CSC Trigger crate

Clock and Control Board (CCB) with TTCrm optical clock receiver mezzanine Muon Sorter (MS) SBS620 VME controller

Global Trigger / Global Muon Trigger Crate Timing (TIM6U) board with TTCrm optical clock receiver mezzanine Global Muon Trigger (GMT) TTCvi board to create periodic bunch counter reset every 3564th bx SBS620 VME controller

4 cables: shielded twisted pair, 34 pairs, halogen freelength: 11 m (max length in final system: 10 m)



CMS21


CSC-GMT Interconnection TestCSC-GMT Interconnection Test



CMS22



Test Patterns “Running one” pattern Random Pattern

Test setups Muon Sorter outputs connected to CSC0 .. CSC3 inputs of GMT Muon Sorter outputs connected to DT0..3, brl-RPC0..3, fwd-RPC0..3 inputs Muon Sorter outputs connected to CSC0, DT0, brl-RPC0, fwd-RPC0 inputs

GMT Input sampling At 160 MHz (4x per bx) Detect switching time of input signal Result: Switching always occurred at same phase. Stable clock relationship

Compare logic in GMT firmware Store reference sequence in RAM (500 words) Continuously compare incoming patterns with reference and count errors Can perform long-term tests at maximum speed



CMS23



ResultTest with pseudo-random data running for 16 hrs3.8 x 1013 bits transferredNo errors observed GMT inputs for all

regional muon triggerstested



CMS24


SummarySummary

CMS has three muon systems. All three are used in the L1 Trigger Regional Muon Triggers find muon candidates Global Muon Trigger combines these candidates

finds the best 4 overall candidates correlates with calorimeter information many advantages (proven by extensive simulation studies)

Higher efficiency Better rate handling Lower ghosting

Hardware development is now compete Single 9U GMT Logic Board + 3 PSB Input boards 10 Xilinx Virtex-II FPGAs on mezzanines Firmware design complete (based on VHDL model)

Online-Software development well underway Performed functional tests (more to come) Successful interconnection test with CSC Trigger

Many thanks to the HEPHYElectronics team:

Michael Padrta

Kurt Kastner

Herbert Bergauer



CMS25


Backup SlidesBackup Slides



CMS26


GMGMT Logic BoardT Logic Board



CMS27


FPGA Development: Logic FPGAFPGA Development: Logic FPGA

Many Functionsimplemented asLook-Up Tables Flexible:

GMT can be adaptedto characteristics ofregional trigger systems

Xilinx Block RAM anddistributed RAM

6 .. 14 bits input (addr)1 .. 18 bits output (data)

In Logic FPGA: 14 types of LUTs 52 sets of default values > 200 LUT instances

Need system to handle LUTs GMT Forward Logic FPGA



CMS28


Types of Look-Up-Tables in GMTTypes of Look-Up-Tables in GMT MIP & ISO assignment FPGA:

4 types of LUTs,(32 sets of default values)

-conversion 6 to 4 bits projection stage 1 projection stage 2 projection

Logic FPGA: 14 types of LUTs, (52 sets of default values) Matching Unit

Delta- calculation Match quality

Cancel-Out Unit Overlap conversion (6 to 4 bits for

match unit inside cancel-out unit) Cancel-Out Unit Delta- calculation

Sort Rank Unit Sort-Rank pt-q Sort-Rank -q Sort-Rank - Sort Rank combine

Merge Rank Unit Merge-Rank pt-q Merge-Rank -q Merge-Rank - Merge-Rank combine

Muon Merger Unit Pt mixing

Unit conversion -conversion (input to output)

Different default values for each LUT typefor DT, CSC, brlRPC, fwdRPC

or combinations thereof

Different default values for each LUT typefor DT, CSC, brlRPC, fwdRPC

or combinations thereof

Need system to handle LUTs



CMS29


Firmware Test: Data FlowFirmware Test: Data Flow

Cross-check of ORCA simulation with FPGA firmware & GMT board

Single type of hardware test file for all chips and for GMT board All GMT inputs & outputs Intermediate results at various

points in GMT

So far tested Logic FPGAs and MIP and ISO Assignment FPGAs Higgs 4 events Full agreement with ORCA

ORCA DT

CSC

RPC

Calo

GMT

GT

HW Testfile

digi

GMTInputs

GMTOutputs

intermediateresults

VHDL test bench(for single chip or entire GMT)

Chip or entire GMTVHDL

Behavioral / Gate Level

stim

uli

Ou

tpu

t si

gn

als

Intermediate signals

hits



CMS30


Automated testing of VHDL codeAutomated testing of VHDL code Example (continued)

./GMT > cvs co -r MIAU_timesim_works_03Jun2003 GMT (check out code)

/GMT > cd src/MipIsoAU/test/GMT > gmake test_miau (analyze + elaborate VHDL, simulate & check using default dataset)..-------------------- checking event nr 15 --------------------Simulated PHI SELECTBITS : 8192 0 0 0 8192 0 0 0 12288 0 0 0 12288 0 0 0form ORCA PHI SELECTBITS : 8192 0 0 0 8192 0 0 0 12288 0 0 0 12288 0 0 0Simulated ETA SELECTBITS : 256 0 0 0 256 0 0 0 384 0 0 0 384 0 0 0from ORCA ETA SELECTBITS : 256 0 0 0 256 0 0 0 384 0 0 0 384 0 0 0Simulated MIP/ISO bits : DTMIP: 0 0 0 0, RPCMIP: 0 0 0 0, DTISO: 1 0 0 0, RPCISO: 1 0 0 0From ORCA MIP/ISO bits : DTMIP: 0 0 0 0, RPCMIP: 0 0 0 0, DTISO: 1 0 0 0, RPCISO: 1 0 0 0..**** all tests succeeded.ncsim: *W,RNQUIE: Simulation is complete.ncsim> exit

/GMT >



CMS31


Selection of low-quality unconfirmed muonsSelection of low-quality unconfirmed muonsEfficiency and Trigger RatesEfficiency and Trigger Rates

50 %

GMT smart: 2.9 kHzGMT smart: 2.9 kHzGMT OR: 5.4 kHzGMT OR: 5.4 kHz

GMT AND: 2.0 kHzGMT AND: 2.0 kHz

GMTGMTEfficiencyEfficiency

ORCA 6.2.3 simulation

100 %

trigger rate from min. biasthreshold 14 GeV/c

EfficiencyEfficiency DT

CSC

RPC

0 %

100 %

GMT smart



CMS32


Efficiency versus PseudorapidityEfficiency versus Pseudorapidity

GMT

smart

DTCSC

RPC

Single muon sample (both charges): 2.5 < pT < 100 GeV/c No pT threshold applied




CMS33


Selection of low-quality unconfirmed muonsSelection of low-quality unconfirmed muonsEfficiency and Trigger RatesEfficiency and Trigger Rates

50 %

GMT smart: 97.3 %GMT smart: 97.3 %GMT OR: 98.1 %GMT OR: 98.1 %

GMT AND: 87.4 %GMT AND: 87.4 %

Single Muon Single Muon Trigger RateTrigger RateL=2x10L=2x103333 cm cm-2-2ss-1-1

from min. biasfrom min. biasGMT smart: 2.9 kHzGMT smart: 2.9 kHz

GMT OR: 5.4 kHzGMT OR: 5.4 kHz

GMT AND: 2.0 kHzGMT AND: 2.0 kHz

All values All values for |for || < 2.1| < 2.1

@ 14 GeV/c@ 14 GeV/c

EfficiencyEfficiency

14




CMS34


Mezzanine connectorsMezzanine connectors

Implementation and Test of the First- Level Global Muon Trigger of the CMS Experiment Hannes Sakulin...

Documents

Transcript of Implementation and Test of the First- Level Global Muon Trigger of the CMS Experiment Hannes Sakulin...