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Transcript of Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 11 Reduced Instruction Set...
![Page 1: Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 11 Reduced Instruction Set Computing.](https://reader036.fdocuments.net/reader036/viewer/2022062301/5697c0201a28abf838cd2321/html5/thumbnails/1.jpg)
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Chapter 11Chapter 11Reduced Instruction Set Reduced Instruction Set
ComputingComputing
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Chapter OutlineChapter Outline
• RISC RationaleRISC Rationale
• Instruction SetsInstruction Sets
• Instruction PipelinesInstruction Pipelines
• Register WindowsRegister Windows
• Instruction Pipeline ConflictsInstruction Pipeline Conflicts
• RISC vs. CISCRISC vs. CISC
• Itanium MicroprocessorItanium Microprocessor
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Speeding Up Typical CodeSpeeding Up Typical Code
• 100% of instructions @ 20 ns100% of instructions @ 20 ns
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Speeding Up Typical CodeSpeeding Up Typical Code
• 100% of instructions @ 20 ns100% of instructions @ 20 ns
• 98% of instructions @ 18 ns and 2% of 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 nsinstructions at 3 * 18 ns
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Speeding Up Typical CodeSpeeding Up Typical Code
• 100% of instructions @ 20 ns100% of instructions @ 20 ns
• 98% of instructions @ 18 ns and 2% of 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 nsinstructions at 3 * 18 ns
• 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c)
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Speeding Up Typical CodeSpeeding Up Typical Code
• 100% of instructions @ 20 ns100% of instructions @ 20 ns
• 98% of instructions @ 18 ns and 2% of 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 nsinstructions at 3 * 18 ns
• 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c)
• 20c vs. 17.64c + 1.08c20c vs. 17.64c + 1.08c
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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Speeding Up Typical CodeSpeeding Up Typical Code
• 100% of instructions @ 20 ns100% of instructions @ 20 ns
• 98% of instructions @ 18 ns and 2% of 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 nsinstructions at 3 * 18 ns
• 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c)
• 20c vs. 17.64c + 1.08c20c vs. 17.64c + 1.08c
• 20 20 18.72 18.72
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RISC CharacteristicsRISC Characteristics
• Fixed-length instructionsFixed-length instructions
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RISC CharacteristicsRISC Characteristics
• Fixed-length instructionsFixed-length instructions
• Limited loading and storing instructionsLimited loading and storing instructions
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RISC CharacteristicsRISC Characteristics
• Fixed-length instructionsFixed-length instructions
• Limited loading and storing instructionsLimited loading and storing instructions
• Fewer addressing modesFewer addressing modes
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RISC CharacteristicsRISC Characteristics
• Fixed-length instructionsFixed-length instructions
• Limited loading and storing instructionsLimited loading and storing instructions
• Fewer addressing modesFewer addressing modes
• Instruction pipelineInstruction pipeline
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RISC CharacteristicsRISC Characteristics
• Fixed-length instructionsFixed-length instructions
• Limited loading and storing instructionsLimited loading and storing instructions
• Fewer addressing modesFewer addressing modes
• Instruction pipelineInstruction pipeline
• Large number of registersLarge number of registers
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RISC CharacteristicsRISC Characteristics
• Hardwired control unitHardwired control unit
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RISC CharacteristicsRISC Characteristics
• Hardwired control unitHardwired control unit
• Delayed loads and branchesDelayed loads and branches
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RISC CharacteristicsRISC Characteristics
• Hardwired control unitHardwired control unit
• Delayed loads and branchesDelayed loads and branches
• Speculative execution of instructionsSpeculative execution of instructions
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RISC CharacteristicsRISC Characteristics
• Hardwired control unitHardwired control unit
• Delayed loads and branchesDelayed loads and branches
• Speculative execution of instructionsSpeculative execution of instructions
• Optimizing compilersOptimizing compilers
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RISC CharacteristicsRISC Characteristics
• Hardwired control unitHardwired control unit
• Delayed loads and branchesDelayed loads and branches
• Speculative execution of instructionsSpeculative execution of instructions
• Optimizing compilersOptimizing compilers
• Separate instruction and data streamsSeparate instruction and data streams
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RISC Instruction SetsRISC Instruction Sets
• Fewer instructionsFewer instructions
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RISC Instruction SetsRISC Instruction Sets
• Fewer instructionsFewer instructions
• Executed in one clock cycleExecuted in one clock cycle
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RISC Instruction SetsRISC Instruction Sets
• Fewer instructionsFewer instructions
• Executed in one clock cycleExecuted in one clock cycle
• Orthogonal, but not too orthogonalOrthogonal, but not too orthogonal– A OR B = NOT((NOT A) AND (NOT B))A OR B = NOT((NOT A) AND (NOT B))– A XOR B = (A AND (NOT B)) OR ((NOT A) A XOR B = (A AND (NOT B)) OR ((NOT A)
AND B)AND B)
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MIPS 4000 Instruction TypesMIPS 4000 Instruction Types
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SPARC Instruction FormatsSPARC Instruction Formats
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Instruction PipelinesInstruction Pipelines
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Instruction PipelinesInstruction Pipelines
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Instruction PipelinesInstruction Pipelines
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Instruction PipelinesInstruction Pipelines
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Instruction PipelinesInstruction Pipelines
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Instruction PipelinesInstruction Pipelines
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Instruction Pipeline Instruction Pipeline AdvantagesAdvantages
• Reduced hardwareReduced hardware
• Reduced clock periodReduced clock period
• Reduced complexity of memory Reduced complexity of memory interfaceinterface
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Pipeline Clock RatePipeline Clock Rate
• Limited by slowest stageLimited by slowest stage
• Speedup:Speedup:
• Example: Example:
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Register WindowingRegister Windowing
• Global RegistersGlobal Registers
• Windowed RegistersWindowed Registers
• Window Data RegisterWindow Data Register
• Window Pointer RegisterWindow Pointer Register
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Register WindowingRegister Windowing
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Register WindowingRegister Windowing
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Register WindowingRegister Windowing
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Register WindowingRegister Windowing
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Register RenamingRegister Renaming
• Arbitrary registers instead of fixed Arbitrary registers instead of fixed windowswindows
• More flexible, but harder to controlMore flexible, but harder to control
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Instruction Pipeline ConflictsInstruction Pipeline Conflicts
• Data conflictsData conflicts
• Branch conflictsBranch conflicts
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Data ConflictsData Conflicts
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Data ConflictsData Conflicts
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No-op InsertionNo-op Insertion
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No-op InsertionNo-op Insertion
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Instruction ReorderingInstruction Reordering
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Instruction ReorderingInstruction Reordering
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Instruction ReorderingInstruction Reordering
• Not always possibleNot always possible
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Stall InsertionStall Insertion
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Stall InsertionStall Insertion
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Data ForwardingData Forwarding
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Data ForwardingData Forwarding
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Data ForwardingData Forwarding
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Branch ConflictsBranch Conflicts
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Branch ConflictsBranch Conflicts
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No-op InsertionNo-op Insertion
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No-op InsertionNo-op Insertion
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Instruction ReorderingInstruction Reordering
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Instruction ReorderingInstruction Reordering
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Conditional BranchesConditional Branches
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No-op InsertionNo-op Insertion
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Instruction ReorderingInstruction Reordering
• Ignoring the data conflict:Ignoring the data conflict:
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Instruction ReorderingInstruction Reordering
• Ignoring the data conflict:Ignoring the data conflict:
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Instruction ReorderingInstruction Reordering
• Ignoring the data conflict:Ignoring the data conflict:
• Not always possible to reorder Not always possible to reorder instructions - sometimes must resort to instructions - sometimes must resort to no-op insertionno-op insertion
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AnnullingAnnulling
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AnnullingAnnulling
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Branch PredictionBranch Prediction
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RISC AdvantagesRISC Advantages
• Simpler control unitsSimpler control units
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RISC AdvantagesRISC Advantages
• Simpler control unitsSimpler control units
• Can run at higher clock frequenciesCan run at higher clock frequencies
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RISC AdvantagesRISC Advantages
• Simpler control unitsSimpler control units
• Can run at higher clock frequenciesCan run at higher clock frequencies
• More chip space for registersMore chip space for registers
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RISC AdvantagesRISC Advantages
• Simpler control unitsSimpler control units
• Can run at higher clock frequenciesCan run at higher clock frequencies
• More chip space for registersMore chip space for registers
• Easier to incorporate parallelismEasier to incorporate parallelism
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RISC AdvantagesRISC Advantages
• Simpler control unitsSimpler control units
• Can run at higher clock frequenciesCan run at higher clock frequencies
• More chip space for registersMore chip space for registers
• Easier to incorporate parallelismEasier to incorporate parallelism
• Simpler compilersSimpler compilers
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CISC AdvantagesCISC Advantages
• Complexity doesnComplexity doesn’’t always increase t always increase costcost
• Can incorporate previous designsCan incorporate previous designs
• Backward compatibilityBackward compatibility
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Itanium MicroprocessorItanium Microprocessor
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Itanium MicroprocessorItanium Microprocessor
• IA-64 ISAIA-64 ISA
• Explicitly Parallel Instruction ComputingExplicitly Parallel Instruction Computing
• PredicationPredication
• Speculative ExecutionSpeculative Execution
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PredicationPredication
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PredicationPredication
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Speculative ExecutionSpeculative Execution
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Speculative ExecutionSpeculative Execution
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SummarySummary
• RISC RationaleRISC Rationale
• Instruction SetsInstruction Sets
• Instruction PipelinesInstruction Pipelines
• Register WindowsRegister Windows
• Instruction Pipeline ConflictsInstruction Pipeline Conflicts
• RISC vs. CISCRISC vs. CISC
• Itanium MicroprocessorItanium Microprocessor