IMAGE COMPRESSSION USING LIFTING BASED DESCRETE WAVELET TRANSFORM

V.BALAKRISHNAN , STUDENT, FINAL YEAR ECE R.JEBARAJ, STUDENT , FINAL YEAR ECE.ABSTRACT

This paper proposes an efficient VLSI architecture for implementation of 2-D lifting-based discrete wavelet transform (DWT). The whole architecture was optimized in efficient pipeline and parallel design way to speed up and achieve higher hardware utilization. The prediction step and updation step using the same architecture, which reduced the size of the circuit. Exploited embedded mirror symmetric boundary extension technique to optimize the architecture for 1-D DWT. The architecture was coded in system c, implemented in a FPGA, and verified by a real-time platform which comprises a FPGA and a PC. Finally we try to reduce the complexity level up to 50 % in this attempt. In this face recognition system which has wide range of application in various field the over all output of this face recognition system will be mainly depends on the image compression quality. gvbalaaa@gmail.com icejeba@gmail.com Introduction

Standard application of Wavelet Transform which uses floating-point arithmetic means redundant processing which requires very complicated processing architecture and so it is very time-consuming. Most of the processing stages can be omitted or simplified using an adaptation to the integer arithmetic processing. In most cases it is possible to apply the transform using only integer addition and bit shifting operations. This can result in ultra-fast processing especially when implemented into FPGA Recently the lifting scheme (LS) [1] has become a revolutionary framework for efficient computation of the DWT.

The main advantages offered by LS lie in its better computational efficiency and in its improved modular structure, well suitable for scalable hardware implementation. Moreover, it has also been demonstrated [2] the feasibility of perfectly lossless Wavelet Transform, which is able to map integer numbers into integer coefficients. This paper goal is to investigate novel and efficient VLSI designs for the lifting algorithm. In order to reduce complexity for lossy compression, we design rational lifting coefficients for Daubechies (9,7) filters. The rational coefficients allow the integer execution units to be implemented. In addition, based on the proposed rational lifting algorithms, we present an efficient FPGA implementation for the lifting scheme in order to fully satisfy different possible requirements.

In fact the proposed architecture is well suitable for real-time applications, form very low bit rate to high definition environments.

Lifting Wavelet TransformSweldens first introduced the concept of second generation wavelet, which is the so-called lifting scheme. Comparing with traditional Mallat Construction of WT, the lifting scheme is completely based on construction in spatial domain and dose not depend on the concept of translates and dilates and also does not require any tools of frequency analysis, which main idea is founded on the theory of bi-orthogonal wavelets and perfect reconstruction filter bank. Daubechies and Sweldens proved that any wavelet with FIR filters can be factorized into a finite number of lifting steps and all of the conventional WT based on Mallat algorithm may find their equivalent lifting scheme [4].

Lifting scheme

Generally, lifting scheme is composed of three steps: Split/Merge, Prediction and Update [5]. Let denotes input signals.

The general lifting algorithm is described as follow [2].

1. Splitting The input signals, Xi are separated into two sets of even and

odd samples.

2. Prediction

The odd samples are predicted by linear interpolation using coefficients.

3. UpdateThe even samples are updated with coefficient Un (k).

The prediction step and the update step may be performed in N sub-steps. The number of sub-steps N nd the values of Pn(k) and Un(k) are depended on wavelet filters.

4. Normalization

Low pass and high pass outputs must be normalized to get the correct results. Thus,

Then the next transform step can be performed, but only using the low-frequency component just as WT. The reconstruction of LWT is an inverse process of decomposition. The lifting scheme of decomposition and reconstruction for 1-D signal is illustrated in Fig.1

1.Reconstruction for 1-D signalFPGA DesignThe proposed architecture in this section for the partitioned 2D-DWT mainly consists of two one dimensional DWT units (1D-DWT) for horizontal and vertical transforms, a control unit realized as a finite state machine, and an internal memory block. For illustration see Fig 3. To process a sub-image, all rows are transferred to the FPGA over the PCI bus and transformed on the fly in the horizontal 1D-LWT unit using pipelining. The coefficients computed in this way are stored in internal memory of different types. The coefficients corresponding to the rows of the subimage itself are stored in single port RAM. Now the vertical transform levels can take place. This is done by the vertical 1D-LWT unit [8]. The control unit coordinates these steps in order to process a whole subimage and is responsible for generating enable signals, address lines, and so on.

At the end, the wavelet transformed sub-image is available in the internal RAM.

Fig .2

To implement one level of DWT using the lifting method, the following steps are necessary: split the input into coefficients at odd and even positions, perform a predict-step and update-step. An efficient realization of the last two steps is given in Fig .4. The computation is split into the elementary pieces, which are additions, subtractions, and shifts. With the given arrangement, the combinational function between two flip-flops fits into one column of CLBs. Furthermore the registered adder/subtracters generated by logic block are configured such that the dedicated carry logic in the XC4000 series is used.

Fig .3 PREDICTION

Fig .4 UPDATIONIn order to perform a faster transform, which is needed during the first and second level, the w-bit input 1DDWT has to be parallelized. One approach is to process four rows in parallel but we have to take into account the growing chip area. Another disadvantage is the fact that we have to split the RAM into four slices, where each slice corresponds to a w-bit input 1DDWT. This results in additional data and address lines and slows down the access time to the RAM. As a direct consequence of this, the order of the data transfered to the FPGA has to be adapted accordingly. To avoid the disadvantages just mentioned we have implemented a filter unit which takes four pixels of the same row at a time. Instead of 12 w-bit and 12 w+1-bit flip-flops, 4 predict and update units we only need 4 w-bit and 5 w + 1-bit flip-flops and 2 predict and update components, if the bit-width of the input coefficients/pixels is w. We use this unit for both the first and the second level of the transform.

Simulation Result1. ORIGINAL IMAGE

2. EIRST LEVEL DECOMPOSITION RESULT]3. SECOND LEVEL DECOMPOSITION RESULT

4. COMPRESSED IMAGE

Conclusion

In this paper, a lifting based architecture which is called a 22 array is proposed to take advantage of all the parallelisms effectively. For an NN DWT, our architecture takes only N2/4+N/2+1 time units while maintain the memory requirement to only 3N+2. The advantages of lifting scheme are less operations, in-place computation, and less memory requirement. At the same time, the coefficients computed using lifting scheme are identical with the convolutional implementation. The new fully integer processing of the wavelet transform scheme compression enables a very fast application and thus it can be very useful in the application in real-time systems. The most important property of this concept is the possibility of a simple and fast application into FPGA or ASIC chip. And also we have developed a FPGA-based implementation.FUTURE WORK

Here we completed image compression for face recognition system; in future we are going to perform video compression using the same platform.Also, perform pre-processing steps such as lighting correction, Histogram equalization both for video and image compression. REFRENCES

[1] S. Mallat, A Wavelet Tour of Signal Processing. New York: Academic, 1998.

[2] R. R. Coifmen and M. V. Vickerhauser, Entropy-based algorithms for best basis selection, IEEE Trans. Inf. Theory, vol. 38, no. 3, pp. 713718, Mar. 1992.

[3] Z. Xiong, K. Ramchandran, and M. T. Orchad, Wavelet packet image coding using space-frequency quantization, IEEE Trans. Image Processing, vol. 7, pp. 160174, 1998.

[4] D. Sinha and A. H. Tewfik, Lowbit rate transparent audio compression using adapted wavelets, IEEE Trans. Signal Process., vol. 41, no. 12,pp. 34633479, Dec. 1993.

[5] X. Wu, Y. Li, and H. Chen, Programmable wavelet packet transform processor.