MOSTEK 16,384 x 1 Bit Dynamic Ram MK 4116P-2/3

FEATURES o Recognized industry standard 16-pin config­

uration from MOSTEK

o 150ns access time, 375ns cycle (MK 4116-2) 2 00ns access time, 375ns cycle (MK 4116-3)

o ± 10% tolerance on all power supplies (+12 V, ±5V)

o Low power: 462mW active, 2 0mW standby (max)

o Output data controlled by CAS and unlatched at end of cycle to allow two dimensional chip selec­tion and extended page boundary

DESCRIPTION

The MK 4116 is a new generation MOS dynamic random access memory circuit organized as 16,384 words by 1 bit. As a state-of-the-art MOS memory device, the MK 4116 (16K RAM) incorporates advanced circuit techniques designed to provide wide operating margins, both internally and to the system user, while achieving performance levels in speed and power previously seen only in MOSTEK's high performance MK 4027 (4K RAM).

The technology used to fabricate the M K 4116 is MOSTEK's double-poly, N-channel silicon gate, POL Y lie process. This process, coupled with the use of a single transistor dynamic storage cell, pro­vides the maximum possible circuit density and rei iabil ity, wh ile maintaining high performance

FUNCTIONAL DIAGRAM

o Common 1/0 capability using "early write" operation

o Read-Modify-Write, liAS-only refresh, and Page­mode ca/Jability

o All inputs TTL compatible, low capacitance, and protected against static charge

o 128 refresh cycles

capability. The use of dynamic circuitry through­out, including sense amplifiers, assures that power dissipation is minimized without any sacrifice in speed or operating margin. These factors combine to make the MK 4116 a truly superior RAM product.

Multiplexed address inputs (a feature pioneered by MOSTEK for its 4K RAMS) permits the MK 4116 to be packaged in a standard l6-pin DIP. This recognized industry standard packa�e configuration, while compatible with widely available automated testing and insertion equipment, provides highest possible system bit densities and simplifies system upgrade from 4K to 16K RAMs for new generation applications. Non-critical clock timing requirements allow use of the multiplexing technique while main­taining high performance.

PIN CONNECTIONS

vee 16 vss DIN 2 15 CAS WRITE 3 14 DOUT

RAS 4 13 As Ao 5 12 A3 A2 6 II A4 AI 7 10 A5 Voo 8 9 Vee

PIN NAMES

�A6

DIN g��T

iNRiTE VBB Vee VDD VSS

ADDRESS INPUTS COLUMN ADDRESS STROBE DATA IN DATA OUT ROW ADDRESS STROBE READIWRITE INPUT POWER (-5V) POWER (+5V) POWER (+12V) GROUND

III ALFRED NEVE - ENATECHNIK GmbH Zentrale: SchilierstraBe 14,2085 Quickborn,Telefon Sa.-Nr.: 0 41 06/612-1, Telex: 02-13590 Hannover 05 11/88 60 8 6 1 Dusseldorf 02 11/66 61 45 1 Darmstadt 0 61 51/264 4 6 1 Stuttgart

Verkaufsburos: Berlin 03 0/4 33 30 52 11173 6357 1 Munchen08 9/47 30 23

2

ABSOLUTE MAXIMUM RATINGS*

Voltage on any pin relative to Vss .................... -O.S V to +20V Voltage on V D D, VCC supplies relative to VSS .......... ....:1.0V to + lS.0V

'Stresses greater than thosa listed under .. Absolute Ma)(imum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi· tions above those indicated in the opera' tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilitY.

VBS-VSS (V D D-VSS >OV) .................................. OV Operating temperature, T A (Ambient) ................... O°C to + 70t Storage temperature (Ambient). ..................... -S SoC to + lS 0°C Short circuit output current ................................. S OmA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Watt

RECOMMENDED DC OPERATING CONDITIONS (O°C .;:;;T A';:;; 70cC) 1

PARAMETER SYMBOL MIN

Supply Voltage VOO 10.8 VCC 4.5 VSS 0 VBB -4.5

Input High (Logic 1) Voltage, RAS, CAS, WRITE

VIHC I 2.7

Input High (Logic 1) VOltage, VIH 2.4 all inputs except RAS, CAS WRITE

Input Low (Logic 0) Voltage, VIL -1.0 all inputs

DC ELECTRICAL CHARACTERISTICS

TYP MAX UNITS NOTES

12.0 13.2 Volts 2 5.0 5.5 Volts 2,3 0 0 Volts 2 -5.0 -5.5 Volts 2

- 7.0 Volts 2

7.0 Volts 2

- .8 Volts 2

(O°C';:;; TA� 70°C)1 (V D D = 12.0V ± 10%; VCC = S.OV ± 10%; VSS = -S.OV ±10%; VSS = OV)

PARAMETER

OPERATING CURRENT Average power supply operating current (RAS, CAS cycling; tRC 375ns)

STANOBY CURREN T Power supply standby current (R"AS '" VIHC, °OUT High Impedance)

REFRESH CURRENT Average power supply current, refresh mode (RAS cycling, CAS ----

V I He; tRC '" 375ns)

PAGE MOOE CURRENT Average power supply current, page-mode operation (RAS =VIL,CAS cycling; tpc 225nsl

INPUT LEAKAGE Input leakage current, any input (VBB -5V, OV � VIN � +7.0V, all other pins not under test o volts)

OUTPUT LEAKAGE Output leakage current (OOUT is disabled, OV � VOUT � +5.5V)

OUTPUT LEVELS Output high (Logic 1) voltage ( lOUT = -5mA)

Output low (Logic 0) voltage ( lOUT = 4.2 mAl

NOTES.

SYMBOL

1001 ICCl IBBl

1002 ICC2 IBB2

1003 ICC3 IBB3

1004 ICC4 IBB4

II(L)

10(L)

I VOH

VOL

1. T A. is specified here for operation at frequencies to tRC;;;;' tRC Imln). Operation at higher cycle rates with reduced ambient temperatures and higher power dissipation is permissible, how­ever. provided AC operating parameters are met. See figure 1 for derating curve.

2.

3.

A II vo I tages referen ced to V SS.

OutPut voltage will swing from VSS to Vee when activated with no current loading. For purposes o� maintaining data in standby

4.

5.

MIN MAX UNITS NOTES

35 mA 4 5

200 f.J.A

1.5 mA -10 10 f.J.A

100 J.LA

25 mA 4 -10 10 J.LA

200 J.LA

27 mA 4 5

200 J.LA

-10 10 f.J.A

-10 10 I J.LA

2.4 Volts 3

0.4 Volts

mode, VCC may be reduced to VSS without affecting refresh operations or data retention. However, the V OH (min) specifica· tion is not guaranteed in this mode.

IDD1. IDD3. and IDD4 depend on cycle rate. See figures 2,3, and 4 for I DD limits at other cycle rates.

ICCl and ICC4 depend upon output loading. During readout of high level deta VCC is connected through a low impedance (135" tYp) to data out. At all other times ICC consists of leakage currents only.

-ElECTRICAL (O'C� TA�

PARAMETER

Random read or write cycle time

Read-write cycle time

Page mode cycle time

Access time from RAS

dow Address set-up time

Column

Column Address

10.

11.

12. Measured equivalent

13. tOFF open levels.

defines the time at which output achieves the condition and not referenced to output voltl>lI"

NOTES

9 9

8

15

Cl"'"clta,,,,,, calculated from the equation C and power supplies at nornfna{

levels.

18. IHe DOUT' 3

AC ELECTRICAL CHARACTERISTICS (DoC < TA < 70°C) (VOO = 12.0V ± 10%; VSS = OV; VBB = -5.0V ± 10%)

PARAMETER SYMBOL

Input Capacitance (AO-A6), DIN

Input Capacitance RAS, CAS, WRITE

Output Capacitance (DOUT)

CYCLE TIME tllC (nsl 315

� 70-H-+-?! 0.. ::! UJ f-f- 60 Z UJ iii ::E <r

1.0 20 3.0

CYC LE RATE (MH11= 103/t RO (ns )

4.0

� Maximum ambient temperature versus cycle rate for extended frequency operation. T A (max) for operation at cycling rates greater than 2.66 MHz (tCYC < 375ns) is determined by

CI1

CI2

Co

T A (max) (OC] 70-9.0 x {cycle rate (MHz] - 2 .66 1 .

CYCLE TIME t IIC (nsl 1000 500 4<;'0 300 250

�t-4+ ., +tl I

d ' I 1 1/ i/

SOmA

, 1 40mA

f-

I I ! I , I I

I

y��

IV VI

ill p-'I-H i 1-:-Z UJ 0:: I I �� /1 I --l l+l J.;' I � 30mA U

! I-f-t� L

� 0.. is (/)

A' 'I I

, I

, L

� i ,.- ' I i Iii I _ 20mA

a o

.... i/ : '" ' i I 1 1/ !- I

!OmA i/I"'l..'±'_ I --t- I

i tTT I

I 0 io 3'.0 40

o

CYCLE RATE (MHz)= 103/t 110 (ns) !:.JJL1. Maximum I DDl versus cycle rate for device operation at extended frequencies. IDDl (max) curve is defined by the equation:

IDDl (max) [mA] 10+9.4xcyclerate [MHZ]

TYP

4

8

5

i f-Z UJ i => U

� t => <J) <t 0

.S' x « :::f.

MAX UNITS NOTES

5 pF 17

10 pF 17

7 pF 17,18

CYCLE TIME t IIC (mil

2.0 3.0 40

CYCLE RATE (MHz)' 103/t 110 (ns) � Maximum I DD3 versus cycle rate for device ope ration at extended frequencies. I DD3 (max) curve

is defined by the equation: IDD3 (max) [mA]� 10 + 6.5 x cycle rate (MHZ]

40mA

30m A

20mA

lOrnA

CYCLE TIME t PC (ns)

CYCLE RATE (MHz): 10 3/t PC (ns) Fig. 4 Maximum 10 D4 versus cycle rate for device operation in page mode. IDD4 (max) curve is defined by the equation IDD4 (max) [rnA] 10 + 3.75 x cycle rate [MHZ]

READ CYCLE

V1HC-RAS V1L -

CAS V1HC -

V1L -

VIH_ ADDRESSES I

IL- ,

WRITE V IHC-; V IL -

VOH D O U T VOL

WRI CYCLE (

RA S V,

L

CAS V1HC -V1L -

ADDRESSES

tRCO

LV

AR---�

COLUMN ADDRESS

l...--- t CAC

tRAC

OPEN

tRC t RAS

tAR --1 I

I

I

J tOFF

VALID DATA

t RSH t RP

t CAS

O P E N

5

READ-WRITE/READ-MODIFY-WRITE CYCLE

,..------ t cwo ----..;

DOUT VOL---

------------------------------ OPEN

"RAS-ONL Y" REFRESH CYCLE NOTE: CAS = VIHC, WRITE = Don't Care 1-'11-_________ _

ADDRESSES VIH-V IL -"""""".:.J....J...J...t...I....J...J...t...I....t..U ,'_ _______ --"

PAGE MODE READ CYCLE

t ASR-.., v,,; ADDRESSES v I

'l-

Dour

PAGE MODE WRITE CYCLE

ADDRESSES

7

write are re­

rather than DIN is referenced to depicting the read­

while the "early referenced to CAS).

read cycle or high state

cycle in which from selected cell

in the specified

D

is not latched, CAS is not required to turn off the outputs of unselected memory devices in a matrix. This means that both CAS and/or RAS can be decod­ed for chip selection. If both RAS and CAS are decoded, thim a two dimensional (X,Y) chip select array can be realized.

Extended Page Boundary - Page-mode operation allows for successive memory cycles at multiple column locations of the same row address. By de­coding CAS as a page cycle select signal, the page boundary can be extended beyond the 128 column locations in a single chip. (See page-mode operation).

OUTPUT INTERFACE CHARACTERISTICS

The three state data output buffer presents the data output pin with a low impedance to VCC for a logic 1 and a low impedance to V SS for a logic O. The effective resistance to V CC (logic 1 state) is 420 n maximum and 135n typically. The resistance to VSS (logic 0 state) is 95 n maximum and 35 n typically. The separate V CC pin allows the output buffer to be powered from the supply voltage of the logic to which the chip is interfaced. During battery standby operation, the Vce pin may have power removed without affecting the MK 4116 refresh operation. This allows all system logic except the RAS timing circuitry and the refresh address logic to be turned off during battery standby to conserve power.

PAGE MODE OPERATION

The "Page Mode" feature of the MK 4116 allows for successive memory at mUltiple column locations of the same row address with increased speed without an increase in power. This is done by strobing the row address into the chip and maintain­ing the RAS signal at a logic 0 throughout all success­ive memory cycles in which the row address is com­mon. Th is "page-mode" of operation wi II not d issi pate the .J2.QYVer associated with the negative going edge of RAS. Also, the time required for strobing in a new row address is eliminated, thereby decreas­ing the access and cycle times.

The page boundary of a single MK 4116 is limited to the 128 column locations determined by all combi­nations of the 7 column address bits. However, in system applications which utilize more than 16,384 data words, (more than one 16K memory block), the page boundary can be extended by using CAS rather than RAS as the chip select signal. RAS is applied to all devices to latch the row address into each device and then CAS is decoded and serves as a page cycle s�lect signal. On those devices ich receive both RAS and CAS will execute a read or write cycle.

REFRESH

Refresh of the dynamic cell matrix is accomplished by performing a memory cycle at each of the 128 row addresses within each 2 millisecond time interval. Although any normal memory cycle will perform the refresh operation,�hjs function most easily accomp­lished with "RA -only" RAS-only refresh results in a substantial reduction in power. This reduction in power is iDD3 specification.

POWER CONSIDERATIONS

Most of the circuitry used in the MK 4116 is dynamic and most of the power drawn is the result of an address strobe edge. Consequently, the dynamic power is primarily a function of operating frequency rather than active duty cycle (refer to the MK 4116 current waveforms in figure 5). This current char­acteristic of the M K 4116 precludes inadvertent burn out of the device in the event that the clock inputs become shorted to ground due to system malfunction.

Although no particular power supply noise restriction exists other than the supply voltages remain within the specified tolerance limits, adequate decoupling should be provided to suppress high frequency noise resulting from the transient current of the device. This insures optimum system performance and reliability. Bulk capacitance requirements are minimal since the MK 4116 draws very little steady state (DC) current.

In system applications requiring lower power dissi­pation ,the operating frequency (cycle rate) of the MK 4116 can be reduced and the (guaranteed maxi­mum) average power dissipation of the device will be lowered in accordance with the IDOl (max) spec limit curve illustrated in figure 2 . NOTE: The MK 4116 family is guaranteed to have a maximum I D D 1 requ i rement of 35mA @ 375ns cycle with an ambient temperature range from OOto 70 'C. A lower operating frequency, for example 1 microsecond cycle, results in a reduced maximum 1001 require­ment of under 20mA with an ambient temperature range from Oto 70 C.

It is possible to operate certain versions of the MK 4116 family (the -2 and -3 speed selections for example) at frequencies higher than 2.66 MHz (37505 cycle), provided all AC operating parameters are met. Operation at shorter cycle times « 375ns) results in higher power dissipation and, therefore, a reduction ir arr,bient temperature is required. Refer to figure 1 for derating curve.

RC;'s ONLY CYCLE

50 NANOSECONDS! DIV!SION

5 Typical Current Waveforms 9

Although RAS and/or CAS can be decoded and used as a chip select signal for the MK 4116,overall system power is minimized if the Row Address Strobe (RAS) is used for this purpose. All unselected de­vices (those which do not receive a RAS) will remain in a 10"Y-Qower (standby) mode regardless of the state of CAS.

POWER UP

The MK 4116 requires no particular power supply sequencing so long as the Absol,ute Maximum Rating Conditions are observed. However, in order to insurE: compliance with the Absolute Maximum Ratings, MOSTE K recommends sequencing of power suppl ies

PACKAGE DESCRIPTION 16-lead side-brazed ceramic dual-in-line hermetic package

10

such that VBB is applied first and removed last. VBB should never be more positive than VSS when power is applied to VOO.

Under system failure conditions in which one or more supplies exceed the specified limits significant addi­tional margin against catastrophic�ice failure may be. achieved by forcing RAS and CAS to the inactive state (high level) .

After power is appl ied to the dev ice, the M K 4116 requires several cycles before proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose.

TYPICAL CHARACTERISTICS

TYPICAL ACCESS TIME (NORMALIZEO) \II. VOO 1.2 I

TJ =SO'C

g "'-...

2: 1.0 � � a:

, � � 0 9 I ----a 2: I I

�08 I

I a: ,...

I

'>

0.7 10 11 12 13 VOO SUPl'l Y VOLTAGE (VOL TSI

14

TYPICAL ACCESS TIME iNORMALIZEO) ¥t. Vss 1.2 I

TJ'SO'C I lr---

r-----

0.7 -4.0

I I i i I I

-4.5

i

I I i

I

-5 .0 -5.5 Vas SUPPL Y VOLTAGE (VOL TSI

�.O

TYPICAL ACCESS TIME ,NORMALIZED) V$. Vec 1.2

� 1.1 TJ'50't ! I

u

0.7 4.0

I I

I I "

I I I

4.5 5.0 5.5 vec SUPPL Y VOLTAGE IVOL TSI

6.0

TYPICAL ACCESS TIME (NORMALIZED) 1.2,--_r-'y,;,;··..;;J.::U.:;NC;;:,cT:.;.IO:,;N.;,;.;,;T::;EM::;;..PErRc.;:A..;,T.:,;U;.;Rc:.E:....,

51 1.1 I---+_�--+_---:,/L-----l � ... � 101--_---!_� __ �"-__ + __ _l a:

� t: O.91---71"----r----r--_l � a: ... 0.8t_----+---_t_---+----I

C.7'-::: __ -:::-___ -:l::-__ -'::--_:-:-! -10 20 50 80 110 T J. JUNCTION TEMPERATURE r C)

TYPICAL 1001 WI. VOO ��----�----�----�----�

TJ'5O'C i30I----+---+---+--=:-l ... z .... �25�---+--���-----t----� a > &:20/----+--=""'"'''''''''-----+----1 iii I

.Rc•75Om OI51 ____ ��---��---=�----� 9 r

,0 �IO�----- ,�,------�------�,3�----�1� 4

VOO SUPI'L Y VOL TAGE (VOL TSI

1.4,.----,----..,=.=-..;:..::,-----,

- TJ'5CfC 1 1.21---'--+----+---�+_---I ... z .... � I.OI-----+----+----+----l ::> u > i O.8�----+_---+:,...-=_t_---�

� N �06t----+-----+----+----i

0.4 �,;:;0------1f:,:----"C,:::2:------.:,!:-3-----�,4 VOO SUPPL Y VOL TAGE (VOL TSI

18

8 10

TYPICAL 1003 V$. VOO

I / �C'375n1

,/ I tRC =0 SOOns

� � -

'RC=75Om -1-'

V--� I -

11 12 13 Voo SUPPLY VOL TAGE (VOL TSI

TYPICAL 1004 VI VOO

14

2O ,.----,-----�------r-----�

;f TJ'SO't !'81-----+---+-���--_l ... z ...

�161----����1---_l---_l ::> u > i14f---__ +_---+-���------+ � ... � 121---�r----l1-���----_l

10�10�----�-----c�------�---�,4 VOO SUPPL Y VOL TAGE (VOL TS)

TYPICAL 1001 VI JUNCTION TEMPERATURE

tvoo ,,3.2V

10 -10

1.4

'RC' 375m

I ItRC·SOOn.

I I ! tRC' 7SOn.

i i !

20 50 80 "0 TJ. JUNCTION TEMPERATURE ('CI

TYPICAL 1002 VI JUNCTION TEMPERATURE

VOO ·13.2� I

0.4 -10

, I I

---t-----..,

I '---

20 50 80 TJ.JUNCTION TEMPERATURE ('Cl

TYPICAl1003vsJUNCTION TEMPERATURE

110

;f !18�--��--���-ffi< � 16�------4-------�-------+-------4 ::> t.) > ..J � 14r-

------+_-----=�---c������ iii '" 2 121--______ �------+-------+ __ ----�

... Z '"

I tRC '"' 750m: �,�0�----�2O�----�50�----��BO�------J!,0

TJ. JUNCTION TEMPF.RATURE ('Cl

TYPICAL 1004 YS. JUNCTION TEMPERATURE 20

!pC" 250ns

� 161--------�------+-------+------_l ::> u >

'PC '"37511. t 14�_=----+_------�--����=----4 iii ..,. tPC .. SOOn • �12r_------�------+---=���----�

1��,0r-----�2O�----�50�----�BO�----�, l0 TJ, JUNCTION TEMPERATURE I 'C.

11

TYPICAL CLOCK INPUT LEVELS ... VDD 3.0

TJ = SO'C

2.5 VB8 =-5.0V

VIHC (MINI I--!-"

I VllC (MAX)

I l 0.5 10 11 12 13 14

VDD SUPPL V VOLTAGE (VOL TSI

TYPICAL ADDRESS AND DATA INPUT lEVELS ••. VDO

iii' ... ... o

3.0

2.5

� 2.0 ...I W > W ..J 1.5 ... :> ... z -1.0

0.5

:rJ=sot I VBB=-5.0VI I

I I I i I

� .---�IH(MINI

..... I-

-!-" VIL (MAX)

, I !

10 11 12 13 14 VDD SUPPLY VOLTAGE (VOLTS)

TYPICAL CLOCK INPUT lEVELS v,. VSS 3.0

TJ" so'c

2.5 VDD = 12.0V

iii' :; 02.0 � ... w � 1.5 ... ... � !l: 1.0

0.5 -4.0

I -4.5

I I i I i 1

I -5.0

VIHC (MIN)

VILC (MAX

-5.5 -6.0 Vss SUPPL Y VOL TAGE (VOL TSI

TVPICAL ADDRE.lS AND DATA INPUT LEVELS ... VSS 3.0

TJ 50'C ! 2.5 IvDD =12.0\1

iii' :; o �2.0 ..J w > w ...11.5 � z -1.0

0.5 -4.0

VIH(MINI

VIL (MAXI

-4.5 -5.0 -5.5 -6.0 Vss SUPPL Y VOLTAGE (VOL TSI

TYPICAL CLOCK INPUT LEVELS V$. TJ 3.0 I

VDD =12.0V VSS =-5.0V

1.0

0.5 -10

-

I I I

VIH�IN

VILC (MAX

I 20 50 80

TJ, JUNCTION TEMPERATURE (' C)

-

110

TYPICAL ADDRESS AND DATA INPUT LEVELS V$. T J

iii' ... ..J

3.0

2.5

� 2.0 ..J w

� 1,5 ... :> ... z -1.0

!vDO =12.0V

VSS =-5.0V

VIHIMINI

VILIMAX)

0.5 -10 20 50 80 110

T J, JUNCTION TEMPERATURE ('CI

9.76/ AT3289-2. 77