IEEE TRANSACTIONS VOL. Introduction Multiple-Valued Logic · Introduction Multiple-ValuedLogic...
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IEEE TRANSACTIONS ON COMPUTERS, VOL. c-35, NO. 2, FEBRUARY 1986 Introduction Multiple-Valued Logic M ULTIPLE-valued logic has been the object of much research over the last fifteen years. Since 1971, there has been an annual symposium devoted exclusively to the subject and, during that time, nearly 600 papers have ap- peared in its Proceedings. In addition, a large number of technical papers have appeared elsewhere together with a number of survey articles [1]-[4] and a number of textbooks [5]-[7]. Much of the older work was of a purely theoretical nature concerned with the functional completeness of sets of operators, functional minimization, and similar problems from switching theory and logic design. Work on the hard- ware implementation of multiple-valued devices has been more recent (see [8] for an early discussion). There are three main directions for the work in multiple- valued logic. The pressure of attempting to reduce intercon- nection complexity and reduce chip area on VLSI is giving impetus to the investigation of many different hardware im- plementations of multivalued systems. The largest commer- cial use of multiple-valued logic is in the area of multivalued memories and this is discussed in the paper by Rich. The second area concerns the use of multiple-valued systems to assist in the analysis of problems in two-valued digital sys- tems, such as the design of fault simulators (see the paper by Hayes). Finally there is stili on going work in the general area of switching theory to yield the best methodologies for the design of multivalued systems. The papers in this Special Issue span the full range of areas from applications to VLSI technology and design techniques. They consist of papers submitted especially for this Special Issue together with some selected papers from the Fifteenth International Symposium on Multiple-Valued Logic. In the first paper Rich gives us a survey of various tech- niques for storing multiple values in a single memory lo- cation. This is one area where we have seen multiple-valued devices in commercial use and the paper addresses both ROM's and dynamic RAM's together with the peripheral circuitry needed to distinguish between the states stored in the memory cell. Hayes applies multiple-valued logics to the analysis of binary switching circuits (especially MOS VLSI circuits) under uncertainty, hazards and energy considerations and develops the corresponding algebraic theory for both the ordered and unordered case. His approach is useful for tim- ing and hazard analysis and provides a rigorous framework for designing gate-level logic simulation programs. Maruoka studies the asymptotic (Lupanov type) com- plexity Cm (f) of the minimal representation of an n -vari- able Boolean switching function f by a two-valued circuit with binary gates which is partitioned so that every pair of blocks has at most m interconnections. To get lower and upper bounds for Cm(f) each block is treated as a multiple- valued gate. The use of charge coupled devices (CCD's) and their basic building blocks is addressed by Abd-El Barr, Zaky, and Vranesic. The authors discuss realization techniques for multivalued multithreshold functions using CCD technology. Two new decomposition techniques are proposed together with synthesis methods. The emphasis of the paper is on 4-valued systems. Heuristic sum of product minimizations of a multiple- valued function are considered by Besslich. The expressions use either max or plus (truncated from above) and shift and literal operators but the search is much more complex than in the two-valued case. The method uses a direct cover ap- proach to lead to near minimal solutions. Huntsberger, Rangarajan, and Jayaramamurthy apply Zadeh's fuzzy set theory to the computer vision problem- one of the most difficult tasks within the framework of expert systems - in which a three-dimensional model of a natural scene must account for uncertainty due to incomplete input cues; fuzzy sets are also used for color edge distinction and shape representation. Mangin and Current discuss the performance of prototype CMOS binary to quaternary encoder and quaternary to binary decoder test circuits that have been realized on a gate array IC chip. Yamakawa and Miki consider the circuits that would be required for the construction of a "fuzzy computer." They describe nine basic fuzzy logic circuits which employ p-ch and n-ch current mirrors. They show that any complex fuzzy hardware system using these basic circuits can be realized with only one kind of master slice. Hu and Smith propose a new scheme for VLSI scan testing designs in which binary clocking signals are replaced by ternary clocking signals. The great advantage of this ap- proach is that it enables the mode-selecting line to be dis- pensed with leading to a significant saving in chip area and reduced circuit interconnection complexity. However, it re- tains the same high testability as the binary scan method. Sengupta and Sen introduce a general model of a system with three-valued test outcomes and its diagnosability. Nec- essary and sufficient conditions for the diagnosability of such a system are developed in the correspondence. Reischer and Simovici survey the iterative properties of multiple-valued functions for synthesis by circuit cascades. Their approach is based on transformations of finite sets and involves their integration powers and roots. Mukaidono studies the regular three-valued functions which are suitable for treating ambiguity. These important functions are treated from three different standpoints, de- fined axiomatically and represented by a canonical form. Moraga is concerned with the calculation of the Chresten- son spectrum for an arbitrary multiple-valued function. He proposes the use of a systolic system as a dedicated piece of hardware for the computation and compares the resulting system with similar two-valued implementation#. The Guest Editors would like to thank all those persons in- volved in producing this Special Issue, especially the authors 97
Transcript of IEEE TRANSACTIONS VOL. Introduction Multiple-Valued Logic · Introduction Multiple-ValuedLogic...
IEEE TRANSACTIONS ON COMPUTERS, VOL. c-35, NO. 2, FEBRUARY 1986
Introduction Multiple-Valued Logic
M ULTIPLE-valued logic has been the object of muchresearch over the last fifteen years. Since 1971, there
has been an annual symposium devoted exclusively to thesubject and, during that time, nearly 600 papers have ap-
peared in its Proceedings. In addition, a large number oftechnical papers have appeared elsewhere together with a
number of survey articles [1]-[4] and a number of textbooks[5]-[7]. Much of the older work was of a purely theoreticalnature concerned with the functional completeness of sets ofoperators, functional minimization, and similar problemsfrom switching theory and logic design. Work on the hard-ware implementation of multiple-valued devices has beenmore recent (see [8] for an early discussion).
There are three main directions for the work in multiple-valued logic. The pressure of attempting to reduce intercon-nection complexity and reduce chip area on VLSI is givingimpetus to the investigation of many different hardware im-plementations of multivalued systems. The largest commer-cial use of multiple-valued logic is in the area of multivaluedmemories and this is discussed in the paper by Rich. Thesecond area concerns the use of multiple-valued systems toassist in the analysis of problems in two-valued digital sys-
tems, such as the design of fault simulators (see the paper byHayes). Finally there is stili on going work in the general area
of switching theory to yield the best methodologies for thedesign of multivalued systems.The papers in this Special Issue span the full range of areas
from applications to VLSI technology and design techniques.They consist of papers submitted especially for this SpecialIssue together with some selected papers from the FifteenthInternational Symposium on Multiple-Valued Logic.
In the first paper Rich gives us a survey of various tech-niques for storing multiple values in a single memory lo-cation. This is one area where we have seen multiple-valueddevices in commercial use and the paper addresses bothROM's and dynamic RAM's together with the peripheralcircuitry needed to distinguish between the states stored inthe memory cell.Hayes applies multiple-valued logics to the analysis of
binary switching circuits (especially MOS VLSI circuits)under uncertainty, hazards and energy considerations anddevelops the corresponding algebraic theory for both theordered and unordered case. His approach is useful for tim-ing and hazard analysis and provides a rigorous frameworkfor designing gate-level logic simulation programs.
Maruoka studies the asymptotic (Lupanov type) com-
plexity Cm(f) of the minimal representation of an n -vari-able Boolean switching function f by a two-valued circuitwith binary gates which is partitioned so that every pair ofblocks has at most m interconnections. To get lower andupper bounds for Cm(f) each block is treated as a multiple-valued gate.The use of charge coupled devices (CCD's) and their
basic building blocks is addressed by Abd-El Barr, Zaky, and
Vranesic. The authors discuss realization techniques formultivalued multithreshold functions using CCD technology.Two new decomposition techniques are proposed togetherwith synthesis methods. The emphasis of the paper is on4-valued systems.
Heuristic sum of product minimizations of a multiple-valued function are considered by Besslich. The expressionsuse either max or plus (truncated from above) and shift andliteral operators but the search is much more complex than inthe two-valued case. The method uses a direct cover ap-proach to lead to near minimal solutions.
Huntsberger, Rangarajan, and Jayaramamurthy applyZadeh's fuzzy set theory to the computer vision problem-one of the most difficult tasks within the framework of expertsystems- in which a three-dimensional model of a naturalscene must account for uncertainty due to incomplete inputcues; fuzzy sets are also used for color edge distinction andshape representation.Mangin and Current discuss the performance of prototype
CMOS binary to quaternary encoder and quaternary to binarydecoder test circuits that have been realized on a gate arrayIC chip.Yamakawa and Miki consider the circuits that would be
required for the construction of a "fuzzy computer." Theydescribe nine basic fuzzy logic circuits which employ p-chand n-ch current mirrors. They show that any complex fuzzyhardware system using these basic circuits can be realizedwith only one kind of master slice.Hu and Smith propose a new scheme for VLSI scan testing
designs in which binary clocking signals are replaced byternary clocking signals. The great advantage of this ap-proach is that it enables the mode-selecting line to be dis-pensed with leading to a significant saving in chip area andreduced circuit interconnection complexity. However, it re-tains the same high testability as the binary scan method.
Sengupta and Sen introduce a general model of a systemwith three-valued test outcomes and its diagnosability. Nec-essary and sufficient conditions for the diagnosability of sucha system are developed in the correspondence.
Reischer and Simovici survey the iterative properties ofmultiple-valued functions for synthesis by circuit cascades.Their approach is based on transformations of finite sets andinvolves their integration powers and roots.Mukaidono studies the regular three-valued functions
which are suitable for treating ambiguity. These importantfunctions are treated from three different standpoints, de-fined axiomatically and represented by a canonical form.Moraga is concerned with the calculation of the Chresten-
son spectrum for an arbitrary multiple-valued function. Heproposes the use of a systolic system as a dedicated piece ofhardware for the computation and compares the resultingsystem with similar two-valued implementation#.The Guest Editors would like to thank all those persons in-
volved in producing this Special Issue, especially the authors
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9EEE TRANSACTIONS ON COMPUTERS, VOL. C-35, NO. 2, FEIRUARY 1986
and many referees, all of whom worked under incrediblyshort deadlines. We are indebted to J. T. Butler for his assis-tance as Special Project Editor for this issue: His help wasof immense value. Finally we would like to thank Tse-yunFeng, Editor-in-Chief of the TRANsACTIONS ON COMPUTERS.
JON C. Muzio, Guest EditorChairman, Dep. Cormput. Sci.Univ. VictoriaVictoria, B.C., V8W 2Y2 Canada
Ivo C. ROSENBERG, Guest EditorDep. Math. Stat.Univ. MontrealMontreal, P.Q., H3C 3J7 Canada
REFERENCES
[1] G. Epstein, G. Frieder, and D. C. Rine, "The development of multiple-valued logic as related to computer science," Computer, vol. 7,pp. 20-32, 1974.
[2] J. M. Dunn and G. Epstein Eds., Modern Uses of Multiple-ValuedLogic. Dordrecht, Holland: D. Reidel, 1977.
[3] J. A. Ginzer and J. T. Butler, "Multiple-valued logic: 1974-1978 -surveyand analysis," in Proc. 9th Int. Symp. Multiple-Valued Logic, 1979,pp. 1-13.
[4] K. C. Smith, "The prospects for multivalued logic: A technology and ap-plications view," IEEE Trans. Comput., vol. C-30, pp. 619-634, 1981.
[5] D. C. Rine Ed. Computer Science and Multiple-Valued Logic -Theoryand Application, 2nd ed. Amsterdam, The Netherlands: North-Holland,1985.
[6] M. Davio, J. P. Deschamps, and A. Thayse, Discrete and Switching Func-tions. New York: McGraw Hill, 1978.
[7] J. C. Muzio and T. C. Wesselkamper, Multiple-Valued Switching The-ory. Boston, MA: Adam Hilger, 1986.
[8] Z. G. Vranesic and K. C. Smith, "Engineering aspects of multiple-valuedlogic systems," Computer, vol. 7, pp. 31-41,1974.
Jon C. Muzio (M'72) was born in Manchester, England on January 29, 1945. He receivedthe B.Sc. degree in mathematics and the Ph.D. degree in computer science in 1966 and 1970,respectively, from the University of Nottingham, England.From 1969 to 1982 he was with the Department of Cornputer Science, University of
Manitoba, Winnipeg, Canada. Currently, he is Professor and Chairman of the Department ofComputer Science, University of Victoria, Victoria, B.C., Canada. He is a former Vice-Chairman of the IEEE Technical Committee on Multiple-Valued Logic. His research interestsinclude multiple-valued logic, fault detection, fault-tolerant computing, switching theory,and logic design.
Ivo C. Rosenberg was born in Brno, Czechoslovakia on December 13, 1934. He received theM.S. degree from Masaryk University, Brno, and the Ph.D. degree from Purkyne University,Brno, both in mathematics, in 1958 and 1965, respectively.From 1958 to 1971 he was with the Mathematics Departments of the Technical University
of Brno, Brno, Czechoslovakia, the University of Khartoum, the Sudan, and the Universityof Saskatchewan, Sask., Canada. Since 1971, he has been with the Applied Math ResearchCenter of the Universit6 de Montr6al, P.Q., Canada. Currently he is a full Professor at theDepartment of Mathematics and Statistics, Universite de Montreal. In 1977-1978 he was anInvited Professor at Ecole des Hautes Etudes en Sciences Sociales, Paris, France and in 1983an Invited Professor at Universite Claude-Bernard, Lyon I, France. His research interestsinclude multiple-valued logic, universal algebra, theory of relations, partial orders, combina-torics, 0-1 and integer programming, automata, and rigidity problems. He is the author of 86published or accepted papers and 12 preprints, and actively participated at eight InternationalSymposiums on Multiple-Valued Logic.
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