IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 0, NO. 0, SEP 2016 1

Self-powered Time-keeping and Synchronizationusing Fowler-Nordheim Tunneling based

Floating-gate IntegratorsLiang Zhou, Student Member, IEEE and Shantanu Chakrabartty, Senior Member, IEEE

Abstract—Self-powered timers provide a mechanism to achievetemporal synchronization between two passive devices (for e.g.radio-frequency tags, credit/access cards, thumb drives) withoutthe need for any external powering or clocks. As a result thetimers could be used to implement dynamic SecureID typeauthentication involving random keys and tokens that need tobe periodically generated and synchronized. We report a novelsolid-state self-powered timer which exploits a self-compensatingmechanism in the physics of Fowler-Nordheim quantum transportof electrons tunneling onto a floating-gate. The proposed deviceshave been fabricated using standard CMOS processing and aredemonstrated to be operational for durations greater than 3years using extrapolation studies. The fabricated devices were alsofound to be extremely robust to device mismatch and as a resultof which the proposed self-powered timers can be synchronizedwith respect to each other with an accuracy greater than 0.5%.

Keywords—Fowler-Nordheim Tunneling, Zero-power devices,Floating-gate, Self-powering, Time-keeping, Quantum Tunneling.

I. INTRODUCTION

AUTHENTICATION techniques using encryption, stronghash functions and pseudorandom number generators [1],

[2], [3] are necessary for providing secure access to criticaldata and assets. However, for passive assets like credit cardsand passive IoT devices like radio-frequency tags and sensors,the use of these techniques is impractical due to limitedcomputational bandwidth and due to limited availability ofenergy [4], [5]. Also, the lack of access to a continuouslyrunning system clock obviates the use of dynamic authentica-tion techniques like SecureID on these devices, where randomkeys need to be periodically generated and synchronized [6].In this regard, zero-power and self-powered timers that operatewithout any external powering [7] can overcome this limitationand provide a mechanism for dynamic trust verification ofpassive assets. The approach is illustrated in Fig. 1 where self-powered timers integrated on different passive assets (for e.g.

This work was supported in part by research grants from the NationalScience Foundation (CNS:1525476, ECCS:1550096) and by a research con-tract from Semiconductor Research Corporation (Contract: 2015-TS-2640).L. Zhou is with the Department of Computer Science and Engineering andS. Chakrabartty is with the Department of Electrical and Systems Engi-neering, Washington University in St. Louis, St. Louis, MO, 63130 USA.All correspondences regarding this paper should be addressed to Email:shantanu@wustl.edu

Verification Server

Rapid Signature

Verification

Synchronization

“Gold Standard”Timer

Fig. 1. Trust verification based on synchronization between self-poweredtimers on different passive assets like credit cards and passive RFID tags.

credit cards and tags) are synchronized with respect to a “gold-standard” timer located on a remote authentication server.Rapid trust verification can then be achieved by comparingsynchronized tokens (example random numbers in the caseof secureID type approach [6]) that are seeded using theoutputs from the self-powered timers. Because the approachdoes not involve any static identifiers for example bar-codes orproduct IDs, compared to a conventional passive authenticationmethods [4], [8], the proposed dynamic technique should bemore secure and will make the passive assets immune to theft,counterfeiting or tampering.

However the success of this approach relies on three keyattributes of the self-powered timer: (a) the timers need tocontinuously operate over a time-period that matches the life-cycle or the shelf-life of the passive asset (at least for 3 years[9]); (b) different timers can be accurately synchronized withrespect to each other, as illustrated in Fig. 1; and (c) an accuratebehavioral model that can be used for implementing the “gold-standard” timer on the authentication server, also illustratedin Fig. 1. All these attributes require predictability in timeroperation as well as availability of timer parameters that canbe reliably adjusted for calibration and synchronization. In [7],we had proposed a zero-power timer device based on electron-leakage through synthetic oxide-traps. While the device wasshown to be operational for durations greater than 100 hours,000-0-0000-0000-0/00/$00.00 c©2016 IEEE

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 0, NO. 0, SEP 2016 2

FN

Tunneling

EF

*

Drec

ES

C

SiO2 Floating-gate

Thermal

Excitation

Silicon Substrate

Fig. 2. Implementation of self-powered timer using proposed FN tunnelingbased approach.

the dynamics of the electron leakage process was found tobe unpredictable and difficult to control. In this paper, wepropose self-powered timers based on the physics of Fowler-Nordheim (FN) quantum transport of electrons tunneling intoa floating-gate [10]. The physics of FN tunneling, described inSection II, inherently scavenges the thermal activation energyand can be viewed as the self-powering mechanism for theproposed timers. Note that the power levels in thermal-noise(fluctuations) lie well below 10−18-10−16 W which is tooscarce for any conventional energy scavenging circuit to beoperational. In the proposed self-powered timing device, asshown in Fig. 2, the rectification diode is implemented usingthe triangular quantum-mechanical tunneling barrier which iscoupled to a floating-gate. We will show in section III thatcontinuous integration of tunneled electrons onto the floating-gate leads to an ultra-reliable and robust quasi-linear responsethat can be then used for time-keeping and synchronization.The floating-gate also serves as a non-volatile accumulator(counter) whose value can be asynchronously interrogatedusing an externally powered circuit, as shown in Fig. 2 andaccording to previously reported approaches [11]. Section IIIpresents measurement results using timer prototypes fabricatedin a 0.5µm standard CMOS process. The results not onlyvalidate the behavioral model of the timer but also show thatthe timer can be functional for durations greater than 3 years.Also, we present measurement results that demonstrate syn-chronization accuracy up to 0.5%. Section IV and Section Vconclude the paper with a brief discussion about the effectof ambient temperature variations on the timer response andpossible mechanisms for compensation.

II. FN TUNNELING BASED SELF-POWERED TIMERS

The structure of a generic FN timer comprises of a strip ofpoly-crystalline silicon (polysilicon) that is completely insu-lated by high-quality, thermally-grown silicon-di-oxide. Thispolysilicon strip, also referred to as a floating-gate, serves as a

reservoir of electrons and the surrounding oxide will serve asan energy barrier (shown in Fig. 2) that prevents the electronsto leak out by means of thermiomic emission. Electrons,however, can tunnel through the oxide using three mechanisms:(a) Trap-assisted tunneling (TAT) where carriers tunnel throughthe oxide layer with the assistance of trap states [12], (b)direct tunneling (DT) where carriers directly tunnel throughthe rectangular barrier formed by the oxide layer [13], and(c) Fowler-Nordheim tunneling (FNT) where carriers tunnelthrough a triangular-shaped barrier which results from thepresence of a strong electric field across the barrier [14]. Trap-assisted tunneling depends on the number and distribution oftraps and is difficult to control and modulate externally. It isalso negligible in CMOS floating-gate structures because theoxide is thermally-grown, thus, the interface between the poly-crystalline silicon and silicon-di-oxide has very few defects orelectron traps. Direct tunneling relies on the thickness of theoxide layer and only becomes prominant when the thicknessof the dielectric layer is small (for silicon-di-oxide, less than5 nm). Oxide thickness is a process specific parameter andcannot be modulated or controlled. However, in literature directtunneling current has been exploited to implement large time-constant and ultra-low-power watch-dog timers [15].

FN tunneling, on the other hand, depends on the shape of theenergy barrier across the dielectric (oxide) layer which can becontrolled and modulated by changing the electric field appliedacross the dielectric layer. The physics of FN tunneling, asillustrated in Fig. 2 is a two step process. Electrons are firstthermally excited to an energy level E which then tunnelthrough the triangular barrier into the floating-gate. Note thatat the bottom of the energy barrier, the oxide thickness is largeenough (greater than 10nm in a 0.5µm CMOS process) that theprobability of electrons directly tunneling through is negligible.Thus, FN tunneling can be modeled by an equivalent energyscavenging circuit shown in Fig. 2 where the input energysource is the ambient thermal-activation or thermal-noise andrectification diode is formed by the tunneling barrier whoseoutput is the floating-gate capacitance. Mathematically thecombination of thermal activation and electron tunneling canbe expressed by the FN tunneling current density J (A/m2)as [16]:

J =q

hγ

∫ ∞−∞

PT (ζ)T (ζ)dζ (1)

where PT (ζ) is the probability density function correspondingto an electron occupying an energy level ζ and T (.) representsthe tunneling probability of the electron and is a function ofthe barrier thickness. The parameters h and q correspond tothe Plank’s constant and charge of free electrons respectively.γ represents a transmission parameter that is a function of theinterface properties. In its general form shown in equation 1,it is practically impossible to obtain a closed form expressionfor FN tunneling current density J , let alone solve a coupleddifferential equation involving J . Therefore, for the sake ofsimplicity we will ignore several second order effects (for e.g.effect of image force and temperature variations) and consider

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 0, NO. 0, SEP 2016 3

the following mathematically tractable form of J

J = αE2 exp(− β

E) (2)

where E represents the electric field across the oxide-barrierand where the parameters α and β are a function of the materialproperties and are given by

α =mq3

8πm∗hφ(3)

β =4(2m∗)

12φ

32

3hq(4)

m∗ being the effective mass of electrons in the forbidden gapof the silicon-di-oxide, m being the mass of a free electron, φthe barrier height at the interface, and h the Planck’s constant.

J(Vfg) CT

Vfg

Time

Transient EquilibriumV0

Vfg

t0（a） （b）

Fig. 3. Model of the self-powered timer device: (a) equivalent circuit ofthe timer, and (b) temporal response illustrating the transient and equilibriumregions.

The core structure of the timer can be modeled as aparallel connection of the tunneling current source and thegate capacitance, as illustrated in Fig. 3(a). If the floating-gatecapacitance is assumed to be CT and the cross-sectional area ofthe tunneling junction is assumed to be A, then the incrementalchange in floating-gate voltage Vfg(t) (equivalently floating-gate charge) can be expressed by the first order differentialequation

dVfg(t) =dQ

CT=AJ(E)dt

CT. (5)

Under the assumption of a triangular barrier, Vfg and E arerelated by the oxide-barrier thickness tox as

Vfg(t) = toxE(t) + Vsub (6)

where Vsub is the effective voltage drop across the n-typesubstrate. By integrating equations 2, 5 and 6, the dependenceof electric field E on time t can be expressed in the form of

E(t) =β

ln(k1t+ k0)(7)

where k0 and k1 are constants that are given by

k0 = exp(β

E0), k1 =

Aαβ

CT tox(8)

here E0 is the initial electric field across the gate oxide.Substituting E into equation 6, the floating-gate voltage changeover time can be expressed as

Vfg(t) =k2

ln(k1t+ k0)+ Vsub (9)

wherek2 = βtox (10)

Fig 3(b) illustrates a typical response of the timer accordingto the equation 9. While the initial timer response is a functionof the parameters k0, k1 and k2, for the time intervals t �t0 � k0/k1 the response becomes

Vfg(t) =k2

ln( tt0)+ Vsub. (11)

This regime labeled as the equilibrium region in Fig. 3(b)tracks equation 11 and reveals two important attributes whichare useful for designing robust long-term timers. First, thefloating-gate voltage monotonically decreases and is inverselyproportional to a logarithmic function of time. Thus the rateof decrease is slower than a linear timer and faster than alogarithmic time integrator [7], [17]. This implies that thetimer could be functional for a long-term duration relevantto the proposed application. The second attribute shown inequation 11 is that the response is only a function of the pa-rameter k2 which depends only on the material properties andthe oxide-thickness, as described by equations 10 and 4. Thus,asymptotically, the response of the timer becomes theoreticallyindependent of device sizes (cross-sectional area and floating-gate capacitance). Thus, timers based on equation 9 shouldbe robust to device mismatch and can be used to achievesynchronization between different devices.

III. DEVICE IMPLEMENTATION AND MEASUREMENTRESULTS

The micro-photograph of the timer device fabricated usingstandard CMOS processing techniques is shown in Fig. 4(a).The floating-gate is formed by the gate of a pMOS transistorwhich is also used for programming the initial charge onto thefloating-gate [18]. Note that the initial charge on the floating-gate controls the initial electric-field in the oxide barrier andhence the shape of the FN tunneling barrier. Timers withdifferent form factors (floating-gate capacitances and tunnelingjunction area) were also fabricated and the micro-photographsof eight timer structures are shown in Fig. 4(b). Timers labeledas Timer-C1 to Timer-C4 are devices with the same tunnelingjunction area but with different floating-gate capacitances.Timers labeled as Timer-A1 to Timer-A4 are timers with thesame floating-gate capacitance but with different tunnelingjunction areas. The initial charge (hence the shape of theoxide barrier) on floating-gates were programmed using acombination of Fowler-Nordheim (FN) tunneling and hot-electron injection. A relatively high-voltage ( 15 V in 0.5µmCMOS process) is applied across the parasitic nMOS capacitorCtun (as shown in Fig. 4(a)), which removes the electrons fromthe floating-gate. Hot-electron injection, on the other hand,

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800 mm6

00

mm

Timer-C1 Timer-C2 Timer-C3 Timer-C4

Timer-A1 Timer-A2 Timer-A3 Timer-A4

Tunneling Junction

Floating-gate

Transistor

Re

ad

-ou

t B

uff

er

Vfg

Vcg

Vs

Vd

Vtun

Vo

(a)

(b)

M

20mm

Fig. 4. Micro-photographs of the fabricated devices: (a) a single timer; and(b) timers with different floating-gate capacitances and tunneling area.

requires lower voltage ( 4.2 V in 0.5µm CMOS process) thantunneling and was used for precise programming of floating-gates. Details of precision floating-gate programming can befound in [17] and is ommitted here for the sake of brevity.After the initial programming of the timer, all the calibrationterminals are connected to ground and the timer is operatedin a self-powered mode without any external powering. Thetimer value or the floating-gate voltage periodically read outthrough the buffer shown in Fig. 4(a).

A. FN Timer Measurement Results

TABLE I. MODEL TIMER PARAMETERS ESTIMATED USING MEASUREDDATA

Parameter Valuek2 87.49k0 2.341×108

k1 1.037×104

Vsub 3.94

The first group of experiments were designed to verify thetimer behavior model as given by Equation 9. Measurementresults from Timer-A1 were used for estimating the modelparameters. The results are shown in Fig. 5, where also show

Measured

Model

Fig. 5. Measured timer response and comparison with the behavioral model.

Measured

Extrapolated

Fig. 6. Extrapolation study showing long-term response of a timer with gatecapacitance of CT = 16 pF and tunneling junction area of A= 54 µm2.

the error between the measured data and the behavioral model.The model parameters are summarized in Table. I and themodel error is measured to be smaller than 6mV over a rangeof 700mV, implying a model accuracy greater than 40dB. Oneof the benefits of using a reliable behavioral model is thatit can be used for extrapolation studies for predicting thetimer’s long-term response, which could be impractical forrepeated experimental studies. Fig. 6 shows the result of theextrapolation study where the behavioral model is plotted for aduration greater than 3 years. Also, data points measured fromthe fabricated timer is overlayed on the behavioral responseand is shown to exhibit an accurate fit up to 2 × 106 secondsor 550 hours.

B. Robustness and Mismatch CharacterizationThe next set of experiments were designed to verify the

timer responses and the corresponding behavioral model fordifferent values of: (a) floating-gate capacitances; and (b)tunneling junction areas. Fig. 7 shows the measured values(highlighted by marked points) for floating-gate capacitancesof 2 pF, 4 pF, 8 pF and 16 pF respectively. For this experiment,

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CT=16 pF

CT=8 pF

CT=4 pF

CT=2 pF

(a)

(b)

Fig. 7. Comparison of timers for different gate capacitances CT withtunneling area A=54 µm2. (Marked points represent measured data and solidlines correspond to the behavior model.)

the tunneling junction areas for all the four timers were chosento be 54 µm2. The corresponding timer responses estimatedusing the behavioral model for each of the parameters (FGgate capacitance and tunneling junction area) is also plottedas a solid-line overlaying the measured data in Fig. 7(a).Two observations can be inferred from the measured results:(a) the behavioral model can accurately predict the responseof the fabricated timers for different device parameters; and(b) a smaller capacitance produces a faster change in thetimer response. A more interesting result and verification ofequation 11 is that after the initial differences in respectivetimer responses, all the timers change in a near identicalfashion. This is shown in Fig. 7(b) which plots the change inthe timer outputs measured with respect to the output measuredat a reference time (to = 6 × 105 s or 167 hours). Theresult show that the response changes by less than 2% evenif the capacitances changes by more than 800%. A similarexperiment was conducted for timers with different tunnelingjunction areas of 72 µm2, 108 µm2, 144 µm2 and 180 µm2

and for a fixed gate capacitance of CT =4 pF. The measuredresult is shown in Fig. 8 demonstrating a similar trend asbefore where a smaller junction area produces a larger initialchange in the timer responses; but after a reference time, allthe timers exhibit a near identical response. This is verifiedin Fig. 8 which shows the change in timer values (fromthe value measured at a reference time instant) for differenttunneling junction areas. The measured results again validate

A=72 mm2

A=108 mm2

A=144 mm2

A=180 mm2

(a)

(b)

Fig. 8. Comparison of timers for different tunneling junction areas with CT =4 pF. (Marked points represent measured data and solid lines correspond tothe behavior model.)

the robustness of the timing device exhibiting less than 3%variation for junction areas that can vary by more than 100%.

In the next set of experiments we verified the mismatchin the responses of identical timers fabricated on differentsilicon dies. For this experiment all the timers were simultane-ously programmed to “approximately” the same initial voltageand the set up was housed in an environment with similarconditions (temperature and humidity). Fig. 9(a) shows themeasured timer responses which as expected shows a similartrend, where the initial timer responses vary due to mismatch,but then the responses reach an identical steady state response.Fig. 9(b) show the relative deviation in the timer value withrespect to each other and the measured result exhibits less than500µV variation over a 100mV operating span. This amountsto a synchronization accuracy greater than 46dB. Note thatfor this experiment, the noise and drift in the read-out circuitscould also affect the measured result; therefore it is possiblethat the synchronization accuracy could be higher than whathas been measured. However, optimization of the read-outcircuits was not the goal of this paper.

IV. DISCUSSIONS

The objective of this paper was to demonstrate the function-ality of a proof-of-concept self-powered timing device basedon FN tunneling of electrons onto a floating-gate. When biasedin a saturation regime, the timers can exhibit an extremelyrobust time-keeping response that is dependent only on the

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 0, NO. 0, SEP 2016 6

(a)

(b)

Die 1

Die 2

Die 3

Fig. 9. Comparison of the measurement results from timers with the samestructure on different dies with gate capacitance of CT = 8 pF and tunnelingjunction area of A= 54 µm2.

device physics parameters and oxide thickness. However, inour modeling and analysis of the timer we ignored the effectof temperature and other second order effects.Although theprocess of tunneling through the triangular barrier exhibits aweak dependence with respect to temperature, the number ofthermally excited electrons is a function of temperature. Also,the height of the barrier also depends on temperature.

A group of experiments were conducted to measure thetemperature dependence of the timer. A fabricated timer withCT =2 pF and A=54 µm2 was housed in a temperaturecontrolled environment chamber and timer responses wereobtained for four different temperature settings: 10 ◦C, 20 ◦C,30 ◦C and 40 ◦C. The measured responses are shown in Fig. 10and as expected the initial timer responses show a faster ratewith increase in temperature. This is because for FN tunneling,electrons have to be thermally excited to cross the triangularFN barrier. However, the long-term response of the timerexhibits a self-compensating effect similar to that of the timerswith different device parameters. Fig. 10 shows the measuredchange in timer responses after a reference time of 6×105s,the FG voltage reduction shows a mismatch less than 0.4 mVacross a range of 100 mV. The measured results demonstratethat two timers maintained at two different temperature levels(measured range of 30oC) can still be synchronized withrespect to each other up to an accuracy of 0.5%.

Another important aspect of the proposed FN timer is that itcan be implemented on other CMOS processes as well. Even

T=10 ˚C

T=20 ˚C

T=30 ˚C

T=40 ˚C

(a)

(b)

Fig. 10. Measured dependence of timer’s characteristics on temperature withCT =2 pF and A=54 µm2.

though we have used a 0.5 µm process (with an approximate13 nm gate oxide thickness) to validate the response of theFN timer, the physics of the timer (summarized by equation9) should still be valid as long as the oxide thickness is greaterthan 10nm. Advanced CMOS processes usually provide thickoxide option for I/O modules, which could therefore be usedfor designing the proposed FN timers. The self-compensatingeffect should still be applicable as long as the floating-gatestructure can be reliably fabricated.

V. CONCLUSIONS

In this paper we have presented a self-powered timer basedon FN tunneling of electrons onto a floating-gate. The timercan be accurately described using a simple behavioral modelthat incorporates different non-ideal effects (image force) andthe effect of temperature dependence. The accuracy of thebehavioral model has been verified using measured results thatwere obtained from fabricated timer structures prototyped us-ing standard CMOS processing. Measurement results demon-strate that the long-term response of the timer is very robustto device mismatch and hence can be used for synchronizingtime on two passive devices which do not have access toa continuously running clock. We believe that this attributewould be essential for generating synchronous authenticationtokens that can be used for rapid trust verification similar to asecureID type procedure [6].

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Liang Zhou (SM’14)received the B.S. degree inphysics from Tsinghua University, Beijing, Chinain 2010. Currently, he is working toward the Ph.D.degree in the Department of Computer Science andEngineering, Washington University, St. Louis, MO,USA. His research interests include low-power sens-ing systems, integrated biomedical sensors, analogand mixed-signal circuits, and RF circuits.

Shantanu Chakrabartty (SM’99-M’04-S’09) re-ceived his B.Tech degree from Indian Institute ofTechnology, Delhi in 1996, M.S and Ph.D in Elec-trical Engineering from Johns Hopkins University,Baltimore, MD in 2002 and 2004 respectively. Heis currently a professor in the School of AppliedSciences and Engineering at Washington Universityin St. Louis. From 2004-2015, he was an asso-ciate professor in the department of electrical andcomputer engineering at Michigan State University(MSU). From 1996-1999 he was with Qualcomm

Incorporated, San Diego and during 2002 he was a visiting researcher atThe University of Tokyo. Dr. Chakrabartty’s work covers different aspects ofanalog computing, in particular non-volatile circuits, and his current researchinterests include energy harvesting sensors and neuromorphic and hybridcircuits and systems. Dr. Chakrabartty was a Catalyst foundation fellow from1999-2004 and is a recipient of National Science Foundation’s CAREERaward, University Teacher-Scholar Award from MSU and the 2012 Technologyof the Year Award from MSU Technologies. Dr. Chakrabartty is a seniormember of the IEEE and is currently serving as the associate editor for IEEETransactions of Biomedical Circuits and Systems, associate editor for theAdvances in Artificial Neural Systems journal and a review editor for Frontiersof Neuromorphic Engineering journal.