The design of high-speed real time multi-channel sonar simulation signal source based on FPGA

Parallel Technology

xiaoyan Huang1, xi’an Feng, tiande Gao

College of marine Northwestern Polytechnical University, NWPU

Xi’an ，China E-mail:xyhuang1212@yhaoo.com.cn

Abstract—The mainly task of sonar simulation signal source is to generate real time dynamic echo signal using the underwater acoustic signal properties, the relative motion properties and the underwater environment noise. Sonar simulation signal source is applied in a semi-physical simulation system. So real time ability and high-speed transmission is the main factors in the system design. This paper using the embedded soft real time processor combining high speed hard real time module to generate 128 channel simulation signals based on FPGA parallel technology. Single frequency pulse signal (CW), line frequency modulation pulse signal (LFM), hyperbolic frequency modulation pulse signal (HFM) ,this three type of pulses signals have dynamic generated through above technology in the system. The system test results show that the average compute time of FPGA module is consumed 9.13867ms when working at 192 KHz, the highest system sampling rate to generate 128 channel signals .meanwhile, less than 2.5K system flash memory space is needed to ensure continuous simulation signal output. Experimental results show that System has high real time ability and reliability.

Key words-FPGA Parallel Technolog; multi-channel; sonar simulated signal source; real time echo simulation

I. INTRODUCTION With the development of antisubmarine and Ocean

exploitation, various kind type of sonar has been widely applied in military and economic department. When meet the target, the sonar transmitted acoustic wave will be reflected. Through the time delay difference between transmitted acoustic wave and received acoustic wave and the direction of transmitted acoustic wave the target rang and direction will be computed. Sonar receiver, sonar and target composed a semi-physical simulation close loop system. In such a semi physical system, when the target parameter changed, sonar simulation signal source must quickly compute and generate echo simulation signal especially when the target parameter is dynamited and undetermined. So, high real time ability is needed to satisfy the system demand.

According the system demand, a multi-channel high-speed real time sonar simulated signal source has been designed. The task of simulated signal source is generate echo simulation signal, generate target and background signal, finish array

element time delay superposition and signal synchronous . System is composed of real time operation system, embedded computer, programmable FPGA module, multi-channel output module, and sonar simulated signal source software. Using the programmable logic element and matching developing software to improve the real time ability and data compute ability.

The remainder of the paper is arranged as follows. Section 2 introduces three type of echo simulation signal module. In Section 3, system design is introduced in detail. Section 4 introduces the key technology of system. In Section 5, system real time test result is presented. Finally, in Section 6, the performance results are summarized and significant conclusions are presented.

II. ECHO SIMULATION SIGNAL MODULE

A. Single frequency pulse signal (CW) As the sonar transmitted signal, the simulation echo signal

form of CW is

)()2cos()( 0 tntfAts iii ++= ϕπ (1)

Where A is the amplitude, 0f is the frequency, iϕ is the array element time delay, )(tni is statistical independence

Gauss noise sequence, T is the signal pulse width.

B. Line frequency modulation pulse signal (LFM) As the sonar transmitted signal, the simulation echo signal

form of LFM is

)()212cos()( 2

0 tnBttfAts iiii +++= ϕπ (2)

978-1-4244-5668-0/09/$25.00 © 2009 IEEE

Where T

ffB LH−= ， Hf is high limit frequency， Lf is

the low limit frequency, T is the signal pulse width, other

parameter is defined as formula (1).

C. Hyperbolic frequency modulation pulse signal (HFM) As the sonar transmitted signal, the simulation echo signal

form of HFM is

)(])(2cos[)( tntAts iii ++= ϕπθ (3)

)1ln()(0t

tKt i

i −=ϑ , B

ffTK LH ⋅⋅

=B

Tft H ⋅

=0

Where LH ffB −= ；2Tti ≤ , T is the signal pulse

width, Hf is the high limit frequency ， Lf is low limit frequency, other parameter is defined as form (1).

III. SYSTEM DESIGN

A. system compodition The task of simulated signal source is to generate echo

simulation signal, target and background signal, to finishing the array time delay superposition and signal synchronous.To satisfied this demand, in one hand, high speed process unit and communication interface, multi-channel target data module generating function is need. In the other hand, system need to Configure many high speed D/A channels for digital and analog convert. In the last hand, the real time data process ability is necessary to satisfy the system real time process demand.

According to the function and Properties of the sonar simulated signal source, the system principle is shown in figure 1.

Fig. 1 the compose of sonar simulated signal source system

First, through the Ethernet, the ATE output the system working mode, target parameter and background parameter to real time processor, after computing and loading, the parameter, the simulation echo signal will transmitted by PCI Bus to programmable FPGA, the target signal and background noise array element time delay data will be recomposed to output. The output data will be transmitted to DAC directly. The data stream of active mode is shown in figure2.

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ting s

ignal

Fig 2 .the system data stream of active mode

B. System programmable FPGA module In active mode, when trigger signal received, the

programmable FPGA module dynamic compute and generate 128 channel digital signal and receiving array parameter from real time embedded processor. PCI-7813R Programming module is selected for the system.

PCI-7813R is an onboard FPGA chip, programmable with the LabVIEW FPGA module. User-defined triggering, timing, and decision making in hardware with 25 ns resolution and up to 8 analog inputs, independent sampling rates up to 750 kHz, up to 8 analog outputs, independent update rates up to 1 MHz, 16-bit resolution, up to 160 digital lines configurable as inputs, outputs, counters, or custom logic at rates up to 40 MHz ,direct memory access (DMA) channels for high-speed data streaming ,implement custom control logic, inline signal processing and digital communication protocols is convenient for the system demand.

In this system the key features using PCI-7813R of is as follows:

Through programming in LabVIEW FPGA, each of the I/O signal lines can be controlled independently and using a line can easy to synchronize with other channel. The digital I/O lines can be configured as custom counter/timers, PWM channels, or communication buses for user-defined protocols. PCI-7813R has dedicated analog-to-digital converters/digital-to-analog converters on every analog I/O channel. This offers specialized functionality such as multi rate sampling and individual channel triggering, which are beyond the capabilities of typical data acquisition hardware. The compiled LabVIEW FPGA application can also be stored in the onboard flash memory and configured it for automatic loading and/or execution at power up.

C. System multi channel DAC module Multi-channel DAC module is used to communication

with programming FPGA and recombining the digital data then generate simulation signal. The interface of the DAC is using high speed I/O to connect with FPGA. The output sonar

simulation signal can be output by 8 DB62 Connector. Structured design method used in the system and 128 simulation channels are configured to output signal. The system has 8 D/A circuit boards, each has 16 channels. Each channel of the circuit boards has 8 times interpolation function and the highest output sampling rate reach to 87kHz when 192 kHz input sampling rate used. The composition of multi-channel DAC is shown in figure 3.

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Fig3 the composition of multi-channel DAC

Using double stereo channels, the DAC chip has digital trigger function and has 24 bit resolution, 113DB dynamic range. The sampling rate is up to 10-200 kHz, 8 times interpolation function and digital filter inside. In this condition, the input data rate don’t need to great than fh/0.45. Actually, 11-bit used to generate signal, other 13-bit used amplitude control.

IV. KEY TECHNOLOGY

A. high speed data stream generate System has output signal 128 channel, the sampling rate

is up to 192 kHz for each channel. Huge amounts of data exchange frequently between CPU and inside memory after compute. Up to 400Mb/s total data communication is beyond burden for traditional PCI bus. Traditional processor structure is hard to satisfy such high signal bandwidth between CPU and inside memory.

In this system, system structure is divided into two parts: soft real time processor and high speed programming FPGA module .The soft real time processor is used to generate parameter of target, background, array element time delay. High speed programming FPGA module is ensuring definite time to generate many kinds of signals before loading to DAC. Single cycle time loop (SCTL) and fix point math IP core are used to ensure the real time ability in FPGA. The detail is introduced as follows:

The single-cycle Timed Loop (SCTL) is a special use of the LabVIEW Timed Loop structure. When used with an FPGA target this loop executes all functions inside within one tick of the FPGA clock which has been selected. The default selection is the 40 MHz FPGA global clock. SCTL with derived clocks can also be used to clock the loop at a rate other than 40 MHz. The traditional While Loop in FPGA VI takes an absolute minimum of 3 ticks to execute each iteration operation. This is because of the enable chain used in the compiled FPGA VI. An explanation of the enable chain is beyond the scope of this document, but is used to ensure dataflow when the FPGA VI is compiled into a bit file. Additionally, each function inside the traditional While Loop will require at least one tick to execute. With the SCTL, all

functions will execute in parallel if there is no data dependency. All functions inside the loop must execute within a single tick. Instead of doing an add operation, saving the result, and then a multiply and saving the result, the SCTL does both in one tick and does not have to save the result in between. This conserves FPGA resources because no flip flop is needed between operations to save the result of each previous operation.

The Fixed-Point math IP core contains LabVIEW FPGA IP blocks that implement a variety of elementary and transcendental math functions. These functions use the Fixed-point data type include Divide, Sine, Cosine, and many more important math operations. All functions are verified for usage inside and outside a Single-Cycle Timed Loop. The compute resolution can be improved using FXP Math. Some corner cases or input parameters, outputs from the Fixed-Point Math can be undefined or unexpected. In some cases, these decisions were made to streamline the IP to use less resource.

B. The phase coincidence of multi channel In this system, using the 24 bit hardware circuit DAC to

ensure the coincidence of phase. The DAC working sequence is shown in figure 4.

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...…...

Fig4 .The multi channel DAC working sequence System clock is 24.576MHz, the bit clock PBCK is

generated by 0.5 Frequency dividing of system clock, the channel select clock PLRCK is generated by 64 Frequency dividing of system clock, then each channel data is be separated to high 12 bit and low 12 bit, each bit clock send one bit data, high bit first. Every DAC working clock except system clock is generated by system clock. The advantage of this design is to avoid clock jitter and ensuring the phase coincidence strictly according to DAC working sequence.

V. SYSTEM REAL TIME ABILITY TEST RESULT Real time ability is the key factor to influence the sonar

simulation signal source system capability. The system real time ability can be reflected by computing the signal generating time in FGPA.

In active working mode, when the synchronous pulse signal arrival, the simulation signal output after time delay. Pulse trigger signal is show in figure 5.

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Fig5. Pulse trigger signal schematic diagram

In our case, through 256 times sampling, system real time compute timing curve is show in figure 6.

Fig6. real time compute time curve of FPGA signal

Figure 6 shows that the average FPGA compute time is 9.13867ms.the maximum time is 11.5 ms. when the multi channel DAC sampling rate at 192 KHz, the output number per second is 11.5ms*192KHz=2208, need less than 2.5K memory space. System real time ability can be easily satisfied in such high sampling rate.

VI. CONCLUSION In order to satisfy the system real time ability demand

when apply in semi physical simulation system, parallel FPGA technology is used to generate the simulation signal. Meanwhile, the embedded soft real time processor combining high speed hard real time module methods is also be used to generate 128 channel simulation signal. system test result show that when the multi channel DAC sampling rate at 192 KHz, the highest output number per second is 2208, just need less than 2.5K memory space. The average FPGA compute time is 9.13867ms.System real time can be easily satisfied in such high sampling rate.

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