A ‘VirtuaT Waferscale’ Multichip Module System

R.G.C. Artus

The University of Reading J. J. Thomson Laboratory

Whit eknights Reading Berkshire

Abstract A new concept in Multichip Modules is presented that represents a potential ‘next step’ in packaging for solid state electronic systems. A unique heat sink material, in the form of a compacted particulate paste provides a firm three dimensional support to die without adhesion to the die. The material also provides a direct thermal shunt between a die and it’s casing. The resulting low thermal resistance Oj,

allows an array of die to be placed into a single module where the die spacing can be such that direct die to die interconnects are possible. A dense array of die with direct die to die interconnects will behave electronically as if it were a single die. A ‘virtual waferscale’ 128Mb SRAM memory block, fabricated as a 32 die array, is considered.

Introduction The new concept in MCM design allows an array of die to be held in place without a die to substrate bond and which also provides thermal management for the array. The efficiency of the thermal management is such that the die can be held very close together so as to enable direct die to die interconnects. As there is no bonding of the die, any die in this array may be changed without disturbing the rest of the array. Thus we show the possibility of a practical realisation to waferscale design in a ‘virtual waferscale’ packaging scheme.

There are two ‘key’ parameters to MCM package design and fabrication, they are :-

(i) thermal management (ii) ability to replace defective die

Thermal Management Effective thermal management of die is the hndamental requirement of any packaging scheme.

As all the heat is generated in the working face of a die, the most efficient route for heat removal is to provide a thermal shunt directly from that surface to the casing. A new material is available to provide that thermal shunt.

The new heat sink material is in the form of a particulate paste; it has a consistency that is similar to “ almost dry ” clay. The material is composed of sub-micron diamond particles dispersed in a paraffin at very high packing fractions and shows the interesting thermal property of having an increase in thermal conductance with increasing temperature‘ ’. Heat is removed from all faces of the die, however, the prime route is the direct thermal shunt between the working face of the die and the casing. The effectiveness of this direct route results in a very low e,, . The temperature of the enclosed die will then be governed by the overall thermal resistance e,, of the casing and it’s total heat load.

Die Replacement If a large array of die is to be assembled, it is essential for there to be a means of replacing defective die. In this packaging scheme the die are not bonded to a substrate. The heat sink composite does not set or have any adhesive properties and because of it’s particulate nature, it does not flow. Consequently die suitably encased in the material cannot move, however, the material can be readily removed to allow rework. The absence of die attach means that die are only bonded into the array via die leads. Therefore any die in an array can be changed without thermal shock or stress to it’s nearest neighbours.

The ease of die replacement in this scheme means that the final module yield will be very close to

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100% regardless of the size of the array. In addition it can be fabricated to allow for repair or subsequent die upgrade.

The new 'Virtual Wafer' Module The following module description is for a straight forward configuration, that is, for a set of die designed specifically for direct die to die interconnects. In addition to the die set, the module is composed of three elements, the die lattice, the heat sink material and the casing.

Die Lattice '-\

-- Lattice bond area

An array of die is held in an X,Y plane by a 'die lattice'. The lattice has the same thickness as the die and the holes of the lattice are the same dimensions as the die. Thus die inserted into the holes would be flush with the surface of the lattice. The width of this lattice work defines the die to die spacing and, in this simplest lattice structure, the lattice would need only to have surface bond areas between the die. Die to die interconnects are made via the lattice surface using wire bond or TAB leads. The completed array is then subjected to a test programme; any defective die may be replaced without disturbance to the rest of the array. The rework capability of any site would be governed by the rework capability of the lattice bond areas.

The working array is now coated with the heat sink material ( the order of 0.5- thick ) and placed into the casing. This module assembly is then sealed off such that no voids remain inside the casing.

Thermal Design Considerations The following example relates to the thermal management of a 128 Mb memory block composed of 32 die confrgured for direct die to die interconnects and held in the module structure described.

Consider an 8x4 array of die :- Let these 32 die be 4Mb SRAM die having an 'active state' power dissipation requirement of 1W / die. The dimensions of each die is taken to be 8x5 mm (40.106 m').

Paste 100% fill \ Finned Caseing

~

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Let the thermal conductivity h of the heat sink material be 5 W/mK and have a layer d, of 0.5- ( 5.lO"'m), between the surface of the die and the casing

The calculated thermal resistance Ojc is given by :-

0 j c = d I h.A

where A = surface area of the die; in this example, using the front surface of the die only :--

Ojc = 2.5 OC/W

If some allowance is made for the removal of heat from the back face of the die, each die will have an operating temperature of approximately 2 OC above the casing temperature.

With a finned casing we could expect a maximum thermal resistance 0, of 1 OC/W. With all 32 die in

the ‘ON’ state we must dissipate 32W and the casing temperature will be 32 OC, the working temperature of the die will then be 34 OC (max.) above ambient. In practice, not all of the die in such a large memory needs to be in the active state and it would be reasonable to consider 32 Mb active at any one time, thereby reducing the working heat load to 8W. At this power level the casing temperature will be 8 OC giving an active die temperature of 10 OC above ambient.

ermal behaviour of the material This material has a unique thermal behaviour in that it shows a positive coefficient of thermal conductance with increasing temperature, that is, the thermal conductance increases with increasing temperature. Such a thermal response has particular relevance to the thermal stress problems generated by possible ‘hot spots’ in the die design.

The heat sink material can be produced with different levels of thermal conductivity. It is considered possible that the thermal conductivity of this new type of material could exceed that of metals, that is to say, in excess of 200W/mK. Well before that level, at say 50 W/mK, consideration could be given to 3D structures.

Other Design Considerations The very low operating temperature of die in this new packaging scheme, has significant implications regarding the reliability of modules in general and the operating speed of CMOS die in particular.

The module above relates to an optimum performance design and uses essentially an ASIC die set. This new type of module has particular relevance for the design of complex high performance ASIC systems, fabricated as a VLSIC. For the ASIC designer, any system can be partitioned into a die subset where simpler and perhaps more robust die have a very much higher yield than a single VLSIC. Thus there is the possibility of fabricating a design economically as a module, rather than a VLSIC, since the ease of die replacement takes the module yield very close to 100%. It follows that it is also possible to consider

a die set that would have the performance of a single die when assembled in the module, but which would be impossible to fabricate as a single die. That is to say, that the array would function as a ‘virtual’ wafer.

Any ‘standard’ die / PCB design scheme can be implemented within the new module. In this case, the die lattice structure is more complex and acts as a PCB. Such a configuration would have a substantial improvement in performance due to the improved thermal management and the shorter path lengths between die.

Die size change is a significant problem in any MCM assembly that uses die normally fabricated for the general market. This problem is overcome by designing the lattice structure to accept a ring adapter between the die and lattice. The cost of die size change is then limited to the replacement cost of an adapter.

High power systems In this packaging scheme heat will be removed from all faces of the die. In the normal die form, that is a thin plate geometry, it follows that if heat is removed equally from the front and back of the die, the power density is effectively halved. High power density capability is most significant in the thermal management of smart power devises. Because of the effective thermal control / management there would be advantages for very smart power systems to be fabricated as a module instead of a smart power die. It is usually the case, from a design point of view, that the sensor input and logic processing will be most efficiently implemented in one die type and the high power segment in another.

Very fast systems In this new type of assembly, vertical channel surface emitting lasers VCSEL’s (currently in production by Motorola) can easily be included within the design. This would provide direct optical links between modules. This practical and real possibility of direct and multiple, optical highways between modules, has dramatic implications for electronic systems design generally. For desk top

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computer systems in particular, a 64 channel, direct optical highway between a ‘Pentium Class’ CPU, and a 32Mbyte SRAM module would be highly desirable. This development would provide two or three orders of magnitude increase in effective speed; optically linking this system to a Video U0 module would generate a new class of computers.

The ability to enclose a dense array of fast switching die within a metal structure has significant implications for the control of EMI.

Acknowledgement I would like to thank Dr. I. Kiflawi for his helpkl discussions and to K.M.A. for her patience and unfailing support during this work.

References [l] R.G.C. Artus, ‘Measurements of the Novel Thermal Conduction of a Porphritic Heat Sink Paste’ EEE Trans. Advanced Packaging B. Vol. 19No3 1996

Availability and Cost of the raw materials:- The sub-micron diamond required is currently a ‘waste product’ of the industrial diamond manufacturing process. It is available at a rate of over 100 Tonlpa. fiom a world wide distribution of production plants. The cost of the heat sink material will vary with the required level of conductivity, however, the estimated cost, at about SW/mK level is $40 k 20 / gm.

Conclusion This new approach to the packaging of multiple die has considerable benefits over other types of MCM systems. It accommodates the highest possible density of die with excellent thermal management. The relative ease of die replacement affects most notably the economics of MCM production and removes the previous yield constraint on the number of die in a module. As die can be assembled very close together, a total silicon solution to a system is possible as a ‘virtual waferscale’ module. There is flexibility with this packaging approach in that existing die / PCB designs, as opposed to ASIC die systems, can also be implemented.

The ‘virtual wafer’ approach has the potential to enhance the development of electronic systems in much the same way as the previous transition from individual transistors to IC’s. The ‘virtual waferscale’ module can provide a similar improvement, in speed, reliability and performance, to board level designs.

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