IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. ??, NO. ??, MAY 2020 1

A Fully Passive RF Front-end with 13 dB GainExploiting Implicit Capacitive Stacking in a

Bottom-plate N-path Filter/MixerVijaya Kumar Purushothaman, Student Member, IEEE, Eric A.M. Klumperink, Senior Member, IEEE,

Berta Trullas Clavera, and Bram Nauta, Fellow, IEEE

Abstract—A low-power interferer-robust mixer-first receiverfront-end that uses a novel capacitive stacking technique in abottom-plate N-path filter/mixer is proposed. Capacitive stackingis achieved by reading out the voltage from the bottom-plate ofN-path capacitors instead of their top-plate, which provides a2x voltage gain after down-conversion. A step-up transformer isused to improve the out-of-band (OOB) linearity performanceof small switches in the N-path mixer, thereby reducing thepower consumption of switch drivers. This paper explains theconcept of implicit capacitive stacking and analyzes its transfercharacteristics. A prototype chip, fabricated in 22 nm FDSOItechnology, achieves a voltage gain of 13 dB and OOB IIP3/IIP2of +25/+66 dBm with 5 dB Noise figure while consuming only600µW of power at fLO=1 GHz. Thanks to the transformer, theprototype can operate in the input frequency range of 0.6-1.2 GHzwith more than 10 dB voltage gain and 5–9 dB Noise figure. Thusit opens up the possibility of low-power software defined radios.

Index Terms—Passive mixer, N-path filter, CMOS, mixer-firstreceiver, bottom-plate mixing, capacitive stacking, high linearity,transformer, low power, RF front-end, interference-robust, IoT.

I. INTRODUCTION

THE advent of Internet-of-Things (IoT) has been resultingin the surge of connected devices (≥ 25 billion devices by2021 [1]) and proliferation of wireless sensor nodes. MassiveIoT applications lead to a crowded spectrum, making receiverssusceptible to mutual interference. Hence along with costand power consumption, interference robustness is becominga major concern for the radios targeting these applications.For example, NB-IoT standard has an out-of-band blockingrequirement of -15 dBm at 85 MHz offset [2], [3].

Interferer-robust CMOS RF front-ends report out-of-band(OOB) blocker 1dB compression point ≥ 0 dBm and OOB-IIP3 ≥ +25 dBm using techniques such as highly-linearLNTAs, passive-mixers, mixer-first RX, N-path filters andfeedback cancellations [4]–[16]. LNTAs consume large powerto achieve low noise figure and high linearity. Passive mix-ers and N-path filters employ power-hungry clock-generationcircuitry and drivers to drive their large switches. Often, thereported power consumption of these high-performance front-ends are in the range of a few tens to hundred mW.

Low power CMOS receivers typically employ high-Q ex-ternal filters (e.g., SAW, FBAR) or off-chip and on-chip

V.K. Purushothaman, E.A.M. Klumperink and B. Nauta with the IC-Design group, Faculty of Electrical Engineering, Mathematics, and ComputerScience, University of Twente, 7522 NB Enschede, The Netherlands. (e-mail:v.k.purushothaman@uwtente.nl)

B.T. Clavera was with IC Design group, Faculty of Electrical Engineering,Mathematics, and Computer Science, University of Twente. Now, she is withOn Design Czech s.r.o, On semiconductors, 619 00 Brno, Czech Republic.

LC resonant tanks to attenuate the blockers and improvetheir OOB selectivity [17]–[23]. Recently N-path filters andfeedback cancellations [24], [25] are adopted to improve theRF filtering and enhance the linearity performance of the RX.With power consumption ≤ 5 mW, these RXs exhibit OOBIIP3 between -20 and 0 dBm. This is at least 20 dB worsethan the high-performance interferer-robust receivers.

Our objective is to develop energy efficient interferencerobust radio techniques suitable for IoT applications and lowpower software defined radios. In [26], we presented a fullypassive N-path filter/mixer architecture that achieves conver-sion gain and high OOB linearity simultaneously. Bottom-plate mixing is used for its attractive OOB linearity per-formance [14]. Two low-power techniques were introduced:(1) an implicit capacitive stacking technique which provides6 dB voltage conversion gain ”for free” without any activeelements; and (2) a step-up transformer before the N-pathfilter to achieve high linearity at low power consumption.Exploiting these techniques, a fully-passive 1 GHz CMOS RFfront-end achieving 13 dB gain and +25 dBm OOB-IIP3 atsub-mW power consumption is realized. Compared to [26],this paper explains the concept and circuit implementation inmore depth, analyzes the transfer characteristics, and providesadditional simulation and measurement results. Please notethat the design specifications such as operating frequencyand OOB linearity, are inspired by the NB-IoT standard [2].However, the proposed work here is a proof-of-concept for thecapacitive stacking technique rather than a complete receiverfor any specific standard.

The rest of the paper is structured as follows: the concept ofimplicit capacitive stacking technique in bottom-plate N-pathfilter/mixer is discussed in Section II. The transfer functionof the proposed technique and the linearity benefits due totransformer are presented in Section III. Section IV discussesthe implementation details of the proposed fully-passive RFfront-end and its measured performance are reported in SectionV. Finally, the conclusions are summarized in Section VI.

II. IMPLICIT CAPACITIVE STACKING - CONCEPTIn this section, we will briefly summarize the fundamentals

of bottom-plate mixing and its limitations compared to top-plate mixing. Then we will introduce the concept of implicitcapacitive stacking and discuss its principle of operation.

A. Bottom-plate mixing - FundamentalsCMOS N-path filters [7], [8], [15] are commonly imple-

mented with N passive mixers connected to the top-plate of

2 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. ??, NO. ??, MAY 2020

CVIN R VG

VSVRF

fS

(a)

VRFCVIN R VGVS

VD

fS(b)

IIP3 of 4-path filter

Single-ended bottom-plate mixing

Single-ended top-plate mixing

(c)

Fig. 1: Switched RC mixer (a) Top-plate mixing, (b) Bottom-platemixing and, (c) Simulated IIP3 for 4-path singled-ended top-plateand bottom-plate mixing filters [14].

-

+VIN

R

R

VOUT

N-path filter Down-conversion

Fig. 2: Differential bottom-plate N-path filter followed by a cross-coupled switch-RC N-path down-conversion mixer [14].

the grounded capacitors on one end and the RF terminal onthe other (Fig. 1a). The on-resistance of MOS mixer-switchesis heavily modulated by the voltage at its drain and sourceterminals, i.e., the RF input and the down-converted basebandcapacitor voltage. As shown in Fig. 1a, this modulation inswitch resistance limits the achievable in-band linearity [14].

The bottom-plate mixing technique ties the RF node tothe top-plate of the capacitor while the switch connects thebottom-plate of the capacitor to ground (see Fig. 1b) [14]. TheVS node of the switch is now always grounded and the VDterminal is also pulled down to ground when the switch is on.Hence VGS of the switch remains constant, thereby reducingthe input induced variation in switch resistance. This results in10 dB higher in-band linearity compared to top-plate mixing(see Fig. 1c) [14]. On the other hand, when the switch isopen, the corresponding capacitor becomes floating as it isdisconnected from the ground. This complicates the extractionof the baseband voltage from the capacitor. However, still N-path RF band-pass filtering can be realized at the RF nodes. Adifferential implementation of a bottom-plate N-path filter isshown in Fig. 2, in which the RF voltage from the top-plate ofthe N-path capacitors is down-converted using a cross-coupledswitch-RC network [14].

B. Implicit Capacitive Stacking technique

In reference [14], the filtered RF voltage is sensed at thetop-plate of the capacitor before down-conversion. Here wepropose to sense the voltage from the bottom-plate of thecapacitor instead. Fig. 3a and Fig. 3b compare the proposedidea with implementation in [14]. We will show how this

Φ0 Φ90 Φ180 Φ270

Down-conversion mixer [14]

R

VINΦ90 Φ0 Φ270 Φ180

C2C1 C4C3

(a)

(Proposed approach)

VA4

Φ0 Φ90 Φ180 Φ270

CB4

Φ90 VA4

CB3

VA3 Φ0 VA2

CB2

Φ270 VA1

CB1

Φ180

R

VINΦ90

VA1 VA2

Φ0 Φ270

VA3

Φ180

C2C1 C4C3

Implicit Capacitive stacking

(b)

Fig. 3: Voltage read-out options in a bottom-plate 4-path filter (a)Read the top-plate voltage of the mixing capacitors [14] (b) Proposedapproach - read the bottom-plate voltage of the mixing capacitors

simple modification results in 6 dB passive voltage gain atdown-conversion.

Consider a 4-path single-ended bottom-plate N-path filterwith resistor R and capacitors C1-C4 of capacitance C, asshown in Fig. 3b. The bottom-plate of these capacitors areconnected to capacitors CB1-CB4 of capacitance CB throughswitches. Assume that the switches are ideal and have neg-ligible resistance. The switches are turned on/off by 4-phasenon-overlapping clocks φ0−270, switching at a frequency fLO.Suppose that the time constant RC is much larger than Ton ofclock phases, φ0−270, for ”mixing region” operation [7]. Aftera large number of switching cycles, each capacitor stores theaverage value of the input signal it sees during its on-time.

For simplicity, consider that a sinusoidal signal with fre-quency fin is applied at the input Vin. Let VRF be the voltageat RF node to which the top plate of all the capacitors areconnected and VC1-VC4 be down-converted voltages stored inthe capacitors C1-C4 repsectively. For fin = fLO, the resultantbaseband voltage on each capacitor is a zero-IF signal. Due to4-phase clocking, the capacitor voltages are related as follows:VC1 = −VC3 and VC2 = −VC4 (see Fig. 4). For negligibleswitch resistance, VRF at any instant is equal to the voltage ofthe capacitor switched to ground at that particular instant. Thevoltage wave at VRF can be constructed by time multiplexingthe capacitor voltages, as shown Fig. 4. It should be noted thatVRF is the band-pass filtered RF output of the bottom-plateN-path filter in [14] with fundamental frequency of fin.

Since the voltage VA1 at the bottom-plate of the capacitorC1 is equal to VRF (t) − VC1(t), its waveform is simply thewaveform of VRF , shifted down by DC voltage VC1 (seeFig.4). Similarly, voltage VA3 at the bottom-plate of C3 isVRF (t)−VC3(t) and its waveform is VRF shifted up by VC3,since VC3 < 0 here. Likewise, the voltage waveform at the

PURUSHOTHAMAN et al.: FULLY PASSIVE RF FRONT-END WITH IMPLICIT CAPACITIVE STACKING 3

RC >> Ton

VB180 = – (VC1+VC3) = -2VC1 VB0 = – (VC3+VC1) = -2VC3

VB90 = – (VC4+VC2) = -2VC4VB270 = – (VC2+VC4) = -2VC2

Φ0 Φ90 Φ180 Φ270

Ton

1/fLO

Φ270 Φ0 Φ90 Φ180 Φ270 Φ0 Φ90 Φ180

VIN(fIN ≈ fLO)

VA1Φ0 Φ90 Φ180 Φ270 Φ0 Φ90 Φ180 Φ270

VA1 = VRF – VC1

VA3Φ0 Φ90 Φ180 Φ270 Φ0 Φ90 Φ180 Φ270

VA3 = VRF – VC3

VA4Φ0 Φ90 Φ180 Φ270 Φ0 Φ90 Φ180 Φ270

VA4 = VRF – VC4

VA2

Φ0 Φ90 Φ180 Φ270 Φ0 Φ90 Φ180 Φ270

VA2 = VRF – VC2

VB180CB

Φ180 VA1

VB270

CB

Φ270 VA2

VB0CB

Φ0 VA3

VB90

CB

Φ180 VA4

VIN

R

Φ90

C2

Φ0 Φ270

C4

Φ180

C3

VA1 VA2 VA3 VA4

VRF

VC1 VC2 VC3 VC4+-

+-

+-

+- C1

VRF

Φ0 Φ90 Φ180 Φ270 Φ0 Φ90 Φ180 Φ270

Fig. 4: Voltage waveforms in a 4-path single-ended bottom-plate filter with implicit capacitive stacking

bottom-plate of remaining capacitors can be obtained. SinceVRF has a fundamental frequency of fin, so does VA1−4.

Now we will examine the voltage waveform at node VA1 atdifferent clock phases. We can see in Fig. 4 that during φ180,capacitor C3 is connected to ground (VA3 = 0), so voltageVRF will be same as VC3. This makes voltage VA1 equivalentto VC3 − VC1. Since VC3 = −VC1, we conclude that VA1 =2 × VC3 during phase φ180. We can read out this doubledvoltage VA1 during φ180 with a switch and a capacitor CBas shown in Fig. 4. This additional switch down-converts VA1to VB180, the baseband voltage in capacitor CB . This resultsin a 6 dB voltage gain compared to VC1. Likewise voltagesVA2, VA3, and VA4 can be read-out during φ270, φ0, and φ90respectively while achieving a passive voltage gain of 6 dBcompared to their respective capacitor voltages VC2–VC4 [26].

What we described above can be seen as ”CapacitiveStacking”, a technique commonly used in switched capacitorvoltage multipliers [27]. However such multipliers explicitlyreconfigure a switched capacitor circuit. For example, 2 par-allel capacitors are first charged to the same voltage andthen reordered to form a ’stacked’ series combination, sothat the voltage doubles. Switches are used for re-orderingand they introduce parasitic capacitance causing multiplierloss. In contrast, we don’t add any extra switches to realizethe stacking here. The stacking occurs already in a bottom-plate mixer when we read-out from the bottom-plate of thecapacitors. Hence we refer to this technique as ”ImplicitCapacitive Stacking” [26].

On a side note, voltage read-out through capacitors is pre-ferred here for its simple implementation. Any voltage sensingcircuit with sufficiently high input impedance in the desiredband can be used after the switches [5], [26]. Moreover, we

can also read-out from the node VA1 during φ90 and φ270but this would result in complex addition (VC1(−1 + i) andVC1(−1 − i)) with comparatively lower gain. Here φ180 ischosen for reading the node VA1, as it provides real additionVC1(−1 + (−1)) resulting 6 dB V-V gain [26]. On the otherhand, complex addition could be useful for applications suchas beam-forming or harmonic rejection.

III. ANALYSIS OF THE PROPOSED FRONT-END

In this section we will analyze the transfer function of the N-path filter/mixer circuit with the proposed implicit capacitivestacking with two main aims: 1) verify the in-band achievable6 dB voltage gain; and 2) find the frequency dependence ofthe conversion gain, especially the selectivity of the N-pathfiltering. We will use a recently introduced simplified analysisfor N-path filters/mixers using the adjoint network [28].

A. Transfer function using adjoint network

The bottom-plate mixer circuit in Fig. 3b can be split intotwo independent kernels, one for the in-phase and one for thequadrature phase signal. Since these kernels have the sameconfiguration, analysis of one kernel will hold for the other.Here we will analyse the quadrature-phase kernel, shown inFig. 5a, where phases φ90 and φ270 periodically switch thecapacitors C2 and C4 to ground respectively. Capacitors CB2and CB4 are the relevant output capacitors. Let the capacitanceof C2 and C4 be C and CB2 and CB4 be CB respectively.

Using the method described in [28], we construct an adjointnetwork for the Quadrature-phase kernel as shown in Fig. 5b.The passive elements in the kernel are retained in the adjointnetwork, however they are periodically switched with clocks

4 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. ??, NO. ??, MAY 2020

VIN

R

C2

CB2Φ90

Φ270

CB4Φ270

Φ90 C4

x(t)

++-

- ‘Sampling moment’o

TLO Φ270

Φ90

0 τ 2τ 3τ 4τ

(a)

R

C2

CB2

Φ'270

x(t)

+-

+-

o(t) = heq(t)

δ(t) o

Φ'90 CB4Φ'270

Φ'90 C4+-

+-

TLO

0 τ 2τ 3τ 4τ

δ(t) Φ'270

Φ'90

(b)

io(t)

νC2(t)

νC4(t)

0 τ 2τ 3τ 4τ 5τ 6τ

p(t)

TLO

β1 β1

β1

Φ270' Φ90'

𝑣 0

𝑣 0β2

β2 β2

(c)

Fig. 5: (a) Quadrature-phase kernel of the 4-path Filter/Mixer with proposed read-out technique, (b) Adjoint network of the kernel withreversed clock phases φ′90 and φ′270, and (c) Voltage and current waveforms in the adjoint network.

Fig. 6: Transfer function of the proposed mixer using heq(t).

whose timing waveform is exactly reversed (φ90 → φ′90 andφ270 → φ′270). The input voltage source is replaced with ashort to ground and the output node, vo(t) is driven by acurrent impulse, δ(t). Since the output vo(t) is sampled atthe end of phase φ270 in the kernel, the current impulse isintroduced to the adjoint network at t = 0+ during φ′270,as shown in the figure. The resulting current, io(t), flowingthrough the resistance R in the adjoint network is the impulseresponse, heq(t) of the linear time-invariant equivalent of thekernel [28]. The complete response of the proposed front-endcan be obtained using heq(t) as shown in Fig. 6.

The current io(t) can be given as vx(t)/R during the phaseφ′270 and φ

′90. vx(t) = vC4(t) during φ

′270 and it is equal to

−vC2(t) during φ′90. For τ ≤ t < 2τ and 3τ ≤ t < 4τ , allthe switches in the adjoint network are open, hence io(t) = 0.The capacitor voltages do not change during these time slots.

Upon application of the current impulse δ(t), at at t =0+, the capacitor CB2 is charged to vo(0+) = 1/CT , whereCT = CB +C/2. And the initial voltage across R, vx(0+) =vC4(0+) = 1/(C + 2CB). Additionally, vC4(0+) = vC2(0+)since the capacitors C2 and C4 are equal and in series.

During φ′270, the capacitors discharge through R. VoltagevC4 decay exponentially, with a time constant RCeq , where

Ceq = C + CCB/(C + CB). At t = τ−,

vC4(τ−) = vC4(0+)e−τ/RCeq ≡ β1vC4(0+) (1)

where, β1 = exp(−τ/RCeq). Similarly, vC2(τ−) can beexpressed as β2vC2(0+) where,

β2 ≈ 1 +CB

C + CB(1− β1) (2)

It should be noted that the polarity of vC2 is opposite to voand vC4 and the capacitor C2 gets charged by the capacitorCB2 during φ′270. Hence the β2 > 1 indicating vC2 increase.At t = 2τ+, the positive node of C2 is shorted to groundand CB4 is connected to C4. Charge redistribution occurs be-tween C2, C4,and CB4. It will complicate the transfer functionderivation. So to make the analysis simpler, we assume thatCB � C and charge distribution at t = 2τ+ has negligibleeffect on vC4 and vC2. Later, we will quantitatively show thatthis assumption is in practice an acceptable approximation.

Based on the above assumption, vC4(2τ+) = vC4(τ−)and vC2(2τ+) = vC2(τ−). Further, vx(t) = −vC2(t), for2τ ≤ t < 3τ . During φ′90, vC2 decays exponentially with timeconstant RCeq . At t = 3τ−,

vC2(3τ−) = vC2(τ+)e−τ/RCeq = β1β2vC2(0+)vC4(3τ−) = β2β1vC4(0+)

(3)

Using the above analysis, we constructed the waveform ofio(t), vC4(t),and vC2(t). We denote io(t) for 0 ≤ t < TLO byp(t), as shown in Fig. 5c.

At t = TLO+ = 4τ+, the discharging process repeats withcapacitor C4 connected to ground again and C2 connectedto CB2. However, the initial voltages of vC4 and vC2 are

PURUSHOTHAMAN et al.: FULLY PASSIVE RF FRONT-END WITH IMPLICIT CAPACITIVE STACKING 5

C = CB Analysis _ Simulation

(a)

_ SimulationAnalysisC = 100 CB

(b)

Fig. 7: Comparison of analytical and simulated Heq(f), for the circuitshown in Fig. 4 with fLO = 1 GHz C = 16 pF, 160 pF and 1.6 nFand for (a) For C = CB and (b) For C = 100 × CB .

now β1β2vC4(0+) and β1β2vC2(0+) respectively. It meansthat the waveform p(t) repeats every clock period TLO withinitial capacitor voltages scaled by a factor β1β2. If heq(t)is the response for vC4(0+) and vC2(0+), then response forvC4(TLO+) and vC2(TLO+) should be β1β2heq(t− TLO).

Following the approach employed in [28], we can rewritethe impulse response heq(t) as,

heq(t) = p(t) + β1β2heq(t− TLO) (4)

In the frequency domain,

Heq(f) =P (f)

1− β1β2e−j2πfTLO(5)

From the Fig. 5c, we note that p(t) can be described as a sumof decaying exponentials as shown below,

p(t) =vxR

(h(t)−β1h(t− τ))

− β2 (h(t− 2τ)− β1h(t− 3τ)))(6)

where h(t) ≡ e−t/RCeq · u(t) and u(t) denotes unit-stepfunction. The fourier transform of p(t) is given as,

P (f) =H(f)

R(C + 2CB)(1− β1e−j2πfτ

− β2(e−j4πfτ − β1e−j6πfτ ))(7)

where, H(f) = RCeq/(1 + j2πfRCeq). Finally, Heq(f) canbe obtained using (5) and (7).

Fig. 7a and Fig. 7b compares the Spectre simulation resultswith analytical equation of Heq(f) for fLO = 1 GHz, R =50 Ω, and three different values of CB = 16 pF, 160 pF and1.6 nF. For the ratio of C/CB = 1, the in-band gain estimationis 1.2 dB smaller than the simulation results. This is due to ourassumption of negligible charge distribution. We find that thedifference between simulation and analytical model decreases

rapidly with increase in C/CB ratio. It becomes less than0.3 dB for C/CB > 4. At out-of-band, the simulation andanalytical results are in agreement irrespective of the ratios.

B. Linearity considerations - Impedance up-conversion

N-path passive mixer-first front-ends often use largeswitches with power-hungry LO drivers to achieve high OOBlinearity. In [29], the maximum achievable OOB-IIP3 in a N-path passive mixer/filter is estimated as:

VIIP3 =

√4

3

(1 + ρ)4

ρ3(2g22 − g3(1 + ρ))(8)

where ρ is the ratio of switch resistance, Rsw to sourceresistance Rs (ρ = Rsw/Rs), g2 and g3 are calculated fromthe 2nd and 3rd derivation of ID(VDS). It can be shownthat g2 = (2VOD)−1 and g3 = −(2V 2SAT )−1, where VOD isoverdrive voltage and VSAT is velocity saturation parameter,respectively. According to (8), low ρ or high Rs/Rsw ratioresults in large VIIP3.

In this work, we propose to increase the Rs/Rsw ratioby increasing the source resistance Rs rather than reducingRsw [17], [30]. This allows for achieving good linearity atlow power consumption. The principle of using impedanceconversion to lower the power consumption is similar to thatof matching networks in other low-power RF front-ends [19]–[22]. However, there the primary aim is to exploit voltage gaindue to impedance up-conversion and achieve low noise figureat low power. We also target high OOB linearity performancein our mixer-first RX here [26]. Though the voltage gain isa benefit for NF, it increases in-band swing and limits theachievable in-band linearity. A limitation associated with alarge Rs is the large signal loss due to unwanted low passfiltering caused by parasitic capacitance at RF nodes [31].Hence the trade-off between out-of-band linearity and signalloss due to unwanted filtering determines the optimal Rs.Transformers with wide bandwidth are preferred to covermultiple RF bands with tunable N-path filters [26].

IV. DESIGN AND IMPLEMENTATION

In this section, we will discuss the design considerations andcircuit implementation of a RF front-end with the proposedcapacitive stacking technique.

A. Design considerations

In Section III, ideal capacitors and switches are used for thetransfer function analysis of implicit capacitive stacking. How-ever, the real capacitor has parasitic capacitance to substrate.Let us qualitatively examine the behavior of the proposed 4-path filter/mixer with parasitic capacitances.

The proposed 4-path filter/mixer with equivalent parasiticcapacitance, CP at the RF input is shown in Fig. 8. Theparasitic capacitances of C1−4 are always connected to the RFinput. Hence the parasitic capacitance of the floating capacitorsintroduce signal loss by shunting it to ground, i.e., passivelow-pass filtering occurs due to Rs and CP before the N-path

6 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. ??, NO. ??, MAY 2020

VA1 VA2 VA3

Φ270

Rs

VINΦ90 Φ0 Φ180

C2C1 C4C3CP

CB4

Φ90 VA4

CB3

VA3Φ0 VA2

CB2

Φ270 VA1

CB1

Φ180

Vx

Passive 1st order low-pass filtering

Zs = Rs || 1/sCp

VA4

CP – Equivalent parasitic capacitance of C1-4

CX – Effective capacitance seen from Vx to C1-4CX

Rs Vx

VIN CP RshFor CB

PURUSHOTHAMAN et al.: FULLY PASSIVE RF FRONT-END WITH IMPLICIT CAPACITIVE STACKING 7

Φ0 Φ90 Φ180 Φ270

2LO+

2LO- ÷2

Φ270

N4

N8

C4

C8

Φ180

N3

N7

C3

C7

Φ90

N2

N6

C2

C6

Φ0

N1

N5

C1

C5

VRF

Rs c

RF-

RF+

VC

VC

VC

VC

VC

VC

VC

VC

Φ0 Φ90

Φ90

Φ180

Φ180

Φ270

Φ270

On-chip

1:2 MC1 MC2 MC3 MC4

MC5 MC6 MC7 MC8

M1 M2 M3 M4

Φ0

CB1

N1 N7

Φ0 Φ180 BBI+

M5 M6

CB3

N3 N5

Φ180 Φ0 BBI-

M7 M8

CB4

N4 N6

Φ270 Φ90 BBQ-

M11 M12

CB2

N2 N8

Φ90 Φ270 BBQ+

M9 M10

Fig. 10: Complete architecture of the implemented RF front-end

4) Mixer switches can be sized up to provide low switchresistance and increase the OOB linearity at the cost ofpower consumption [29].

As mentioned in the Section I, inspired by the NB-IoTstandard, we chose the operating frequency, fLO, in the rangeof 0.7 – 1.0 GHz [2]. Such fLO also facilitate us to experimentwith multiple ”off-the-shelf” transformers. Further we chosea step-up transformer with turn-ratio 1:2 to achieve >20 dBmOOB IIP3 while targeting ≤1 mW of power at fLO=1 GHz.

B. Bottom-plate N-path filter with bottom-plate read-out

The circuit schematic of the fully-differential implemen-tation of the proposed RF front-end is shown in Fig. 10. Itis composed of an off-chip transformer, a differential 4-pathbottom-plate filter with the proposed read-out circuit and a4-phase LO generator. With no other active circuitry, clockdrivers determine the total power consumption of the RF front-end. An off-chip transformer is preferred for its low insertionloss which is good for NF.

All the mixer switches (M1−M12) in the front-end are im-plemented with NMOS transistors of W/L= 9.6µm/20nm.When turned on, these switches provide a differential re-sistance of 38 Ω. For these transistors, VOD = 0.302 Vand VSAT = 0.248 V. Employing this in (8), the front-endshould achieve an OOB-IIP3 of +24 dBm with a 1:2 step-uptransformer. The simulation results also report similar OOBIIP3 of +25 dBm with these small switches. NMOS switchesMC1 −MC8 with 4× smaller W/L are used to periodicallyreset the dc common-mode level of mixer switches from anexternal supply VC [14].

All the capacitors are Metal-oxide-metal (MOM) capacitorswith Metal 7 as top-layer and Metal 3 as bottom-layer toreduce the total parasitic capacitance to substrate. Based onQRC extraction, the parasitic capacitance is about 1.3% ofthe MOM capacitance. Parasitic capacitance of C1−8 togetherwith source impedance provides unwanted low-pass filteringresulting in signal loss and causes Zin degradation [31].To reduce the signal loss and achieve desired impedancematching at fLO = 1 GHz, C1−8 is chosen to be 6.4 pF in

Divide-by2

(@ 2fLO)50% duty-cycle (@ fLO)25% duty-cycle

Φ0 Φ90 Φ180 Φ270

CK

CKb

CLK

D Q

CLK

D QΨ2

CLKb CLKb

Db Qb Db QbΨ4

Ψ1

Ψ3

Divide-by-2

Qb

CLKb

Q

Differential D-latch

D

CLK CLK

CLKb

DbQbQ

(a)

0.6 mW at 1 GHz LO frequencyANDs + Buffers

(48%)

DIVIDER(27%)

Limiters(25%)

(b)

Fig. 11: Multiphase LO generation – (a) Implementation and (b)Power consumption breakdown

this design. Switches M5 − M12 isolate CB1−4 and theirparasitic capacitances from the RF terminal when they areturned off. CB1−4 determines the shape of Zin at out-of-band frequencies and the -3 dB bandwidth of RF-RF transfergain, f−3 dB,RF. Using the transfer function given in (5), weestimated that a 15 MHz IF bandwidth is desirable to achievefiltering and >+20 dBm IIP3 at 80 MHz. Hence, we choseCB1−4 to be 4.2 pF so that together with load capacitanceof the measurement probe, a 30 MHz f−3 dB,RF is realized.

C. Multiphase LO generation

All the switches are driven by 4-phase non-overlapping 25%duty-cycle clocks, generated using on-chip frequency dividerand multi-phase generator. As shown in Fig. 11a, the clockgeneration circuitry employs divide-by-2 circuit to generate50% duty-cycle quadrature clocks from an input differentialclock at 2fLO. These 50% duty-cycle quadrature clocks areANDed with each other to generate 25% duty-cycle non-overlapping quadrature clocks at the same frequency. Equalrise and fall time in LO buffers ensures the shape of LOpulses throughout the propagation and maintains the desiredduty-cycle. For similar rise and fall time, PMOS and NMOStransistors in LO buffers should have equal driving capability.In conventional CMOS process, the PMOS should be typically2-3× larger than the NMOS to achieve equal driving strength,i.e., Wp ' 3Wn, assuming minimum gate length L for all thetransistors. This results in an input capacitance, Cin = 4WnL.On the other hand, GF22 nm FDSOI uses SiGe channel in thePMOS transistors to achieve driving capability similar to that

8 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. ??, NO. ??, MAY 2020

0.8 mm

0.4

mm RF CAP BB CAP

SWCKGEN DECAP

RF INXFMR

CHIP

PURUSHOTHAMAN et al.: FULLY PASSIVE RF FRONT-END WITH IMPLICIT CAPACITIVE STACKING 9

600 800 1000 1200LO frequency [MHz]

0

2

4

6

8

10

DSB

Noi

se fi

gure

[dB

]

-5

-4

-3

-2

-1

0

Inse

rtio

n lo

ss [d

B]

Measured NFSimulated NF

NF

Insertion loss

(a)

600 800 1000 1200RF frequency [MHz]

-30

-20

-10

0

10

20

Gai

n an

d S1

1 [d

B] Attenuation: 4.5 dB

(b)

900 950 1000 1050 1100RF frequency [MHz]

-30

-20

-10

0

10

20

Gai

n an

d S1

1 [d

B]

Gain (Measured)S11 (Measured)Gain (simulated)S11 (simulated)

(c)

Fig. 13: (a) Measured insertion loss of the transformer; and simulated and measured inband noise figure for multiple LO; (b) Measured gainand S11 vs. RF for multiple LO; (c) Simulated and measured gain and S11 vs. RF for LO =1 GHz.

0 2 4 6 8 10Normalized frequency offset ( f/BW)0

20

40

60

80

IIP2

& II

P3 [d

Bm

]

-10

-5

0

5

B1d

B [d

Bm

]

IIP3

B1dB

IIP2

(a)

600 800 1000 1200LO frequency [MHz]

0

20

40

60

80

OO

B-I

IP2

& O

OB

-IIP

3

-8

-6

-4

-2

0

2

OO

B-B

1dB

& C

P1dB

IIP2

IIP3

B1dB

CP1dB

(b)

-50 -40 -30 -20 -10Blocker power [dBm]

0

2

4

6

8

10

NF

degr

adat

ion

[dB

] f-offset = 80 MHzf-offset = 160 MHz

(c)

Fig. 14: (a) Measured linearity performance: IIP3, IIP2 and B1dB vs. relative frequency offset ∆f/f−3 dB,BB; (b) Measured Linearityperformance (IIP3, IIP2, and B1dB at ∆f/f−3 dB,BB = 10) and in-band CP1dB for multiple LO frequencies; (c) Measured NF degradationdue to blockers for fLO = 1 GHz. (DSB-NF = 5 dB for no blockers).

blocker located at 80 MHz away from fLO. Since the measuredB1dB (-1 dBm) is higher than −15 dBm, it is clear that the NFdegradation is largely due to LO phase noise from the on-chipmulti-phase generation. Since sub-mW power consumption istargeted here, the LO phase noise is not as good as high-performance RXs [9] [16]. On the other hand, the achievedblocker NF of 10 dB for a −15 dBm blocker is competitivewith other sub-mW RF front-ends. For example, the 1.15 mWRX, reported in [24], achieves a blocker NF of 13.7 dB for a−20 dBm blocker located at 50 MHz offset.

D. LO leakage

Any mismatch between the mixer switches and LO buffersresults in asymmetric leakage of LO signal from gate to thedrain terminal of the switches [33]. Imbalance between thedifferential terminals of the transformer will also contributeto LO leakage in this implementation. Hence, careful layoutis carried out and dummy transistors are used to improvethe matching. To account for process variation, LO leakageis measured for 4 different samples. As shown in Fig. 15,the proposed RF front-end achieves

10 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. ??, NO. ??, MAY 2020

R

VIN

Proposed RF front-

end

x4

Gm

Baseband Transconductor

2Vn,Gm

NF

(a)

10-1 100 101 102 103Transconductance [mS]

0

2

4

6

8

10

12

DSB

_NF

[dB

]

(3 dB, 4 mS)

(6 dB, 0.8 mS)

fLO = 1 GHzNEF = 0.70

(2 dB, 30 mS)

[14](6 dB, 250 mS)

[12](2.9 dB, 200 mS)[10](2.6 dB, 100 mS)

[16](2.5 dB, 360 mS)

(b)

Fig. 16: Design set-up to estimate the Noise figure of the completefront-end and (b) Simulated DSB NF vs. Transconductance at the 1st

stage of baseband circuitry.

for linearity), this leads to a current consumption of 320µAand 1.6 mA of current respectively, for 4 baseband transcon-ductors. It is much less compared to baseband circuitry in otherstate-of-the-art mixer-first front-ends, shown in Fig. 16b. Weestimated these numbers using the simulation setup illustratedin Fig.16a, similar to the methodology described in [10]. Onthe other hand, the baseband amplifiers may degrade the in-band linearity performance of the proposed front-end. For out-of-band linearity, the design of baseband amplifiers is relaxedby the 20 dB attenuation provided by the proposed RF front-end and facilitates competitive linearity performance. Anotherway to improve linearity might be the use of LC resonant tanksinstead of transformers to achieve impedance up-conversion.The band-pass behavior of LC resonant tank improves theout-of-band blocker attenuation at the cost of noise [29] andflexibility in operating input frequency.

VI. CONCLUSIONThis paper described and analyzed implicit capacitive stack-

ing in a bottom-plate N-path filter/mixer which results in 2×voltage gain in a fully-passive switch R-C circuit. Passivevoltage gain facilitates low noise figure at the cost of additionalcapacitor area. Further, an off-chip step-up transformer with1:2 turn ratio is employed to achieve 6 dB voltage gain andhigh OOB linearity with small mixer switches. A 600µWfully-passive RF front-end achieving 13 dB gain, 5 dB NF and+25 dBm OOB-IIP3 is demonstrated, opening up a possibilityfor highly-linear RX for low power IoT and software definedradio applications.

ACKNOWLEDGEMENT

The authors would like to thank Global Foundries for silicondonation, Gerard Wienk for CAD assistance, Henk de Vriesfor measurement setup assistance, and Dr. Yao-Hong Liu andProf. Shanti Pavan for useful discussions.

REFERENCES

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[2] “Digital cellular telecommunications system (Phase 2+) (GSM);GSM/EDGE Radio transmission and reception 3GPP TS 45.005 V13.4.0Release 13,” 2017.

[3] P. Tseng, W. Yang, M. Wu, L. Jin, D. Li, E. Low, C. Hsiao, H. Lin,K. Yang, S. Shen, C. Kuo, C. Heng, and G. Dehng, “A 55 nm SAW-Less NB-IoT CMOS Transceiver in an RF-SoC with Phase Coherent RXand Polar Modulation TX,” in 2019 IEEE Radio Frequency IntegratedCircuits Symposium (RFIC), June 2019, pp. 267–270.

[4] E. Klumperink and A. Molnar, “Interference robust, flexible radioreceivers in CMOS,” IEEE Radio Frequency Integrated Circuits - VirtualJournal, vol. 6, October 2014.

[5] M. C. M. Soer, E. A. M. Klumperink, Z. Ru, F. E. van Vliet, andB. Nauta, “A 0.2-to-2.0 GHz 65 nm CMOS receiver without LNAachieving >11 dBm IIP3 and 15 dBm wide-band IIP3,66 dB IRR supporting non-contiguous carrier aggregation,” in 2015IEEE Radio Frequency Integrated Circuits Symposium (RFIC), May2015, pp. 155–158.

[11] A. Nejdel, M. Abdulaziz, M. Törmänen, and H. Sjöland, “A PositiveFeedback Passive Mixer-First Receiver Front-End,” in 2015 IEEE RadioFrequency Integrated Circuits Symposium (RFIC), May 2015, pp. 79–82.

[12] Z. Lin, P. Mak, and R. P. Martins, “A 0.028 mm2 11 mW single-mixingblocker-tolerant receiver with double-RF N-path filtering, S11 centering,+13 dBm OB-IIP3 and 1.5-to-2.9 dB NF,” in 2015 IEEE InternationalSolid-State Circuits Conference - (ISSCC) Digest of Technical Papers,Feb 2015, pp. 1–3.

[13] C. K. Luo, P. S. Gudem, and J. F. Buckwalter, “A 0.4 - 6-GHz 17-dBm B1dB 36-dBm IIP3 Channel-Selecting Low-Noise Amplifier forSAW-Less 3G/4G FDD Diversity Receivers,” IEEE Transactions onMicrowave Theory and Techniques, vol. 64, no. 4, pp. 1110–1121, April2016.

[14] Y. Lien, E. Klumperink, B. Tenbroek, J. Strange, and B. Nauta, “Ahigh-linearity CMOS receiver achieving +44 dBm IIP3 and +13 dBmB1dB for SAW-less LTE radio,” in 2017 IEEE International Solid-StateCircuits Conference (ISSCC), Feb 2017, pp. 412–413.

[15] E. A. M. Klumperink, H. J. Westerveld, and B. Nauta, “N-path filtersand mixer-first receivers: A review,” in 2017 IEEE Custom IntegratedCircuits Conference (CICC), April 2017, pp. 1–8.

[16] Y. Lien, E. A. M. Klumperink, B. Tenbroek, J. Strange, and B. Nauta,“Enhanced-Selectivity High-Linearity Low-Noise Mixer-First ReceiverWith Complex Pole Pair Due to Capacitive Positive Feedback,” IEEEJournal of Solid-State Circuits, vol. 53, no. 5, pp. 1348–1360, May 2018.

PURUSHOTHAMAN et al.: FULLY PASSIVE RF FRONT-END WITH IMPLICIT CAPACITIVE STACKING 11

TABLE IRESULT SUMMARY AND COMPARISON WITH HIGH-PERFORMANCE MIXER-FIRST RECEIVERS

Features JSSC10[6]

RFIC15[11]

ISSCC15[12]

RFIC16[30]

JSSC18[16]

This Work

Technology 65 nm 65 nm 65 nm 65 nm 45 nm SOI 22 nm FDSOIFrequency [GHz] 0.1 - 2.4 2 - 3 0.1 - 1.5 0.03 - 0.3 0.2 - 8 0.6 - 1.3Power (Analog) [mW] 30 8.2 11@1.5 GHz a 36 50 0

b

Power (Digital - Clock) [mW] 7.2 - 39.6 19.2 - 67.2 7.2 - 10.1 6 - 240 0.4 - 0.78Gain [dB] 40 - 70 7.5 38 21-36 21 9 - 14BB BW [MHz] 10 3 - 10 2 2 - 40 10 16DSB-NF [dB] 3 - 5 2.5 - 4.5 2.9 6 2.3 - 5.4 5 - 9OOB IIP3[dBm @ ∆f /BW] 25 @ 10 26 @ 33.3 10 @ 15 41 @ 20 39 @ 8 25 @ 10OOB IIP2[dBm @ ∆f /BW] 56 @ 10 65 @ 33.3 47 @ 15 90 @ 20 88 @ 8 66 @ 10B1dB [dBm @ ∆f /BW] 10 @ 10 3 @ 33.3 N.A. 11 @ 27.5 12 @ 8 1 @ 10LO leakage [dBm]

12 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. ??, NO. ??, MAY 2020

[30] H. Westerveld, E. Klumperink, and B. Nauta, “A cross-coupled switch-RC mixer-first technique achieving +41 dBm out-of-band IIP3,” in 2016IEEE Radio Frequency Integrated Circuits Symposium (RFIC), May2016, pp. 246–249.

[31] Y. Lien, E. A. M. Klumperink, B. Tenbroek, J. Strange, and B. Nauta,“High-Linearity Bottom-Plate Mixing Technique With Switch Sharingfor N -path Filters/Mixers,” IEEE Journal of Solid-State Circuits, vol. 54,no. 2, pp. 323–335, Feb 2019.

[32] S. Pavan and E. Klumperink, “Analysis of the Effect of Source Capaci-tance and Inductance on N-Path Mixers and Filters,” IEEE Transactionson Circuits and Systems I: Regular Papers, vol. 65, no. 5, pp. 1469–1480, May 2018.

[33] T. H. Lee, The Design of CMOS Radio-frequency Integrated circuits,2nd ed. Cambridge University Press, 2004.

Vijaya Kumar Purushothaman (S’16) received theBachelor’s degree in electronics and communicationfrom the College of Engineering, Guindy, Chennai,India, in 2011, and the M.Sc. degree in electricalengineering (Microelectronics) from the Delft Uni-versity of Technology, Delft, The Netherlands, in2016. From 2011 to 2013, he was with SynopsysInc. in Bangalore, India, working as an applicationengineer. He is currently pursuing the Ph.D. degreewith the Integrated Circuit Design Group, Universityof Twente, Enschede, The Netherlands. His current

research interest includes analog and radio-frequency circuits and systems forlow-power interferer-robust transceivers.

Eric A. M. Klumperink (M’98 – SM’06) wasborn in Lichtenvoorde, The Netherlands, in 1960.He received the B.Sc. degree from HTS, Enschede(1982), worked in industry on digital hardware andsoftware, and then joined the University of Twente,Enschede, in 1984, shifting focus to analog CMOScircuit research. This resulted in several publicationsand his Ph.D. thesis - “Transconductance BasedCMOS Circuits: Circuit Generation, Classificationand Analysis” in 1997. In 1998, he started as anAssistant Professor at the IC-Design Laboratory in

University of Twente and shifted research focus to RF CMOS circuits (e.g.sabbatical at the Ruhr Universitaet in Bochum, Germany). Since 2006, he isan Associate Professor, teaching Analog and RF IC Electronics and guidingPhD and MSc projects related to RF CMOS circuit design with focus onSoftware Defined Radio, Cognitive Radio and Beamforming. He served as anAssociate Editor for the IEEE TCAS-II from 2006 to 2007, IEEE TCAS-Ifrom 2008 to 2009 and the IEEE JSSC from 2010 to 2014, as IEEE SSCDistinguished Lecturer from 2014 to 2015, and as a member of the technicalprogram committees of ISSCC from 2011 to 2016. He has been a member ofthe technical program committee of IEEE RFIC Symposium since 2011. Heholds several patents, authored and co-authored 175+ internationally refereedjournal and conference papers, and was recognized as 20+ ISSCC papercontributor over 1954-2013. He is a co-recipient of the ISSCC 2002 andthe ISSCC 2009 “Van Vessem Outstanding Paper Award”.

Berta Trullas Clavera received the B.S. degree inindustrial engineering from Polytechnic Universityof Catalonia, Spain, in 2015 and the M.S. degreein electrical engineering from the University ofTwente, The Netherlands, in 2017. She joined ONSemiconductor, ON Design Czech s.r.o., in 2018,as an electronic design engineer for the Analog IPDevelopment team.

Bram Nauta (M’91–SM’03–F’08) was born in 1964in Hengelo, The Netherlands. In 1987 he receivedthe M.Sc degree (cum laude) in electrical engi-neering from the University of Twente, Enschede,The Netherlands. In 1991, he received the Ph.D.degree from the same university on the subject ofanalog CMOS filters for very high frequencies. In1991, he joined the Mixed-Signal Circuits and Sys-tems Department of Philips Research, Eindhoven theNetherlands. In 1998, he returned to the Universityof Twente, where he is currently a distinguished

professor, heading the IC Design group. Since 2016, he also serves as chairof the EE department at this university. His current research interest is high-speed analog CMOS circuits, software defined radio, cognitive radio andbeamforming. He served as the Editor-in-Chief of the IEEE Journal of Solid-State Circuits (JSSC) from 2007 to 2010 and was the 2013 program chair ofthe International Solid State Circuits Conference (ISSCC). He is currentlythe President of the IEEE Solid-State Circuits Society (2018-2019 term).Also, he served as Associate Editor of IEEE Transactions on Circuits andSystems II from 1997 to 1999, and of JSSC from 2001 to 2006. He was inthe Technical Program Committee of the Symposium on VLSI circuits from2009 to 2013 and is in the steering committee and programme committeeof the European Solid State Circuit Conference (ESSCIRC). He served asa Distinguished lecturer of the IEEE, is co-recipient of the ISSCC 2002and 2009 “Van Vessem Outstanding Paper Award”. In 2014, he received the‘Simon Stevin Meester’ award (500.000BC), the largest Dutch national prizefor achievements in technical sciences. He is fellow of the IEEE and memberof the Royal Netherlands Academy of Arts and Sciences (KNAW).