Time-Stamping-Based Synchronization of Power

Electronics Building Block Systems

Tommi Laakkonen, Toni Itkonen, Julius Luukko, Jero Ahola

Lappeenranta University of Technology (LUT)

Institute Of Energy Technology

Department of Electrical Engineering

P.O.Box 20, FI-53851, Lappeenranta, Finland

Email: firstname.lastname@lut.fi

Abstract—Integrated design has become a very attractivechoice for modern power electronic systems. One way to in-troduce modularity to integrated designs is to utilize intelligentpower electronics building blocks as a base for power electronicssystems. The main reason for moving toward a building-block-

based design is that the traditional centralized control structuredoes not provide much flexibility and reusability. A building-block-based design needs a distributed control scheme that setsnew challenges to system design. Distributed control of buildingblocks requires a deterministic, real-time communication schemeand accurate synchronization. The synchronization becomes anissue especially with ring-based control topologies. In this paper,a flexible time-stamping-based synchronization scheme for acascaded ring communication topology is proposed. Further, acommunication scheme suitable for building-block-based designsis presented. The achieved synchronization accuracy is analyzedin relation to a parallel connection of power semiconductors.

I. INTRODUCTION

An integrated system approach has become an interesting

alternative to traditional design and manufacturing methods in

power electronics. Besides increasing the level of integration,

the higher level of reusability is also a desired goal. The

possibility of reusing the designs in the traditional systems

based on centralized control structures is usually poor. For new

applications and up/downscaled designs, the control scheme

may have to be totally redesigned. One of the proposed ap-

proaches for modular design is the power electronics building

block (PEBB) concept, the development of which has been

funded by the U.S. Navy’s Office of Naval Research [1].

The goal of the PEBB-based design is to have a set of

reusable building blocks that can be used in different kinds

of applications.

The building-block-based designs require more complex

control structures compared with the traditional centralized

structures. Deterministic communication and accurate syn-

chronization are needed to control the distributed building

blocks. The control topology has an effect on the requirements

set for the control scheme. For example, a star topology

consists of simple point to point connections, and thus the

communication capacity needed for each connection is low.

The synchronization can be easily done by sending the mes-

sages from a central unit simultaneously. On the other hand, if

the number of building blocks can vary a lot, the star topology

is not flexible, since the physical connections must be designed

according to the maximum number of building blocks.

A cascaded ring (also called daisy-chained) control architec-

ture has been proposed for distributed PEBB systems [2], [3].

These solutions are based on a communication and synchro-

nization scheme called Power Electronics Systems Network

(PESNet), proposed in [4]–[6]. The synchronization scheme

in PESNet is based on a custom-designed communication

protocol. The predefined propagation delays are taken into

account in the implementation of messaging. The scheme is

valid only for a certain configuration. If the propagation delays

are changed, for instance, the physical communication path

is altered, the implementation of the communication protocol

must be reconfigured.

Simple physical connections can be used with the cascaded

ring control topology, only one transmitter/receiver pair is

needed in each block. The flexibility and scalability of this

scheme is good, although a more complex communication

protocol and higher communication capacity is needed to

obtain the same performance as with the star topology. The

synchronization is a major concern with the cascaded ring

topology. Although a separate synchronization cabling with

star connection could be used with the ring communication

structure, it would decrease the flexibility and increase the

amount of cabling. If the ring communication structure is used

also for synchronization, a dedicated synchronization method

is needed.

In this paper, a flexible time-stamping-based synchroniza-

tion scheme for a cascaded ring topology is presented. The

synchronization scheme is not embedded in the implementa-

tion of the communication scheme, so it can be used with

a variety of communication protocols. The synchronization

cycle can also be different from the operational cycle of the

application. This enables the same synchronization accuracy

regardless of the operational cycle of the application, for

instance, a switching period. A communication scheme for

a cascaded ring topology is also presented. In Chapter II

the synchronization of nodes in cascaded ring topology is

discussed. In section II-A, the synchronization method used

in PESNet is described. The proposed synchronization scheme

is presented in section II-B. Chapter III covers implementa-

tion and testing. The communication scheme is presented in

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section III-A, the implemenatation of the synchronization in

section III-B, and the test setup and results in section III-C.

The effect of synchronization accuracy in parallel-connected

PEBB systems is discussed in section III-D. Conclusions are

presented in Chapter IV.

II. SYNCHRONIZATION OF CASCADED BUILDING BLOCKS

A chained ring topology is challenging with respect to syn-

chronization. The propagation delay to each node is different.

In addition, each node has a clock source introducing clock

drift. The drift of each clock source is different. The behavior

of the cascade of such nodes is quite complex.

An easy way to achieve the synchronization would be to use

dedicated cabling for synchronization. With a dedicated star

topology network, as presented in Fig. 1, the synchronization

would be straightforward. A simple synchronization pulse

would be sent simultaneously to the nodes. The use of a ring

topology usually aims at a simple connection of nodes, flex-

ibility, and scalability. The use of dedicated synchronization

cabling hinders these goals.

To maintain the desired properties of a ring topology, the

synchronization should be implemented using the existing

communication path. A simple solution to synchronize the cas-

caded nodes is to send synchronization messages to the nodes.

The nodes synchronize to the receptions of these messages.

This method introduces a synchronization error resulting from

the propagation delays. A single synchronization message

arrives to each node at a different time. Synchronization

accuracy could be increased by reducing the propagation

delays [7].

If the propagation delays are known, they can be taken

into account to increase the synchronization accuracy. If each

node knows its position in the ring and the total number of

nodes, they can calculate the time when the last node should

receive the synchronization message. After the synchronization

message is received, each node waits a certain time before a

synchronization event is signaled. This method requires that

the propagation delay between two nodes is known, including

the delay between the nodes and the pass-through delay of a

node.

m a s t e rn o d e

s l a v en o d e 3

s l a v en o d e 1

s l a v en o d e 2

(a)

m a s t e rn o d e

s l a v en o d e 3

s l a v en o d e 1

s l a v en o d e 2

(b)

Fig. 1. The synchronization of building-block-based system with cascadedring communication topology can be done in different ways. a) A separatecabling with star topology is used to synchronize the nodes. b) The ringcommunication topology is utilized also for synchronization.

A. Synchronization in PESNet

The synchronization method presented in [4]–[6] uses the

predetermined propagation delays. In this case, a synchroniza-

tion event is chosen to be the reception of a certain field in a

synchronization frame. A frame includes a start field and all

the addresses of the slave nodes. Every address is stored in a

separate field. The addresses are in reverse order starting from

the last. The communication frames are observed and sent a

byte at a time (4B/5B encoding is used). When a start field of

a synchronization frame is observed, the nodes start to wait

their own address field. Each node should receive their own

address field at the same time, and a synchronization event is

then signaled. Excess bit stuffing between the address fields is

used in the synchronization frames so that all the nodes would

receive their own address field at the same time. The amount

of bit stuffing must be selected according to the propagation

delay between the reception instants of consecutive nodes.

The benefit of this kind of a synchronization method is

that the compensation of propagation delays is embedded in

the frame structure itself. Outside the communication scheme,

there is no need for any additional functionality to achieve

synchronization events. This is also a drawback of the syn-

chronization scheme. The scheme is tightly coupled with

the structure of the communication frame, so a customized

communication protocol is needed. Further, the amount of bit

stuffing between the address fields must be chosen according

to the propagation delays, which have to be measured or

approximated. If the communication system is altered, for

instance, the cable length or type is changed, the data frame

structure has to be changed accordingly.

An enhancement to the described method is proposed in

[8]. The synchronization procedure consists of a sequence of

synchronization frames, instead of a single frame. When a

node receives a synchronization frame, it waits for a prete-

dermined time before sending it forward. This wait time is

chosen according to the real propagation delays. On each

reception of a frame, a node increases its system clock. When

the system clock reaches a certain value, a synchronization

event occurs. Because a sequence of synchronization frames is

used to synchronize the nodes, every node must continuously

transmit messages, even null messages, until the synchroniza-

tion sequence is over.

An improvement of this method is that the frame structure

does not need to be changed when the propagation delay is

changed. It can be taken into account by the wait time imple-

mented in the nodes. The method is still tightly coupled with

the communication protocol. Both of these methods assume

that no other data transmissions occur during a synchronization

sequence. If the sequence is disturbed and other data is sent

during it, the synchronization is directly affected. To avoid

these conflicts, the communication scheme in PESNet is cyclic

and master-slave-based, that is, each of the data transmissions

is initiated by the master. The slave nodes cannot initiate a

data transmission.

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B. Proposed synchronization method

The proposed synchronization method is of explicit nature,

meaning that all the nodes have a local clock, in which

the operations of a node are synchronized. The clocks of

the slave nodes are synchronized to the clock of the master

node. Synchronous operations do not require event signaling,

like in implicit systems. The basis of the synchronization

scheme is accurate time stamping of messages. Time stamps

are used to determine the propagation delays of the system

(Fig. 2). The delays are divided into two categories: delays

from a transmission time stamping point of a node to the

reception time stamping point of the next node (internode

delay), and delays from a reception time stamping point of a

node to the transmission time stamping point of the same node

(pass-through delay). The time stamping scheme is similar to

the method defined in the standard IEEE1588 (Standard for

a Precision Clock Synchronization Protocol for Networked

Measurement and Control Systems) [9], although the way in

which the time stamps are used is different. IEEE1588 is

applicable to symmetric communication channels only, thus

excluding the unidirectional cascaded ring topology used here.

m a s t e rn o d e

s l a v en o d e n

s l a v en o d e 1

s l a v en o d e 2

t d 1 t d 2

t d 3

t d nt d ( n + 1 )

t h 1

t h 2

t h n

. . .

Fig. 2. Cascaded system of n nodes. Propagation delays of the system aredivided into internode delays (td1 , td2, ..., td(n+1)) and slave node pass-throughdelays (th1 , th2 , ..., thn).

An initialization sequence is performed at startup. First,

a test message is sent by the master node to check the

validity of the communication path. A unique device number

is assigned to each of the slave nodes during this sequence.

The total amount of slave nodes is also determined. If the

communication path is intact, the initialization sequence of

the synchronization can start.

The master node sends a synchronization frame and saves

the transmission time tmtx . Each of the slave nodes saves the

reception time tsirx, forwards the synchronization frame, and

saves the transmission time tsitx, si being the ith slave node in

the ring. The reception time tmrx of the synchronization frame is

also saved by the master node. The master node also sends the

transmission time tmtx to the slave nodes in a separate frame.

Slave nodes calculate their pass-through delays

thi = tsitx − tsi

rx, (1)

and send them forward. The subscript hi denotes the pass-

through delay of the ith slave node. All the slave nodes store

the pass-through delays of the preceding nodes, and the master

node stores all the pass-through delays. The master node

calculates the time ttot from transmission to reception of the

synchronization frame.

ttot = tmrx − tm

tx (2)

Next, the master node calculates the average internode delay

tavg =

ttot −

n

∑i=1

thi

n, (3)

where n is the number of slave nodes. The average delay tavg

is sent to the slave nodes. The counters of the slave nodes

are not yet synchronized to the counter of the master node.

However, every slave node has the information of when the

synchronization frame was transmitted by the master and how

long the propagation delays were before the reception of the

synchronization frame. Every slave node calculates total delay

tsidelay from master node transmission to slave node reception.

tsi

delay =

tavg, i = 1

2× tavg + th1, i = 2

3× tavg + th1 + th2, i = 3...

n× tavg +n

∑j=1

th j − thn, i = n

(4)

Now the error of a counter of each slave node tsierror can be

calculated.

tsierror = tm

tx + tsi

delay − tsirx (5)

The counter value of a slave node in the reception of the

synchronization frame should be the same as the transmission

time of the master node added with the propagation delays. If

this is not the case, the counter of a slave must be corrected.

The synchronization sequence is repeated periodically, with

one exception. The internode propagation delay is not calcu-

lated again, assuming that the time stamping points have been

chosen so that there is no significant variation in time stamping

instants. In practice, this means that the time stamping should

be carried out close to the physical layer of the protocol.

If time stamping of messages can be implemented, the

method can be used with different kinds of communication

protocols. The functionality, besides time stamping, can be im-

plemented in higher protocol layers. No custom-made lower-

level communication protocol is needed. The proposed scheme

is designed with goals contrary to the synchronization scheme

used in PESNet. PESNet relies on a custom-made communica-

tion protocol, in which the synchronization is embedded, and

thus no higher-level functionality is needed to achieve the syn-

chronization. The tradeoff is that changes in the propagation

delays require modifications to the communication protocol.

By taking into account the slave node pass-through times,

the communication is less restricted than in PESNet. The

data path does not need to be reserved for the duration of

the synchronization sequence. The nodes can initiate a data

transmission at any time. If a transmitter is busy for a while,

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it is taken into account in the synchronization scheme. This

way, the synchronization sequence can be different from the

operational sequence of the application. The synchronization

sequence messaging does not need to be taken into account

in the application data messaging. The synchronization is

transparent to the application.

The synchronization period has an effect on the synchro-

nization accuracy. The longer the period, the more time the

local clock sources have to drift. Because the synchronization

sequence of the proposed method is transparent to the ap-

plication, the synchronization period can be set regardless of

the application. This ensures that the synchronization accuracy

does not change when the operational cycle of an application

is changed.

III. IMPLEMENTATION AND TESTING

A. Communication protocol

A simple communication protocol for a cascaded ring topol-

ogy was developed and implemented in Field Programmable

Gate Array (FPGA). Data recovery is done in FPGA, and no

dedicated communication ICs are used. An 8B/10B channel

encoding is used, and encoding/decoding blocks provided

by XILINX® are used in the implementation. The channel

encoding used ensures a bit balance of the data stream, and

it can also be used to observe errors in communication. The

frame length is fixed, and it is 60 bits (encoded). The frame

length is parametrized, and can be changed by recompiling the

FPGA design. The 10-bit sequence at the beginning of each

frame indicates the start of a frame.

A block diagram of the communication and synchronization

system is presented in Fig. 3. The receiver performs the data

recovery and deserialization. The Rx control passes on the

data either to the application block, the synchronization block,

or the buffer. The destination is derived from the protocol

information of the data frame, consisting of three fields. One

bit indicates whether the frame was initiated by the master

or a slave node. Three bits indicate the sender/receiver of the

frame. One ID is reserved for multicast addressing. Four bits

indicate the type of the data that the frame contains. At the

current setup, the messaging is restricted so that the frames

initiated by a slave node are automatically addressed to the

master node. No slave to slave messaging is allowed. However,

this scheme can be modified if needed.

The synchronization block handles the messaging of the

synchronization sequence. The Tx control relays data to the

transmitter, when the transmitter is not busy. The First In First

Out (FIFO) buffers are added before the Tx control so that

each source of data can initiate a frame at any time without

conflicts. This way, the messaging scheme can be modified

quite freely, and strict cyclic operation is not necessary. Any

node can initiate a data frame at any time without conflicts

in the messaging scheme. Because the propagation delay of a

synchronization message may vary, this is taken into account

in the synchronization scheme by calculating the node pass-

through delays.

T r a n s m i t t e r R e c e i v e r

S y n c h r o n i z a t i o n

T x c o n t r o l R x c o n t r o l

F I F O F I F O F I F O

A p p l i c a t i o n

Fig. 3. Implementation of the communication and synchronization schemeconsists of a transmitter, a receiver, Tx and Rx controls, a synchronizationblock, and FIFOs.

B. Implementation of the synchronization

The implementation of the synchronization and communica-

tion scheme runs at 100 MHz, which is also the data rate of the

communication. During periodic synchronization sequences,

the errors of the local counters are calculated and corrected.

Since the time stamping and the counters run at 100 MHz,

a unit of the calculated error is 10 ns. The synchronization

sequence is repeated every 100 µs. The synchronization period

is parametrized. The synchronous counter can be used to

schedule the messaging of a node.

The local counter correction value can be used to produce a

slower synchronous clock signal. A 10 MHz adjustable clock

signal is generated in the synchronization block. This clock

signal can be adjusted by 10 ns in every 100 ns clock period.

The adjustment is presented in Fig. 4. The procedure to apply

the correction to the synchronous 10 MHz clock signal is

presented in Fig. 5. This way, the synchronization scheme

can be used to produce a 10 MHz synchronous clock signal,

which can be used as an operational clock of the application.

The drawback is the jitter in the synchronous 10 MHz clock

signal.

a)

b)

c)

Fig. 4. Synchronous 10 MHz clock adjustment. a) Unmodified clock signalb) Clock pulse is lengthened 10 ns c) Clock pulse is shortened by 10 ns.

C. Test setup and results

The test setup consists of three FPGA cards, based on

XILINX® FPGAs. Virtex®-II FPGAs were use in the master

node and Spartan®-3s in the slave nodes.

FPGA control cards were connected to a cascaded ring by

plastic optical cables, as in Fig. 2. The nodes were connected

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start

wait correction

correction=0

Correction

positiveShorten clock pulse Lenghten clock pulse

correction = correction-1 correction = correction+1

no

yes

yes

no

Fig. 5. Correction of the synchronous clock is carried out in 10 ns at a time.If correction is positive, a shorter clock pulse must be generated, and viceversa. Correction value is calculated periodically.

to each other with 10 m cables. The FPGA cards have a 100

MHz oscillator as a local clock source.

The synchronous 10 MHz clock signals, produced by the

synchronization blocks of the slave nodes, were routed to the

external pins on the control cards. These clock signals were

observed with an oscilloscope.

The jitter of 10 MHz clock signals of the two slave nodes is

less than 15 ns, as can be seen in Fig. 6. If the application block

were operated by the synchronous clock signal, this would

also be the jitter of the application. It should be noted that

adding more nodes to the cascaded ring connection reduces

the synchronization accuracy, and thus the presented result is

valid for two slave nodes.

The use of the synchronous clock signal requires that the

clock signals at each node start at the same time. This is

done by first performing the initial synchronization sequence

and starting the synchronous clock signal after that, when all

the nodes are already synchronized. The start of the 10 MHz

clocks of the slave nodes, after the system startup, is presented

in Fig. 7.

Fig. 6. Jitter of the synchronous 10 MHz clock signals of two slave nodes.The time division is 10 ns.

In the propagation delay calculations, the delay between

every two nodes is assumed to be the same, and an average of

these internode delays is calculated. In reality, there is always

some difference, even if the cables are of the same length.

The effect of the internode delay differences was demonstrated

by using cables of different lengths. The master node was

Fig. 7. The start of the generation of synchronous 10 MHz clock signals ofthe slave nodes after the startup. The time division is 40 ns.

connected to the slave nodes by 10 m optical cables. The

slave nodes were connected by a 2 m cable. As can be seen

in Fig. 8, the difference in the internode propagation delays

causes a static error to synchronization. With the example

configuration, the static error is less than 20 ns.

Fig. 8. Synchronous 10 MHz clock signals of the slave nodes. The masternode is connected to the slave nodes by 10 m cables, and the slave nodes areconnected by a 2 m cable. A static error of less than 20 ns can be seen. Thetime division is 20 ns.

D. Discussion of results

The previous sections of this paper have mainly concen-

trated on the synchronization issues of the PEBB systems.

With the proposed synchronization method, synchronization

jitter between two nodes was shown to be less than 15 ns.

With a significant error in the propagation delays, caused by

the cables of different lengths, an additional 20 ns static error

was present. But is this accuracy sufficient or even necessary?

One group of applications, which especially require accurate

synchronization, is high-power converters, which are built

by connecting two or more PEBBs in parallel. The purpose

of paralleling is to increase the reliability and the carrying

capacity of the overall system beyond the ratings of individ-

ual power semiconductor devices. The demand for accurate

synchronization is emphasized when the parallel connection

is established without or with minimal intermodule reactors,

the function of which is to limit the rate of change of currents

during asynchronous switchings [10]. The demonstrations,

presented for example in [11] and [12], have shown that

when the intermodule reactors are not used, switching pattern

differences that are of the size of tens of nanoseconds and

more lead to severe dynamic current imbalances between the

parallel-connected modules.

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Based on the above, the proposed synchronization method

is applicable even to demanding applications, such as systems

that use parallel-connected PEBBs to meet the high-power

requirements. It is, however, worth mentioning that the syn-

chronization error is just one of the causes for asynchronous

switchings. For example, differences in gate driver and power

semiconductor device parameters may cause asynchronous

switchings even if the switching patterns of the parallel-

connected units were accurately synchronized [13]. Despite

this, an accurate synchronization is essential, since it affects

the sizing of the intermodule reactors, and this way helps to

decrease the cost of the overall system [10].

IV. CONCLUSIONS

A time-stamping-based synchronization scheme for a cas-

caded ring topology was proposed. The scheme is based on

time stamping of synchronization messages. The proposed

scheme enables the decoupling of synchronization and appli-

cation periods. This way, the same synchronization accuracy

can be maintained with different application cycles.

A flexible communication scheme for a cascaded ring topol-

ogy was presented. The scheme allows each node to initiate

a frame at any time, without causing conflicts. The proposed

synchronization scheme is applicable to other communication

protocols, if time stamping can be implemented. A jitter less

than 15 ns between two slave nodes was measured. The effect

of differences in the internode propagation delays, causing a

static error to synchronization, was demonstrated.

A building-block-based design can be used in parallel con-

nection of power semiconductors. The parallel connection re-

quires accurate synchronization, which can be a problem with

distributed modules. The proposed synchronization method is

applicable to parallel-connected PEBB systems, although it

should be kept in mind that variations in power semiconductor

parameters can cause asynchronous switching, even if the gate

driver signals were accurately synchronized.

REFERENCES

[1] T. Ericsen, N. Hingorani, and Y. Khersonsky, “Pebb - power electronicsbuilding blocks from concept to reality,” in Petroleum and Chemical

Industry Conference, 2006. Industry Applications Society 53rd Annual,Sept. 11 2006-Oct. 15 2006, pp. 1–7.

[2] G. Francis, R. Burgos, F. Wang, and D. Boroyevich, “A power electronicscommunication protocol for distributed digital control architectures,” inPower and Energy Society General Meeting - Conversion and Delivery

of Electrical Energy in the 21st Century, 2008 IEEE, 20-24 July 2008,pp. 1–8.

[3] L. Hang, Z. Lu, and Z. Qian, “High speed and intelligent communicationtopology dedicated to complex power electronic system integration,” inIndustrial Electronics, 2007. ISIE 2007. IEEE International Symposiumon, 4-7 June 2007, pp. 485–490.

[4] I. Milosavljevic, Z. Ye, D. Boroyevich, and C. Holton, “Analysis ofconverter operation with phase-leg control in daisy-chained or ring-typestructure,” in Power Electronics Specialists Conference, 1999. PESC 99.30th Annual IEEE, vol. 2, 27 June-1 July 1999, pp. 1216–1221vol.2.

[5] I. Milosavljevic, “Power electronics system communications,” Master’sthesis, Virginia Polytechnic Institute and State University, Blacksburg,VA, USA, 1999.

[6] I. Celanovic, N. Celanovic, I. Milosavljevic, D. Boroyevich, and R. Coo-ley, “A new control architecture for future distributed power electronicssystems,” in Power Electronics Specialists Conference, 2000. PESC 00.2000 IEEE 31st Annual, vol. 1, 18-23 June 2000, pp. 113–118vol.1.

[7] J. du Toit, A. le Roux, and J. Enslin, “An integrated controller module fordistributed control of power electronics,” in Applied Power ElectronicsConference and Exposition, 1998. APEC ’98. Conference Proceedings

1998., Thirteenth Annual, vol. 2, 15-19 Feb. 1998, pp. 874–880vol.2.[8] G. Francis, “A synchronous distributed digital control architecture for

high power converters,” Master’s thesis, Virginia Polytechnic Instituteand State University, Blacksburg, VA, USA, 2004.

[9] D. Mohl, IEEE1588-Precise Time Synchronization as the Basis

for Real Time Applications in Automation. [Online]. Available:http://www.industrialnetworking.com/White-Papers

[10] B. Shi and G. Venkataramanan, “Parallel operation of voltage sourceinverters with minimal intermodule reactors,” in Industry Applications

Conference, 2004. 39th IAS Annual Meeting. Conference Record of the2004 IEEE, vol. 1, Oct. 2004, pp. –162.

[11] K. F. Hoffmann and J. P. Kärst, “Inductive decoupling of parallelconnected commutation cells for dynamic current balancing,” in Power

Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35thAnnual, vol. 5, June 2004, pp. 3978–3983 Vol.5.

[12] T. Itkonen, K. Rauma, H. Saren, O. Laakkonen, O. Pyrhonen, andP. Silventoinen, “Parallel connected voltage source inverters withoutintermodule reactors,” in Power Electronics and Motion Control Confer-

ence, 2006. EPE-PEMC 2006. 12th International, Aug. 30 2006-Sept.1 2006, pp. 641–646.

[13] P. Hofer-Noser and N. Karrer, “Monitoring of paralleled IGBT/diodemodules,” Power Electronics, IEEE Transactions on, vol. 14, no. 3, pp.438–444, May 1999.

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