POE-165S IEEE 802.3af/at to Passive PoE Power Converter (12V/19V/24V)
IEEE 802.3af PD Interface and PWM Controllers with ...integrate a complete power IC solution for...
Transcript of IEEE 802.3af PD Interface and PWM Controllers with ...integrate a complete power IC solution for...
General DescriptionThe MAX5953A/MAX5953B/MAX5953C/MAX5953Dintegrate a complete power IC solution for PoweredDevices (PD) in a Power-Over-Ethernet (PoE) system, incompliance with the IEEE 802.3af standard. TheMAX5953A/MAX5953B/MAX5953C/MAX5953D providethe PD with a detection signature, a classification sig-nature, and an integrated isolation switch with program-mable inrush current control. These devices alsointegrate a voltage-mode PWM controller with twopower MOSFETs connected in a two-switch voltage-clamped DC-DC converter configuration.
An integrated MOSFET provides PD isolation duringdetection and classification. All devices guarantee aleakage current offset of less than 10µA during thedetection phase. A programmable current limit pre-vents high inrush current during power-on. The devicesfeature power-mode undervoltage lockout (UVLO) withwide hysteresis and long deglitch time to compensatefor twisted-pair-cable resistive drop and to assureglitch-free transition between detection, classification,and power-on/-off phases. The MAX5953A/MAX5953Chave an adjustable UVLO threshold with the defaultvalue compliant to the 802.3af standard, while theMAX5953B/MAX5953D have a lower and fixed UVLOthreshold compatible with some legacy pre-802.3afpower-sourcing equipment (PSE) devices.
The DC-DC converters are operable in either forward orflyback configurations with a wide input voltage rangefrom 11V to 76V and up to 15W of output power. Thevoltage-clamped power topology enables full recoveryof stored magnetizing and leakage inductive energy forenhanced efficiency and reliability. When using thehigh-side MOSFET, the controller can be configured asa buck converter. A look-ahead signal for driving sec-ondary-side synchronous rectifiers can be used toincrease efficiency. A wide array of protection featuresinclude UVLO, over-temperature shutdown, and short-circuit protection with hiccup current limit for enhancedperformance and reliability. Operation up to 500kHzallows for smaller external magnetics and capacitors.
The MAX5953A/MAX5953B/MAX5953C/MAX5953D areavailable in a high-power (2.22W), 7mm x 7mm ther-mally enhanced thin QFN package.
Features♦ Powered Device Interface
Fully Integrated IEEE 802.3af-Compliant PD Interface
PD Detection and Programmable ClassificationSignatures
Less than 10µA Leakage Current Offset During Detection
Integrated MOSFET for Isolation and Inrush Current Limiting
Gate Output Allows External Control of the Internal Isolation MOSFET
Programmable Inrush Current ControlProgrammable Undervoltage Lockout
(MAX5953A/MAX5953C)♦ DC-DC Converter
Clamped, Two-Switch Power IC for HighEfficiency
Integrated High-Voltage 0.4Ω Power MOSFETsUp to 15W Output Power
Bias Voltage Regulator with Automatic High-Voltage Supply Turn-Off
11V to 76V Wide Input Voltage RangeFeed-Forward Voltage-Mode Control for Fast
Input Transient RejectionProgrammable Undervoltage LockoutOvertemperature Shutdown Indefinite Short-Circuit Protection with
Programmable Fault IntegrationIntegrated Look-Ahead Signal for Secondary-
Side Synchronous Rectification> 90% Efficiency with Synchronous
RectificationUp to 500kHz Switching Frequency
♦ High-Power (2.22W), 7mm x 7mm ThermallyEnhanced Lead-Free Thin QFN Package
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________________________________________________________________ Maxim Integrated Products 1
PART PIN-PACKAGE PKG CODE
MAX5953AUTM+ 48 TQFN T4877-6
MAX5953BUTM+ 48 TQFN T4877-6
MAX5953CUTM+ 48 TQFN T4877-6
MAX5953DUTM+ 48 TQFN T4877-6
Ordering Information
19-3945; Rev 1; 7/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Operating junction temperature range is 0°C to +125°C.+Denotes lead-free package.
Pin Configuration and Typical Operating Circuit appear atend of data sheet.
IEEE 802.3af PoweredDevices
IP Phones
Wireless Access Nodes
Internet Appliances
Security Cameras
Computer Telephony
Applications
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VIN = (V+ - VEE) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = VEE, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.
V+ to VEE ................................................................-0.3V to +90VOUT, PGOOD, PGOOD to VEE.....................-0.3V to (V+ + 0.3V)RCLASS, GATE to VEE ...........................................-0.3V to +12VUVLO to VEE ............................................................ -0.3V to +8VPGOOD to OUT ........................................... -0.3V to (V+ + 0.3V)HVIN, INBIAS, DRNH, XFRMRH,
XFRMRL to GND.................................................-0.3V to +80VBST to GND........................................................... -0.3V to +95VBST to XFRMRH .................................................... -0.3V to +12VPGND to GND .......................................................-0.3V to +0.3VDCUVLO, RAMP, CSS, OPTO, FLTINT, RCFF,
RTCT to GND..................................................... -0.3V to +12VSRC, CS to GND...................................................... -0.3V to +6VREGOUT, DRVIN to GND.......................................-0.3V to +12VREGOUT to HVIN .................................................. -80V to +0.3VREGOUT to INBIAS ............................................... -80V to +0.3VPPWM to GND....................................-0.3V to (VREGOUT + 0.3V)
Maximum Input/Output Current (Continuous)OUT to VEE....................................................................500mAV+, RCLASS to VEE.........................................................70mAUVLO, PGOOD, PGOOD to VEE .....................................20mAGATE to VEE....................................................................80mAREGOUT to GND ............................................................50mADRNH, XFRMRH, XFRMRL, SRC to GND (Average),
TJ = +125°C..................................................................0.9APPWM to GND ..............................................................±20mA
Continuous Power Dissipation* (TA = +70°C)48-Pin TQFN 7mm X 7mm(derate 27.8mW/°C above +70°C).............................2222mWθJA ................................................................................36°C/W
Operating Ambient Temperature Range ................0°C to +85°COperating Junction Temperature Range ..............0°C to +125°CJunction Temperature ......................................................+150°CStorage Temperature Range .............................-60°C to +150°CLead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWERED DEVICE (PD) INTERFACE
DETECTION MODE
Input Offset Current IOFFSET VIN = 1.4V to 10.1V (Note 2) 10 µA
Effective Differential InputResistance (Note 3)
dR VIN = 1.4V, up to 10.1V with 1V step 550 kΩ
CLASSIFICATION MODE
Classification Current Turn-OffThreshold
VTH,CLASS VIN rising (Note 4) 20.8 21.8 22.5 V
Class 0, RRCLASS = 10kΩ 0 2
Class 1, RRCLASS = 732Ω 9.17 11.83
Class 2, RRCLASS = 392Ω 17.29 19.71
Class 3, RRCLASS = 255Ω 26.45 29.55
Classification Current ICLASS
VIN = 12.6Vto 20V,RDISC =25.5kΩ(Notes 5, 6)
Class 4, RRCLASS = 178Ω 36.6 41.4
mA
POWER MODE
Operating Supply Voltage VIN VIN = (V+ - VEE) 67 V
Operating Supply Current IINMeasure at V+, not including RDISC,GATE = VEE, HVIN = GND = OUT
0.4 1 mA
MAX5953A/MAX5953C 37.4 38.6 40.2Default Power Turn-On Voltage VUVLO, ON
VINincreasing MAX5953B/MAX5953D 34.3 35.4 36.9
V
Default Power Turn-Off Voltage VUVLO,OFF VIN decreasing, MAX5953A/MAX5953C 30 V
*As per JEDEC 51 standard.
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ELECTRICAL CHARACTERISTICS (continued)(VIN = (V+ - VEE) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = VEE, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5953A/MAX5953C 7.1Default Power Turn-On/OffHysteresis Voltage
VHYST,UVLOMAX5953B/MAX5953D 4
V
External UVLO ProgrammingRange
VIN,EX MAX5953A/MAX5953C only (Note 7) 12 67 V
UVLO External ReferenceVoltage
VREF,UVLO VUVLO increasing 2.400 2.460 2.522 V
UVLO External ReferenceVoltage Hysteresis
VHYST,UVLO Ratio to VREF, UVLO 19.2 20 20.9 %
UVLO Bias Current IIN,UVLO VUVLO = 2.460V -1.5 +1.5 µA
UVLO Input Ground-SenseThreshold
VTH,G,UVLO (Note 8) 50 440 mV
UVLO Input Ground-Sense GlitchRejection
7 µs
Power Turn-Off Voltage,Undervoltage Lockout DeglitchTime
tOFF_DLY VIN, VUVLO falling (Note 9) 0.32 ms
Isolation Switch n-ChannelMOSFET On-Resistance
RON,ISOOutput current = 300mA, VGATE = 5.6V,measured between OUT and VEE
0.6 1.5 Ω
Isolation Switch n-ChannelMOSFET Off-Threshold Voltage
VGSTHVGATE - VEE, OUT = V+,output current < 1µA
0.5 V
GATE Pulldown SwitchResistance
RG Power-off mode, VIN = +12V 38 80 Ω
GATE Charging Current IGATE VGATE = 2V 4.5 10 16.5 µA
GATE High Voltage VGATE IGATE = 1µA 5.59 5.76 5.93 V
VOUT - VEE decreasing, VGATE = 5.75V 1.16 1.23 1.31 VPGOOD Assertion VOUTThreshold (Note 10)
VOUTENHysteresis 70 mV
VGATE - VEE increasing 4.62 4.76 4.91 VPGOOD, PGOOD AssertionVGATE Threshold
VGSENHysteresis 80 mV
PGOOD, PGOOD Output LowVoltage
VOL,PGOOD ISINK = 2mA, VOUT ≤ (V+ - 5V) (Note 11) 0.2 V
PGOOD Leakage Current GATE = high, V+ - VOUT = 67V (Note 11) 1 µA
PGOOD Leakage CurrentGATE = VEE, PGOOD - VEE = 67V(Note 11)
1 µA
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ELECTRICAL CHARACTERISTICS (DC-DC Controller)(All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT =100pF, CBST = 0.22µF, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0°C to +125°C, unless otherwise noted. Typical values are atTJ = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Supply Range VHVIN 11 76 V
OSCILLATOR (RTCT)
PWM Frequency fS 250 kHz
Maximum PWM Duty Cycle DMAX 47 %
Maximum RTCT Frequency fRTCTMAX (Note 12) 1 MHz
RTCT Peak Trip Level VTH,RTCT 0.51 x VREGOUT V
RTCT Valley Trip Level VTL,RTCT 1 V
RTCT Input Bias Current IIN,RTCT ±1 µA
RTCT Discharge MOSFETRDS(ON)
RDIS,RTCT Sinking 50mA 35 85 Ω
RTCT Discharge Pulse Width 50 ns
LOOK-AHEAD LOGIC (PPWM)
PPWM to Output PropagationDelay
tPPWM VPPWM rising to VXFRMRL falling 110 ns
PPWM Output High VOH,PPWM Sourcing 2mA 7.0 11.0 V
PPWM Output Low VOL,PPWM Sinking 2mA 0.2 V
PWM COMPARATOR (OPTO, RAMP, RCFF)
Common-Mode Input Range VCM_PWM 0 5.5 V
Input Offset Voltage 10 mV
Input Bias Current -2 +2 µA
RAMP to XFRMRL PropagationDelay
tCOMPARATORFrom VRAMP (50mV overdrive) rising toVXFRMRL rising
100 ns
Minimum OPTO Voltage VCSS = 0V, OPTO sinking 2mA 1.47 V
Minimum RCFF Voltage RCFF sinking 2mA 2.18 V
REGOUT LDO (REGOUT)
INBIAS unconnected,VHVIN = 11V to 76V
8.3 8.75 9.2REGOUT Voltage Set Point VREGOUT
VINBIAS = VHVIN = 11V to 76V 9.5 10.6 11.0
V
INBIAS unconnected, VHVIN = 15V,IREGOUT = 0 to 30mA
0.25
REGOUT Load RegulationVINBIAS = VHVIN = 15V,IREGOUT = 0 to 30mA
0.25
V
INBIAS unconnected, IREGOUT = 30mA 1.25REGOUT Dropout Voltage
VINBIAS = VHVIN, IREGOUT = 30mA 1.25V
REGOUT UndervoltageLockout Threshold
REGOUT rising 6.6 7.0 7.4 V
REGOUT UndervoltageLockout Threshold Hysteresis
REGOUT falling 0.7 V
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ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)(All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT =100pF, CBST = 0.22µF, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0°C to +125°C, unless otherwise noted. Typical values are atTJ = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SOFT-START (CSS)
Soft-Start Current ICSS VCSS = 0V 33 µA
INTEGRATING FAULT PROTECTION
FLTINT Source Current IFLTINT 80 µA
FLTINT Trip Point VFLTINT rising 2.7 V
FLTINT Hysteresis 0.75 V
INTERNAL POWER FETs
On-Resistance RON,POWERVDRVIN = VBST = 9V,VXFRMRH = VSRC = 0V, IDS = 50mA
0.4 0.8 Ω
Off-State Leakage Current -5 +10 µA
Total Gate Charge Per PowerFET
15 nC
HIGH-SIDE DRIVER
Low to High Latency tLH-HSDriver delay until FET VGS reaches 0.9 x(VBST - VXFRMRH) and is fully on
80 ns
High to Low Latency tHL-HSDriver delay until FET VGS reaches 0.1 x(VBST - VXFRMRH) and is fully off
40 ns
Output Drive Voltage VBST BST to XFRMRH with high side on 8 V
LOW-SIDE DRIVER
Low to High Latency tLH-LSDriver delay until FET VGS reaches 0.9 xVDRVIN and is fully on
80 ns
High to Low Latency tHL-LSDriver delay until FET VGS reaches 0.1 xVDRVIN and is fully off
40 ns
CURRENT-LIMIT COMPARATOR (CS)
Current-Limit ThresholdVoltage
VILIM 140 156 172 mV
Current-Limit Input BiasCurrent
IBILIM 0 < VCS < 0.3V -2 +2 µA
Propagation Delay to XFRMRL tdILIMFrom VCS rising (10mV overdrive) toVXFRMRL rising
160 ns
BOOST VOLTAGE CIRCUIT (See Figure 9, QB)
Driver Output Delay tPPWMD 200 ns
One-Shot Pulse Width tPWQB 300 ns
QB RDSON Sinking 20mA 30 60 ΩTHERMAL SHUTDOWN
Shutdown Temperature TSH Temperature rising +160 °C
Thermal Hysteresis TH 20 °C
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ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)(All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT =100pF, CBST = 0.22µF, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0°C to +125°C, unless otherwise noted. Typical values are atTJ = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
UNDERVOLTAGE LOCKOUT (DCUVLO)
Threshold Voltage VREF,DCUVLO VDCUVLO rising 1.14 1.26 1.38 V
Hysteresis VHYS,DCUVLO 140 mV
Input Bias Current IIN,DCUVLO VDCUVLO = 3V -100 +100 nA
SUPPLY CURRENT
From VHVIN = 11V to 76V,VCSS = 0V, VINBIAS = 11V
0.7 1.5
From VINBIAS = 11V to 76V,VCSS = 0V, VHVIN = 76V
4.4 6.4Supply Current
From VHVIN = 76V, VOPIO = 4V 7
mA
Standby Supply Current VDCUVLO = 0V 1 mA
Note 1: Limits at 0°C are guaranteed by design, unless otherwise noted.Note 2: The input offset current is illustrated in Figure 1.Note 3: Effective differential input resistance is defined as the differential resistance between V+ and VEE without any external
resistance.Note 4: Classification current is turned off whenever the IC is in power mode.Note 5: See Table 2 in the Classification Mode section. RDISC and RRCLASS must be 1%, 100ppm or better. ICLASS includes the IC
bias current and the current drawn by RDISC.Note 6: See the Thermal Dissipation section.Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on UVLO doesnot exceed its maximum rating of 8V when VIN is at the maximum voltage.
Note 8: When VUVLO is below VTH,G,UVLO, the MAX5953A/MAX5953C set the turn-on voltage threshold internally (VUVLO,ON).Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the
MAX5953A/MAX5953B/MAX5953C/MAX5953D to exit power-on mode (as long as the input voltage remains above anoperable voltage level of 12V).
Note 10: Guaranteed by design, not tested in production for MAX5953B/MAX5953D.Note 11: PGOOD references to OUT while PGOOD references to VEE.Note 12: Output switching frequency is 1/2 oscillator frequency.
Figure 1. Effective Differential Input Resistance/Offset Current
IIN
IINi + 1
IINi
IOFFSET
dRi
1VVINi VINi + 1
IOFFSET ≅ IINi - VINi
dRi
dRi ≅ (VINi + 1 - VINi)
= 1V
(IINi + 1 - IINi)
(IINi + 1 - IINi)
VIN
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DETECTION CURRENTvs. INPUT VOLTAGE
MAX
5953
A/B/
C/D
toc0
1
INPUT VOLTAGE (V)
DETE
CTIO
N CU
RREN
T (m
A)
8642
0.1
0.2
0.3
0.4
0.5
00 10
RDISC = 25.5kΩ
IIN + IRDISC
CLASSIFICATION CURRENTvs. INPUT VOLTAGE
MAX
5953
A/B/
C/D
toc0
2
INPUT VOLTAGE (V)
CLAS
SIFI
CATI
ON C
URRE
NT (m
A)
252015105
5
10
15
20
25
30
35
40
45
50
00 30
CLASS 4
CLASS 3
CLASS 2
CLASS 1
CLASS 0
EFFECTIVE DIFFERENTIAL INPUTRESISTANCE vs. INPUT CURRENT
MAX
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A/B/
C/D
toc0
3
INPUT VOLTAGE (V)
EFFE
CTIV
E DI
FFER
ENTI
AL IN
PUT
RESI
STAN
CE (M
Ω)
8642
0.5
1.0
1.5
2.0
2.5
3.0
3.5
00 10
INPUT OFFSET CURRENTvs. INPUT VOLTAGE
MAX
5953
A/B/
C/D
toc0
4
INPUT VOLTAGE (V)
INPU
T OF
FSET
CUR
RENT
(µA)
862 4
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
-4.00 10
NORMALIZED UVLOvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc0
5
TEMPERATURE (°C)
NORM
ALIZ
ED U
VLO
100755025
0.992
0.994
0.996
0.998
1.000
1.002
1.004
1.006
1.008
1.010
0.9900 125
PGOOD OUTPUT LOW VOLTAGEvs. CURRENT
MAX
5953
A/B/
C/D
toc0
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ISINK (mA)
V PGO
OD (m
V)
15105
50
100
150
200
250
00 20
OUT LEAKAGE CURRENTvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc0
7
TEMPERATURE (°C)
OUT
LEAK
AGE
CURR
ENT
(nA)
100755025
1
10
100
1000
0.10 125
VOUT = 48V
INRUSH CURRENT CONTROL(VIN = 48V)
MAX5953A/B/C/D toc08
4ms/div
VOUT TOVEE
50V/div
VGATE5V/div
0V
0V
0A
0V
IINRUSH100mA/div
PGOOD50V/div
DCUVLO THRESHOLDvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc0
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TEMPERATURE (°C)
V DCU
VLO
(V)
100755025
1.2750
1.2775
1.2800
1.2825
1.27250 125
DCUVLO RISING
Typical Operating Characteristics(VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = VEE, CINBIAS = 1µF,CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, TJ = 0°C to +125°C, unless otherwise noted. Typical values areat TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.)
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Typical Operating Characteristics (continued)(VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = VEE, CINBIAS = 1µF,CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, TJ = 0°C to +125°C, unless otherwise noted. Typical values areat TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.)
HVIN STANDBY CURRENTvs. TEMPERATURE
MAX
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A/B/
C/D
toc1
0
TEMPERATURE (°C)
STAN
DBY
CURR
ENT
(µA)
100755025
35
70
105
140
175
210
245
280
315
350
385
00 125
fHVINVDCUVLO = 0V
HVIN INPUT CURRENTvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc1
1
TEMPERATURE (°C)
I HVI
N (m
A)
1007525 50
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.00 125
INBIAS FLOATINGVHVIN = 76VREGOUT = DRVIN
HVIN AND INBIAS INPUT CURRENTvs. TEMPERATURE
MAX
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A/B/
C/D
toc1
2
TEMPERATURE (°C)
INPU
T CU
RREN
T (m
A)
100755025
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
00 125
IINBIAS
IHVIN
VHVIN = VINBIAS = 76V
REGOUT VOLTAGEvs. INPUT VOLTAGE
MAX
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A/B/
C/D
toc1
3
VHIN (V)
V REG
OUT (
V)
63503724
8.76
8.77
8.78
8.79
8.80
8.81
8.82
8.83
8.84
8.85
8.7511 76
INBIAS FLOATINGGND = VEE
REGOUT VOLTAGEvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc1
4
TEMPERATURE (°C)
V REG
OUT (
V)
100755025
8.72
8.74
8.76
8.78
8.80
8.82
8.84
8.86
8.88
8.90
8.700 125
VHVIN = 48VINBIAS FLOATING
REGOUT VOLTAGEvs. LOAD CURRENT
MAX
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A/B/
C/D
toc1
5
IREGOUT (mA)
V REG
OUT (
V)
252015105
8.70
8.75
8.80
8.85
8.650 30
VHVIN = 15VINBIAS FLOATINGGND = VEE
REGOUT VOLTAGEvs. INPUT VOLTAGE
MAX
5953
A/B/
C/D
toc1
6
VHIN (V)
V REG
OUT (
V)
63503724
10.62
10.64
10.66
10.68
10.70
10.6011 76
HVIN = INBIASGND = VEE
REGOUT VOLTAGEvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc1
7
TEMPERATURE (°C)
V REG
OUT (
V)
100755025
10.66
10.67
10.68
10.69
10.70
10.71
10.72
10.73
10.74
10.75
10.650 125
VHVIN = VINBIAS = 48V
REGOUT VOLTAGEvs. LOAD CURRENT
MAX
5953
A/B/
C/D
toc1
8
IREGOUT (mA)
V REG
OUT (
V)
252015105
10.55
10.60
10.65
10.70
10.75
10.500 30
VHVIN = VINBIAS = 15VGND = VEE
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
_______________________________________________________________________________________ 9
REGOUT UVLO VOLTAGE vs. TEMPERATURE
MAX
5953
A/B/
C/D
toc1
9
TEMPERATURE (°C)
REGO
UT U
VLO
VOLT
AGE
(V)
100755025
6.2
6.4
6.6
6.8
7.0
7.2
7.4
6.00 125
RISING
FALLING
OPERATING FREQUENCYvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc2
0
TEMPERATURE (°C)
OPER
ATIN
G FR
EQUE
NCY
(kHz
)
1007525 50
250
300
350
400
450
500
550
600
2000 125
RRTCT = 12kΩCRTCT = 100pF
RRTCT = 24.3kΩCRTCT = 100pF
SOFT-START CURRENTvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc2
1
TEMPERATURE (°C)
SOFT
-STA
RT C
URRE
NT (µ
A)
100755025
31.5
32.0
32.5
33.0
33.5
34.0
31.00 125
MINIMUM RCFF AND OPTO LEVELSvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc2
2
TEMPERATURE (°C)
V RCF
F (V)
, VOP
TO (V
)
100755025
1.25
1.50
1.75
2.00
2.25
2.50
2.75
1.000 125
RCFF
OPTO
CURRENT-LIMIT COMPARATORTHRESHOLD vs. TEMPERATURE
MAX
5953
A/B/
C/D
toc2
3
TEMPERATURE (°C)
V REG
OUT (
V)
100755025
0.151
0.152
0.153
0.154
0.155
0.156
0.157
0.158
0.159
0.160
0.1500 125
HVIN RISING
PPWM TO XFRMRL SKEWvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc2
4
TEMPERATURE (°C)
PPW
M T
O XF
RMRL
SKE
W (n
s)
100755025
91
92
93
94
95
96
97
98
99
100
900 125
FLTINT CURRENTvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc2
5
TEMPERATURE (°C)
I FLTI
NT (µ
A)
100755025
76
77
78
79
80
81
82
83
84
85
750 125
FLTINT SHUTDOWN VOLTAGEvs. TEMPERATURE
MAX
5953
A/B/
C/D
toc2
6
TEMPERATURE (°C)
V FLT
INT (
V)
100755025
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
1.90 125
RISING
FALLING
POWER MOSFETS RDS(ON)vs. TEMPERATURE
MAX
5953
A/B/
C/D
toc2
7
TEMPERATURE (°C)
R DS(
ON) (
Ω)
100755025
0.1
0.2
0.3
0.4
0.5
0.6
0.7
00 125
Typical Operating Characteristics (continued)(VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = VEE, CINBIAS = 1µF,CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, TJ = 0°C to +125°C, unless otherwise noted. Typical values areat TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.)
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10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 2, 3, 5, 7, 12, 13, 14, 17,19, 35, 38, 46, 47, 48
N.C. No Connection. Not internally connected. Make no electrical connection to these pins.
4 V+ Positive Input Power. Referenced to VEE.
6 (MAX5953A/MAX5953C)
UVLO
Undervoltage Lockout Programming Input for PD Interface. UVLO is referenced to VEE.When UVLO is above its threshold, the device enters the power mode. Connect UVLO toVEE to use the default undervoltage lockout threshold. Connect UVLO to the center of anexternal resistor-divider between V+ and VEE to define a threshold externally. The seriesresistance value of the external resistors must add to 25.5kΩ (±1%) and replaces thedetection resistor. To keep the device in undervoltage lockout, drive UVLO betweenVTH,G,UVLO and VREF,UVLO.
6 (MAX5953B/MAX5953D)
N.C. No Connection. Not internally connected. Make no electrical connection to this pin.
8 RCLASSClassification Setting for PD Interface. RCLASS is referenced to VEE. Add a resistor fromRCLASS to VEE to set a PD class (see Tables 1 and 2).
9 GATE
Gate of Internal Isolation n-Channel Power MOSFET. GATE is referenced to VEE. GATEsources 10µA when the device enters power mode. Connect an external 100V ceramiccapacitor from GATE to OUT to program the inrush current. Drive GATE to VEE to turn offthe internal MOSFET. The detection and classification functions operate normally whenGATE is driven to VEE.
10, 11 VEE Negative Input Power. Source of the integrated isolation n-channel power MOSFET.
15, 16 OUTOutput Voltage. OUT is referenced to VEE. OUT is connected to the drain of the integratedisolation n-channel power MOSFET. Connect OUT to GND.
18(MAX5953A/MAX5953B)
PGOOD
Active-High, Open-Drain Power-Good Indicator Output for PD Interface. PGOOD isreferenced to OUT. PGOOD goes high impedance when VOUT is within 1.2V of VEE andwhen VGATE is 5V above VEE. Otherwise, PGOOD is internally pulled to OUT (given thatVOUT is at least 5V below V+). PGOOD can be connected directly to CSS or DCUVLO toenable/disable the DC-DC converter.
18(MAX5953C/MAX5953D)
PGOODActive-Low, Open-Drain Power-Good Indicator Output for PD Interface. PGOOD isreferenced to VEE. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and whenVGATE is 5V above VEE. Otherwise, PGOOD goes high impedance.
20 CSCurrent-Sense Input for PWM Controller. CS is referenced to PGND. The current-limitthreshold is internally set to 156mV relative to PGND. The device has an internal noise filter.If necessary, connect an external RC filter from CS to PGND for additional filtering.
21 PPWMPWM Pulse Output. Referenced to GND. PPWM leads the internal power MOSFET pulse byapproximately 100ns.
22 GND Signal Ground of PWM Controller. Connect GND to PGND.
23 PGND Power Ground of the DC-DC Converter Power Stage. Connect PGND to GND.
24 CSSSoft-Start Timing Capacitor Connection for PWM Controller. CSS is referenced to GND.Connect a 0.01µF or greater ceramic capacitor from CSS to GND. Connect to PGOOD toautomatically enable the PWM controller from the PD interface.
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
______________________________________________________________________________________ 11
Pin Description (continued)
PIN NAME FUNCTION
25 OPTOPWM Comparator Inverting Input. OPTO is referenced to GND. Connect the collector of theoptotransistor to OPTO and a pullup resistor to REGOUT.
26, 27 SRCSource Connection of Low-Side Power MOSFET in the Two-Switch Power Stage of the DC-DC Converter. Connect SRC to PGND with a low-value resistor for current limiting.
28, 29 XFRMRLLow-Side Connection for the Isolation Transformer. Drain terminal of low-side powerMOSFET in the two-switch power stage of the DC-DC converter.
30 DRVINSupply Input for the Gate-Driver of Internal Power MOSFETs. DRVIN is referenced toPGND. Bypass DRVIN with at least 0.1µF to PGND. Connect DRVIN to REGOUT.
31, 32 XFRMRHHigh-Side Connection for the Isolation Transformer. Source connection of high-side powerMOSFET in the two-switch power stage of the DC-DC converter.
33, 34 DRNHDrain Connection of High-Side MOSFET in the Two-Switch Power Stage of the DC-DCConverter. Connect DRNH to the most positive rail of the input supply. Bypass DRNHappropriately to handle the heavy switching current through the transformer.
36 BSTBoost Input for the DC-DC Converter. BST is the boost connection point for the high-sideMOSFET driver. Connect a minimum 0.1µF capacitor from BST to XFRMRH with short andwide PC board traces.
37 DCUVLODC-DC Converter Undervoltage Lockout Input. DCUVLO is referenced to GND. Connect aresistor-divider from HVIN to DCUVLO to GND to set the UVLO threshold.
39 HVINDC-DC Converter Positive Input Power Supply. HVIN is referenced to GND. Connect HVINto V+.
40 INBIASInput from the Rectified Bias Winding to the DC-DC Converter. INBIAS is referenced toGND. INBIAS is the input to the internal linear voltage regulator (REGOUT).
41 REGOUT
Internal Regulator Output. REGOUT is used for the DC-DC converter gate driver. REGOUTis referenced to GND. VREGOUT is always present as long as HVIN is powered with avoltage above the DCUVLO threshold. Bypass REGOUT to GND with a minimum 2.2µFceramic capacitor.
42 RTCTOscillator Frequency Set Input for the PWM Controller. RTCT is referenced to GND.Connect a resistor from RTCT to REGOUT and a ceramic capacitor from RTCT to GND toset the oscillator frequency.
43 FLTINT
Fault Integration Input for PWM Controller. FLTINT is referenced to GND. During persistentcurrent-limit faults, a capacitor connected to FLTINT is charged with an internal 80µAcurrent source. Switching is terminated when VFLTINT reaches 2.7V. An external resistorconnected in parallel discharges the capacitor. Switching resumes when VFLTINT dropsto 1.9V.
44 RCFFFeed-Forward Input for PWM Controller. RCFF is referenced to GND. To generate the PWMramp, connect a resistor from RCFF to HVIN and a capacitor from RCFF to GND.
45 RAMP Ramp Sense Input for PWM Controller. Connect RAMP to RCFF.
— EPExposed Paddle. EP is internally unconnected and must be connected to VEE externally.To improve power dissipation, solder the exposed paddle to a copper pad on the PCboard.
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
12 ______________________________________________________________________________________
Typical Application Circuit
PHY
-48V
-48VRTN
Tx
Rx
SGNDRJ-45
POWER-OVERSPAIR PAIRS
3
61
2
4
5
7
8
POWER-OVERSIGNAL PAIRS
+
-
+
-
VREG
Figure 2. RJ-45 Connector, PoE Magnetic, and Input Diode Bridges
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
______________________________________________________________________________________ 13
PGOO
D
V+ UVLO
R1*
OPEN
R3(R
DISC
)25
.5kΩ
C222
µF 63V
R520
0kΩ C3
220p
F
C44.
7µF
C568
00pF
R624
.9kΩ
R71.
78kΩ
*R1
AND
R2 A
RE O
PTIO
NAL
AND
WHE
N US
ED, T
HEY
MUS
T TO
TAL
25.5
kΩ A
ND R
EPLA
CE R
3, 2
5.5k
Ω.
C168
nFD1 60
V-48V
RTN
-48V
R2*
OPEN
R4(R
RCLA
SS)
255Ω
4 6 8RC
LASS
18
DCUV
LO
37
R16
316k
ΩR1
714
.7kΩ
HVIN
39
DRNH
PPW
M BST
C11
0.1µ
FD2
D3C1
2A47
µF
33, 3
421
36
XFRM
RH31
, 32
XFRM
RL28
, 29
INBI
AS40
R13
15Ω
D6
V EE
10
RCFF
44
RAM
P45
DRVI
N30
GATE
9
OUT
16
REGO
UT
FLTI
NT
4342
24
RTCT
CSS
22GND
25 OP
TO
41
C60.
1µF
C7 100p
FR9 1M
Ω
C8 0.1µ
F
23 PG
ND
PGND
E
U2FO
D271
2
C
LED FB
GND
COM
P
20
CS
26, 2
7SRC
C922
0pF
R10
100Ω
R11
0.1Ω
R8 OPEN
C10
0.33
µF R12
604Ω
R16
562Ω
C16
0.15
µF
C17
0.04
7µF
R15
16.2
kΩ
R14
143k
Ω
D4
22T
25T
11T
C15
1µF
C12B
47µF
C13
0.1µ
F
OUT
SGND
C14
0.00
47µF
MAX
5953
A
Figure 3. Typical Application Circuit
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
14 ______________________________________________________________________________________
PGOO
D
V+ UVLO
R1*
R3(R
DISC
)25
.5kΩ
C168
nFD1 60
V-48V
RTN
-48V
R2*
R RCL
ASS
4 6 8RC
LASS
18
DCUV
LO
37
HVIN
39
DRNH
PPW
M BST
33, 3
421
36
XFRM
RH31
, 32
XFRM
RL28
, 29
INBI
AS40
V EE
10
RCFF
44
RAM
P45
DRVI
N30
GATE
9
OUT
16
REGO
UT
FLTI
NT
4342
24
RTCT
CSS
22GND
25 OP
TO
41
23 PG
ND
PGND
E
U2FO
D271
2
C
LED FB
GND
COM
P
20
CS
26, 2
7SRC
V OUT
SGND
MAX
5953
A
*R1
AND
R2 A
RE O
PTIO
NAL
AND
WHE
N US
ED, T
HEY
MUS
T TO
TAL
25.5
kΩ A
ND R
EPLA
CE R
3, 2
5.5k
Ω.
Figure 4. For higher power applications, the MAX5953A/MAX5953B/MAX5953C/MAX5953D can be used in a two-switch forwardconverter configuration
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
______________________________________________________________________________________ 15
Detailed DescriptionPD Interface
The MAX5953A/MAX5953B/MAX5953C/MAX5953Dinclude complete interface function for a PD to complywith the IEEE 802.3af standard in a PoE system. Theyprovide the PD with a detection signature, a classifica-tion signature, and an integrated isolation switch withprogrammable inrush current control. An integratedMOSFET provides PD isolation during detection andclassification. All devices guarantee a leakage currentoffset of less than 10µA during the detection phase. Aprogrammable current limit prevents high inrush cur-rent during power-on. The device features power-modeUVLO with wide hysteresis and long deglitch time tocompensate for twisted-pair-cable resistive drop and toassure glitch-free transition between detection, classifi-cation, and power-on/-off phases. The MAX5953A/MAX5953C have an adjustable UVLO threshold withthe default value compliant to the 802.3af standard,while the MAX5953B/MAX5953D have a lower andfixed UVLO threshold compatible with some legacypre-802.3af PSE.
Operating ModesDepending on the input voltage (VIN = V+ - VEE), the PDfront-end section of the MAX5953A/MAX5953B/MAX5953C/MAX5953D operate in three different modes:PD detection signature, PD classification, and PD power.All voltage thresholds are designed to operate with orwithout the optional diode bridge while still complyingwith the IEEE 802.3af standard (see Figure 2).
Detection Mode (1.4V ≤ VIN ≤ 10.1V)In detection mode, the power source equipment (PSE)applies two voltages on VIN in the range of 1.4V to 10.1V(1V step minimum), and records the corresponding cur-rent measurements at those two points. The PSE thencomputes ∆V/∆I to ensure the presence of the 25.5kΩsignature resistor. In this mode, most interface circuitryof the MAX5953A/MAX5953B/MAX5953C/MAX5953D isoff and the offset current is less than 10µA.
Classification Mode (12.6V ≤ VIN ≤ 20V)In the classification mode, the PSE classifies the PDbased on the power consumption required by the PD.This allows the PSE to efficiently manage power distrib-ution. The IEEE 802.3af standard defines five differentclasses as shown in Table 1. An external resistor(RRCLASS) connected from RCLASS to VEE sets theclassification current.
The PSE determines the class of a PD by applying avoltage at the PD input and measuring the currentsourced out of the PSE. When the PSE applies a volt-age between 12.6V and 20V, the IC exhibits a currentcharacteristic with values indicated in Table 2. The PSEuses the classification current information to classifythe power requirement of the PD. The classification cur-rent includes the current drawn by the 25.5kΩ detec-tion signature resistor and the supply current of the ICso the total current drawn by the PD is within the IEEE802.3af standard figures. The classification current isturned off whenever the device is in power mode.
Table 1. PD Power Classification/RRCLASS Selection
Table 2. Setting Classification Current
*Class 4 reserved for future use.
*VIN is measured across the MAX5953A/MAX5953B/MAX5953C/MAX5953D input pins (V+ - VEE), which do not include the diodebridge voltage drop.
CLASS USAGERRCLASS
(Ω)MAXIMUM POWERUSED BY PD (W)
0 Default 10k 0.44 to 12.95
1 Optional 732 0.44 to 3.84
2 Optional 392 3.84 to 6.49
3 Optional 255 6.49 to 12.95
4Not
Allowed178 Reserved*
CLASS CURRENT SEEN AT VIN (mA)IEEE 802.3af PD CLASSIFICATIONCURRENT SPECIFICATION (mA)CLASS
RRCLASS(Ω)
VIN* (V)
MIN MAX MIN MAX
0 10k 12.6 to 20 0 2.00 0 4
1 732 12.6 to 20 9.17 11.83 9 12
2 392 12.6 to 20 17.29 19.71 17 20
3 255 12.6 to 20 26.45 29.55 26 30
4 178 12.6 to 20 36.60 41.40 36 44
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
16 ______________________________________________________________________________________
Power ModeDuring power mode, when VIN rises above the undervolt-age lockout threshold (VUVLO,ON), the IC gradually turnson the internal n-channel MOSFET Q1 (see Figure 8).The IC charges the gate of Q1 with a constant currentsource (10µA, typ). The drain-to-gate capacitance of Q1limits the voltage rise rate at the drain of the MOSFET,thereby limiting the inrush current. To further reduce theinrush current, add external drain-to-gate capacitance(see the Inrush Current Limit section). When the drain ofQ1 is within 1.2V of its source voltage and its gate-to-source voltage is above 5V, the MAX5953A/MAX5953Bassert the PGOOD output (MAX5953C/MAX5953D assertthe PGOOD output). The IC has a wide UVLO hysteresisand turn-off deglitch time to compensate for the highimpedance of the twisted-pair cable.
Undervoltage Lockout for PD InterfaceThe IC operates up to a 67V supply voltage with a defaultUVLO turn-on (VUVLO,ON) set at 38.6V (MAX5953A/MAX5953C) or 35.4V (MAX5953B/MAX5953D) and aUVLO turn-off (VUVLO,OFF) set at 30V. The MAX5953A/MAX5953C have an adjustable UVLO threshold using aresistor-divider connected to UVLO (see Figure 3). Whenthe input voltage goes below the UVLO threshold formore than tOFF_DLY, the MOSFET turns off.
To adjust the UVLO threshold, connect an externalresistor-divider from V+ to UVLO to VEE. Use the follow-ing equations to calculate R1 and R2 for a desiredUVLO threshold:
where VIN,EX is the desired UVLO threshold. Since theresistor-divider replaces the 25.5kΩ PD detection resis-tor, ensure that the sum of R1 and R2 equals 25.5kΩ±1%. When using the external resistor-divider, MAX5953A/MAX5953C have an external reference voltage hysteresisof 20% (typ). In other words, when UVLO is programmedexternally, the turn-off threshold is 80% (typ) of the newUVLO threshold.
Inrush Current LimitThe IC charges the gate of the internal MOSFET with aconstant current source (10µA, typ). The drain-to-gatecapacitance of the MOSFET limits the voltage rise rateat the drain, thereby limiting the inrush current. Add anexternal capacitor from GATE to OUT to further reducethe inrush current. Use the following equation to calcu-late the inrush current:
The recommended typical inrush current for a PoEapplication is 100mA.
PGOOD/PGOOD OutputPGOOD is an open-drain, active-high logic output.PGOOD goes high impedance when VOUT is within1.2V of VEE and when GATE is 5V above VEE.Otherwise, PGOOD is pulled to VOUT (given that VOUTis at least 5V below V+). Connect PGOOD directly toCSS to enable/disable the DC-DC converter. PGOOD isan open-drain, active-low logic output. PGOOD ispulled to VEE when VOUT is within 1.2V of VEE andwhen GATE is 5V above VEE. Otherwise, PGOOD goeshigh impedance. Connect a 100kΩ pullup resistor fromPGOOD to V+ if needed.
Thermal DissipationThermal shutdown limits total power dissipation in theIC. If the junction temperature exceeds +160°C, ther-mal shutdown is enabled to turn off the MAX5953A/MAX5953B/MAX5953C/MAX5953D, allowing the IC tocool. The IC turns on after the junction temperaturecools by 20°C.
DC-DC ConverterThe MAX5953A/MAX5953B/MAX5953C/MAX5953D iso-lated PWM power ICs feature integrated switching powerMOSFETs connected in a voltage-clamped, two-transis-tor, power-circuit configuration. These devices can beused in both forward and flyback configurations with awide 11V to 76V input voltage range. The voltage-clamped power topology enables full recovery of storedmagnetizing and leakage inductive energy for enhancedefficiency and reliability. A look-ahead signal for drivingsecondary-side synchronous rectifiers can be used toincrease efficiency. A wide array of protection featuresinclude UVLO, overtemperature shutdown, and short-cir-cuit protection with hiccup current-limit for enhancedperformance and reliability. Operation up to 500kHzallows smaller external magnetics and capacitors.
Power TopologyThe two-switch forward-converter topology offers out-standing robustness against faults and transformer sat-uration while affording efficient use of 0.4Ω powerMOSFETs. Voltage-mode control with feed-forwardcompensation allows the rejection of input supply dis-turbances within a single cycle similar to that of current-mode controlled topologies.
I ICCINRUSH G
OUT
GATE= ×
R kV
V
R k R
REF UVLO
INEX2 25 5
1 25 5 2
= ×
= −
.
.
,
,Ω
Ω
The two-switch power topology recovers energy storedin both the magnetizing and the parasitic leakage induc-tances of the transformer. The Typical ApplicationCircuit, Figure 3, shows the schematic diagram of a -48Vinput flyback converter using the MAX5953A. Figure 4shows the schematic diagram of a -48V input forwardconverter and a 5V, 3A output isolated power supply.
Voltage-Mode Control and the PWM RampFor voltage-mode control, the feed-forward PWM rampis generated at RCFF. From RCFF, connect a capacitorto GND and a resistor to HVIN. The ramp generated isapplied to the noninverting input of the PWM compara-tor at RAMP and has a minimum voltage of approxi-mately 2V. The slope of the ramp is determined by thevoltage at HVIN and affects the overall loop gain. Theramp peak must remain below the 5.5V dynamic rangeof RCFF. Assuming the maximum duty cycle approach-es 50% at a minimum input voltage (PWM UVLO turn-on threshold), use the following formula to calculate theminimum value of either the ramp capacitor or resistor:
where fS is the switching frequency, VR(P-P) is the peak-to-peak ramp voltage (2V, typ). Select RRCFF resistancevalue between 200kΩ and 600kΩ.
Maximize the signal-to-noise ratio by setting the ramppeak as high as possible. Calculate the low-frequency,small-signal gain of the power stage (the gain from theinverting input of the PWM comparator to the output)using the following formula:
GPS = NSP x RRCFF x CRCFF x fSwhere NSP is the secondary to primary power trans-former turns ratio.
Secondary-Side SynchronizationThe MAX5953A/MAX5953B/MAX5953C/MAX5953Dprovide convenient synchronization for optional sec-ondary-side synchronous rectifiers. Figure 5 shows theconnection diagram with a high-speed optocoupler.Choose an optocoupler with a propagation delay ofless than 80ns. The synchronizing pulse is generatedapproximately 110ns ahead of the main pulse that dri-ves the two power MOSFETs.
Undervoltage Lockout for DC-DC ConverterConnect PGOOD to DCUVLO to ensure the PD interfaceis ready prior to the DC-DC converter. The DCUVLOblock monitors the input voltage at HVIN through an
external resistive divider (R16 and R17) connected toDCUVLO (see Figure 3). Use the following equation tocalculate R16 and R17:
where VDCUVLOIN is the desired input voltage lockoutlevel and VDCUVLO is the undervoltage lockout thresh-old (1.25V, typ). Select the R17 resistance valuebetween 100kΩ and 500kΩ.
Optocoupled FeedbackIsolated voltage feedback is achieved by using anoptocoupler as shown in Figure 3. Connect the collec-tor of the optotransistor to OPTO and a pullup resistorbetween OPTO and REGOUT.
Internal RegulatorsAs soon as power is provided to HVIN, internal powersupplies power the DCUVLO detection circuitry.REGOUT is used to drive the internal power MOSFETs.Bypass REGOUT to GND with a minimum 2.2µF ceram-ic capacitor. The HVIN LDO steps down VHVIN to anominal output voltage (VREGOUT) of 8.75V. A secondparallel LDO powers REGOUT from INBIAS. A tertiarywinding connected through a diode to INBIAS powersup REGOUT once switching commences. This powersREGOUT to 10.5V (typ) and shuts off the current flow-ing from HVIN to REGOUT. This results in a lower on-chip power dissipation and higher efficiency.
V VRRDCUVLOIN DCUVLO= × +⎛
⎝⎜⎞⎠⎟
11617
R CV
f VRCFF RCFFIN EX
S R P P× ≥
× × −
,
( )2
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
______________________________________________________________________________________ 17
C
+5V
R
MAX5953AMAX5953BMAX5953CMAX5953D
PPWM
PGND
Figure 5. Secondary-Side Synchronous Rectifier Driver Using aHigh-Speed Optocoupler
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Program the MAX5953A/MAX5953B/MAX5953C/MAX5953D soft-start with an external capacitor (CCSS)connected between CSS and GND. When the deviceturns on, CCSS charges with a constant current of33µA, ramping up to 7.3V. During this time, the feed-back input (OPTO) is clamped to VCSS + 0.6V. This ini-tially holds the duty cycle lower than the value theregulator imposes, thus preventing voltage overshoot atthe output. When the IC turns off, the soft-start capaci-tor internally discharges to GND.
OscillatorThe oscillator is externally programmable through aresistor connected from RTCT to REGOUT and acapacitor connected from RTCT to GND. The PWM fre-quency is one-half the frequency seen at RTCT with a50% duty cycle. Use the following formula to calculatethe oscillator components:
where CPCB is the stray capacitance on the PC board(14pF, typ), VTH,RTCT is the RTCT peak trip level, andfS is the switching frequency.
Integrating Fault ProtectionThe integrating fault protection feature allows the IC toignore transient overcurrent conditions for a program-mable amount of time, giving the power-supply time tobehave like a current source to the load. This can hap-pen, for example, under load-current transients whenthe control loop requests maximum current to keep theoutput voltage from going out of regulation. The ignoretime is programmed externally by connecting a capaci-tor from FLTINT to GND. Under sustained overcurrentfaults, the voltage across this capacitor ramps uptoward the FLTINT shutdown threshold (2.7V, typ).When VFLTINT reaches the shutdown threshold, thepower supply shuts down. A high-value bleed resistorconnected in parallel with the FLTINT capacitor allowsthe capacitor to discharge toward the restart threshold(1.9V, typ). FLTINT drops to the restart threshold allow-ing for soft-starting the supply again.
The fault integration circuit works by forcing an 80µAcurrent into FLTINT for one clock cycle every time thecurrent-limit comparator ILIM (Figure 9) trips. Use thefollowing formula to calculate the approximate capaci-tor needed for the desired shutdown time:
where IFLTINT is typically 80µA, and tSH is the desiredignore time during which current-limit events from thecurrent-limit comparator are ignored.
This is an approximate formula; some testing may berequired to fine tune the actual value of the capacitor.
Calculate the approximate bleed resistor needed forthe desired recovery time using the following formula:
where tRT is the desired recovery time.
Choose tRT ≥ 10 x tSH. Typical values for tSH can rangefrom a few hundred microseconds to a few milliseconds.
ShutdownShut down the controller section of the IC by drivingDCUVLO to GND using an open-collector or open-draintransistor connected to GND. The DC-DC converter sec-tion shuts down if REGOUT is below its DCUVLO level.
Current-Sense ComparatorThe current-sense (CS) comparator and its associatedlogic limit the peak current through the internal MOSFET.Current is sensed at CS as a voltage across a senseresistor between the source of the MOSFET and GND.The power MOSFET switches off when the voltage atCS reaches 156mV. Select the current-sense resistor,RSENSE, according to the following equation:
RSENSE = 0.156V / ILimPrimary
where ILimPrimary is the maximum peak primary-sidecurrent.
To reduce switching noise, connect CS to an externalRC lowpass filter for additional filtering (Figure 3).
Applications InformationDesign Example
Design Example 1: PD with three-output flyback DC-DC converter
Figure 6 shows an isolated three-output flyback DC-DCconverter. It provides output voltages of 10V at 30mA,5.1V at 1.8A, and 2.55V at 5.4A.
Design Example 2: PD with nonisolated step-down(buck) converter
Figure 7 shows a buck converter with 12V, 0.75A out-put. Caution: this converter does not have active cur-rent limit.
Rt
CFLTINTRT
FLTINT≅
× 0 3514.
CI t
FLTINTFLTINT SH≅ ×
1 4.
R
f C C InV
V V
RTCT
s RTCT PCBREGOUT
REGOUT THRTCT
≅
+( ) ⎛
⎝⎜
⎞
⎠⎟−
1
2,
IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
18 ______________________________________________________________________________________
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______________________________________________________________________________________ 19
PGOO
D
V+ UVLO
R1*
OPEN
R3(R
DISC
)25
.5kΩ
C10
22µF 63
V
R5 210k
Ω
C210
0pF
C32.
2µF
C447
00pF
R725
.5kΩ
R11
2kΩ
*R1
AND
R2 A
RE O
PTIO
NAL
AND
WHE
N US
ED, T
HEY
MUS
T TO
TAL
25.5
kΩ A
ND R
EPLA
CE R
3, 2
5.5k
Ω.
C10.
068µ
FD1
56.7
V-48V
RTN
-48V
INBI
AS
R2*
0Ω
R4(R
CL)
255Ω
4 6 8RC
LASS
18
DCUV
LO
37
R16
316k
ΩR1
714
.7kΩ
HVIN
39
DRNH
PPW
M
PPW
M BST
C9 0.22
µFD1
1T1
D3
D2
D10
R6 100Ω
C24
0.1µ
FR2
810
kΩ
-48V
OUT
T2PA
0264
PPW
M
G1
D12
R16
1kΩ
R17
22Ω
G2N4
33, 3
421
36
XFRM
RH31
, 32
XFRM
RL28
, 29
INBI
AS40
D6
V EE
10
RCFF
44
RAM
P45
DRVI
N30
GATE
9
OUT
16
REGO
UT
FLTI
NT
4342
24
RTCT
CSS
22GND
25
OPTO
41
C510
00pF
C6 100p
FR8 1M
Ω
C7 0.01
µF
23
PGND
E3 2
8 7 6 5
U2FO
D271
2
C
LED FB
GND
COM
P
20
CS
26, 2
7SRC
C810
0pF
R9 1kΩ
R10
0.18
Ω
C13
0.22
µF R14
470Ω
R22
221Ω
C19
0.06
8µF
C20
0.06
8µF
C21
0.1µ
F
R21
2.52
kΩ
R20
2.74
kΩ
C12
0.1µ
F
V OUT
1 (10
V AT
30m
A)
MAX
5953
A
U1
R6 210k
Ω
GATE
-48V
OUT
R15
210k
Ω
R25
OPEN
N.C. 1,
4
R24
1kΩ
R23
1MΩ
D8D5
V OUT
2C22
220µ
FC2
322
0µF
A1
D7
V OUT
3
A2
INBI
AS
C11
0.1µ
F
N3A2
V OUT
2
RTN
D4R1
822
Ω
R19
1kΩ
G1N2
N1A1
-48V
OUT
V OUT
3
V OUT
2 (5.
1V A
T 1.
8A)
V OUT
3 (2.
55V
AT 5
.4A)
C17A
100µ
F
C16
100p
F
C14
0.47
µF
C17
220µ
FC1
822
00pF
C15
22µF
C25
0.1µ
F
A1
D9R2
710
kΩ
G2
C26
0.1µ
FA2
Figure 6. PD with Three-Output Flyback DC-DC Converter
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20 ______________________________________________________________________________________
PGOO
D
PGOO
D
U1
R914
.7kΩ
R831
6kΩ
V+
R1(R
DISC
)25
.5kΩ
C222
µF 63V
C168
nF
R321
0kΩ C3
100p
F
C615
0pF
C7 100p
F
C8 0.02
2µF
PGOO
D
D1 60V-48V
RTN
-48V
0.5A
R2(R
RCLA
SS)
255Ω C5
4700
pF
C42.
2µF
R426
.7kΩ
R6 100k
Ω
R5 1kΩ
4 8RC
LASS
18
DCUV
LO
37
HVIN
39
DRNH
PPW
M BST
33, 3
421
36
XFRM
RH31
, 32
XFRM
RL28
, 29
INBI
AS40
D4
V EE
10
RCFF
44
RAM
P45
DRVI
N30
GATE
9
OUT
16
REGO
UT
FLTI
NT
4342
24
RTCT
CSS
22GND
25 OP
TO
41
23 PG
ND
PGND
C9 OPEN
C13
1µF
R10
OPEN
R13
14.3
kΩR1
16.
81kΩ
R12
1.78
kΩ
R73.
9kΩ
L122
0µH
C10
0.02
2µF
C16
0.01
µF
C14
0.15
µF
C11
22µF
C12
1µF
20
CS
26, 2
7
TL43
1CD
SRC
R16
4.99
kΩ
C15
0.03
µF
OUT
12V,
0.7
5A
GND
MAX
5953
A
Figure 7. PD with Nonisolated Step-Down (Buck) Converter
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
______________________________________________________________________________________ 21
Layout RecommendationsAll connections carrying pulsed currents must be veryshort, as wide as possible, and have a ground plane asa return path. The inductance of these connectionsmust be kept to a minimum due to the high di/dt of thecurrents in high-frequency-switching power converters.
Current loops must be analyzed in any layout pro-posed, and the internal area kept to a minimum toreduce radiated EMI. Ground planes must be kept asintact as possible.
Table 3. Component SuppliersCOMPONENT SUPPLIERS WEBSITE
International Rectifier www.irf.com
Fairchild www.fairchildsemi.comPower FETS
Vishay-Siliconix www.vishay.com/brands/siliconix/main.html
Dale-Vishay www.vishay.com/brands/dale/main.htmlCurrent-Sense Resistors
IRC www.irctt.com/pages/index.cfm
ON Semi www.onsemi.com
General Semiconductor www.gensemi.comDiodes
Central Semiconductor www.centralsemi.com
Sanyo www.sanyo.com
Taiyo Yuden www.t-yuden.comCapacitors
AVX www.avxcorp.com
Coiltronics www.cooperet.com
Coilcraft www.coilcraft.comMagnetics
Pulse Engineering www.pulseeng.com
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22 ______________________________________________________________________________________
Block Diagrams
V+
UVLO
V+
UVLO*
*MAX5953A/MAX5953C ONLY.**MAX5953C/MAX5953D ONLY.***MAX5953A/MAX5953B ONLY.
GATE
MAX5953AMAX5953BMAX5953CMAX5953D
CLASSIFICATION RCLASS
PGOOD**
6.8VEN
REF
2.4VREF
2.4V, 0.8HYST
21.8V
39V
200mV
VEE
VGATE, 6V
1.2V, REF
5V, REF
Q4
PGOOD***
OUT
Q3
Q10.6Ω
Q238Ω
EN
Figure 8. Powered Device Interface Block Diagram
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
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Figure 9. DC-DC Converter Block Diagram (Voltage-Mode PWM Controller and Two-Switch Power Stage)
OVTDCUVLOREFOKREGOKOVRLD
T
T
5V
5V
80µA
33µA
IFLT5V
OVRLD
CPWM
ILIM
DCUVLO
REGOUT
RCFF
FLTINT
RAMP
OPTO
CSS
GND
INBIAS
HVIN
DCUVLO
PPWM
BST
XFRMRH
DRVIN
XFRMRL
DRNH
SRC
PGND
RTCT
CS
REGOK
REG
OVTREFOK REF
(1.25V)
7.5V
50Ω
GND
Q D
R
Q R
T-FF
SHDN
OSC
50Ω
GND
R
S
Q
CLK
THERMALSHUTDOWN OVT
1.25V
DCUVLO
80nsDELAY
LEADING-EDGE
DELAY
ONESHOT
LEVELSHIFT
10MHz
PGND150mV
QH
QB
QL
0.4Ω
30Ω
0.4Ω
MAX5953AMAX5953BMAX5953CMAX5953D
2.7V/1.9V
Block Diagrams (continued)
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
24 ______________________________________________________________________________________
Typical Operating CircuitPG
OOD
V+ UVLO
R1*
R3(R
DISC
)25
.5kΩ
C168
nFD1 60
V-48V
RTN
-48V
R2*
R RCL
ASS
4 6 8RC
LASS
18
DCUV
LO
37
HVIN
39
DRNH
PPW
M BST
33, 3
421
36
XFRM
RH31
, 32
XFRM
RL28
, 29
INBI
AS40
V EE
10
RCFF
44
RAM
P45
DRVI
N30
GATE
9
OUT
16
REGO
UT
FLTI
NT
4342
24
RTCT
CSS
22GND
25 OP
TO
41
23 PG
ND
PGND
E
U2FO
D271
2
C
LED FB
GND
COM
P
20
CS
26, 2
7SRC
OUT
SGND
MAX
5953
A
U1
*R1
AND
R2 A
RE O
PTIO
NAL
AND
WHE
N US
ED, T
HEY
MUS
T TO
TAL
25.5
kΩ A
ND R
EPLA
CE R
3, 2
5.5k
Ω.
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
______________________________________________________________________________________ 25
Chip InformationPROCESS: BiCMOS
Selector Guide
Pin Configuration
PARTPGOOD or
PGOODUVLO
MAX5953A PGOOD Adjustable
MAX5953B PGOOD Fixed
MAX5953C PGOOD Adjustable
MAX5953D PGOOD Fixed
TOP VIEW
MAX5953AMAX5953BMAX5953CMAX5953D
THIN QFN7mm x 7mm
13
14
15
16
17
18
19
20
21
22
23
24
N.C.
N.C.
OUT
OUT
N.C.
**
N.C.
CS
PPWM
GND
PGND
CSS
48
47
46
45
44
43
42
41
40
39
38
37
1 2 3 4 5 6 7 8 9 10 11 12
N.C.
N.C.
N.C.
RAMP
RCFF
FLTINT
RTCT
REGOUT
INBIAS
HVIN
N.C.
DCUVLO
*UVLO FOR MAX5953A/MAX5953C N.C. FOR MAX5953B/MAX5953D** PGOOD FOR MAX5953A/MAX5953B PGOOD FOR MAX5953C/MAX5953D
+N.
C.V EE
V EE
GATE
RCLA
SSN.C.*
N.C.V+N.C.
N.C.
N.C.
36 35 34 33 32 31 30 29 28 27 26 25
OPTO
SRC
SRC
XFRM
RL
XFRM
RL
DRVI
N
XFRM
RH
XFRM
RH
DRNH
DRNH
N.C.
BST
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
26 ______________________________________________________________________________________
Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline informationgo to www.maxim-ic.com/packages.)
32, 4
4, 4
8L Q
FN
.EP
S
e
L
e
L
A1A
A2
E/2
E
D/2
D
DETAIL A
D2/2
D2
b
L
k
E2/2
E2
(NE-1) X e
(ND-1) X e
e
CLCL
CL
CL
k
DETAIL B
e
L
L1
PACKAGE OUTLINE
21-0144 21
E
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
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IEEE 802.3af PD Interface and PWM Controllerswith Integrated Power MOSFETs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
M. Quijano
Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline informationgo to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
21-0144 22
E
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
Revision HistoryPages changed at Rev 1: 1, 27