Differential 60 GHz Antenna-on-Chip in Mainstream

65 nm CMOS Technology

A.B.Smolders, U. Johannsen, M.Liu, Y.Yu, P.G.M. Baltus

Electromagnetics Group/Centre for Wireless Technology

Department of Electrical Engineering

Eindhoven University of Technology (TU/e)

P.O. Box 513, 5600 MB Eindhoven, The Netherlands

Abstract—The integration of a differential antenna in

mainstream 65 nm CMOS was investigated. A 60 GHz prototype

integrated circuit (IC) was developed, including a seal-ring and

on-chip calibration structures. Measured results show excellent

impedance matching properties over a 10 GHz bandwidth and a

moderate antenna gain of -1.5 dBi. However, this is still a

significant improvement as compared to state-of-the-art in

mainstream CMOS.

I. INTRODUCTION

Various technologies are used in the millimeter-wave region for implementing antenna structures, ranging from Antenna-in-Package (AiP) to Antenna-on-Chip (AoC) [1]-[3]. Although the inherent losses in most packaging technologies are much lower as compared to on-chip implementations, the AoC has several advantages, e.g. no interconnect losses between antenna and electronics and low-cost. In addition, standard wire-bond technologies can be used, since the Integrated Circuit (IC) does not require any off-chip mm-wave interconnect. The availability of a large bandwidth in the unlicensed 60-GHz band has created a lot of interest for developing new high data rate consumer applications, such as Gigabit wireless ethernet. These consumer-oriented applications require the use of advanced CMOS semiconductor technologies. In this paper we will investigate the integration of an antenna in standard 65 nm CMOS technology. Main issues are the reduction of substrate losses and the investigation of the effect of metal tilling and a seal-ring.

II. ANTENNA-ON-CHIP DESIGN

Since most Silicon-based on-chip front-ends use differential amplifier circuits we have chosen a differential antenna concept [4]. In this way a balanced-to-unbalanced (balun) convertor can be avoided. Mainstream 65 nm CMOS technology typically uses 7 metal layers (M1-M7, all copper) separated by dielectric layers consisting of SiO2 and other low-k materials. The

thickness of this dielectric stack is approx. 4 µm. This stack is placed on a doped Silicon substrate. One of the key limitations when integrating antennas in Silicon-based processes is the fact that the Silicon substrate has a high relative permittivity of

εr=11.9 with a relative high loss tangent. In our case, we used

doped Silicon with a resistivity of 15 Ωcm, which correspond

to a loss tangent tanδ=0.17 at 60 GHz. Hence, the radiation efficiency can be significantly affected by this. The on-chip antenna in mainstream CMOS technology of [5] and [6], only

achieved a gain of -8 dBi and -12 dBi, respectively. When we want to avoid the propagation of TE-modes and higher-order TM-modes (the TM0 mode is always propagating) the Silicon

thickness should be below 350 µm for frequencies up to 66 GHz [7]. Therefore, we have grinded the wafer of our final

prototype back to an overall thickness of 300 µm. We have used the metal-covered substrate approach to reduce substrate losses and to create a quarter-wave Yagi-Uda like reflector for the radiating dipole [7]. The final test chip that was designed and manufactured in a 65 nm CMOS technology including the Short-Open-Load (SOL) calibration structures is shown in Fig.1, including the relevant dimensions. The dipole arms have

a total length of L1=1124 µm. The 70 Ω feed-line that connects the dipole to the GSGSG bond-pad structure uses a U-shaped ground plane. Special care was taken in the design of the overall structure to fulfill all manufacturing rules of the 65nm CMOS process. Design rules dictate that metal tiles have to be used as much as possible to ensure a minimum metal-density. In addition, a metal seal-ring is required along the periphery of the IC to protect the IC from moisture degradation and damage during dicing and packaging. We have used metal tiles of

1 µm2 which are connected from metal layer M7 to M1. Close

to the radiating dipole we have a small region without tiling (8

µm spacing from dipole arm). This is the darker region in Fig.1 close to the dipole arms.

Fig. 1. Photo of the Antenna-on-Chip (AoC) in 65 nm CMOS

including on-chip Short-Open-Load calibration structures. Chip size

is 1.5x1.4 mm2, L1=1124 µm, L2=283 µm. Dipole width is 12 µm.

Feed line (70 Ohm)

Metal plate

short

open

load

antenna

L1

L2

356978-1-4799-3540-6/14/$31.00 ©2014 IEEE AP-S 2014

III. EXPERIMENTAL RESULTS

For experimental verification, the IC was mounted on a 5x5

mm2 grounded substrate with εr=4 and thickness of 0.9 mm. The test-set-up of Fig.2 was used to measure the input impedance of the on-chip antenna. The set-up uses a GSGSG probe with

integrated balun and pitch of 125 µm. The simulated and measured return loss is shown in Fig.3. A quite good agreement between simulation and experiment is obtained. Originally, the antenna was designed for a center frequency at 60 GHz, but due to the presence of the grounded dielectric substrate, the antenna is somewhat detuned to a lower frequency. Note that the simulations were done with a time-domain solver [8] including all details of the IC (e.g. metal-dielectric stack, metal tiles) and the grounded dielectric substrate. The on-chip SOL calibration structures have been measured to extract the effect of the bond pad structure in the measurement results. From the return loss it might be concluded that the impedance bandwidth of the antenna is quite large, more than 10 GHz around the center frequency of 58 GHz. However, the resistive part of the input impedance is not only due to radiation losses, but is partly also due to losses in the Silicon substrate. Therefore, as a next step, the radiation properties were measured in the 60 GHz test set-up of [9]. The gain was determined by comparing the Antenna-under-Test (AUT) with a reference antenna. Based on this, the measured gain was estimated to be approximately -1.5 dBi at 60 GHz. The simulated gain of this antenna is -0.8 dBi with a corresponding efficiency of 32%. The gain is, of course, much lower than one could expect from a printed dipole on a low-loss substrate, but significantly better as compared to the reported on-chip results in [5]-[6]. The radiation efficiency of our AoC can be further improved when the resistivity of the doped Silicon would be increased. Simulations show that the radiation efficiency can be increased to 70% or more, when the

resistivity of the doped Silicon is higher than 100 Ωcm. Future mainstream CMOS technologies could enable on-chip integration of antennas by improving the resistivity up to or above this level.

Fig. 2. Test set-up to measure the input impedance of the AoC. A

Ground-Signal-GSG (GSGSG) probe with 125 µm pitch was used.

Fig. 3. Measured and simulated input reflection of the AoC in 65nm CMOS technology. The simulation ( FIT solver,[8]) includes a

5x5 mm2 supporting grounded dielectric substrate with εr=4.

IV. CONCLUSIONS

It is shown that on-chip integration of antennas in mainstream CMOS technologies is possible. The performance in terms of impedance matching is good. However, the measured antenna gain and efficiency are moderate, but will be sufficient for short range applications in the 60 GHz band.

V. ACKNOWLEDGEMENTS

The authors would like to thank R. van Dommele and A. Reniers for the support during the measurements.

REFERENCES

[1] U. Johannsen, “Technologies for integrated millimeterwave antennas,” Ph.D. dissertation, Eindhoven University of Technology, 2013. [Online]. Available: http://alexandria.tue.nl/extra2/754833.pdf

[2] A. Babakhani, X. Guan, A. Komijani, A. Natarajan, and A. Hajimiri, “A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2795 –2806, 2006.

[3] U. Johannsen and A. B. Smolders, “On the yield of millimeterwave bond-wire-antennas in high volume production,” IEEE Transactions on Antennas and Propagation, vol.61, no.8, pp.4363-4366, Aug. 2013.

[4] Y.Yu et.al. “ A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems”, IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 2795 –2806, 2010.

[5] S.-S. Hsu, K.-C. Wei, C.-Y. Hsu, and H. Ru-Chuang, “A 60-GHz Millimeter-Wave CPW-Fed Yagi Antenna Fabricated by Using 0.18-um CMOS Technology,” IEEE Electron Device Letters, vol. 29, pp. 625 –627, 2008.

[6] Han-Lin Yue et. al, "60-GHz CMOS integrated on-chip Yagi antenna and balun bandpass filter in 90-nm CMOS technology," European Conference on Ant. and Prop. (EUCAP), pp.3546-3548, 2012.

[7] U. Johannsen, A.B. Smolders, R. Mahmoudi, and J.A.G. Akkermans,. “Substrate Loss Reduction in Antenna-on-Chip Design”. Proc. IEEE Antennas and Propagation Symposium, pp. 1-4, June 2009.

[8] www.cst.com

[9] A.B. Smolders, A.C.F. Reniers, U. Johannsen and M.H.A.J. Herben, “Measurement and Calibration Challenges of Microwave and Millimeter-wave Phased-Arrays”, Proc. of the IEEE International Workshop on Antenna Technology (iWAT), pp.354-357, 2013.

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