Real Time Implementation and Profiling of Different CFAR Algorithms over DSP Kit

M. Amir Shafiq CESAT, Islamabad, Pakistan

amirshafiq@gmail.com

Abstract—Constant False Alarm Rate (CFAR) is commonly used in RADAR and SONAR to detect targets in different clutter situations. We aim to design a CFAR detector to be used in FMCW radar which is easily configurable and is best suited to its operational environment. Mathematical formulation and MATLAB simulation of six different CFAR detectors are presented in this paper. The performance of these detectors are discussed with respect to clutter environment and target detection. Real time implementation of these algorithms was also carried out over DSP kit (TMS320C6713). Performance comparison and profiling of CFAR detectors over hardware is also given in this paper. CFAR detector with best performance in terms of time and target detection will be used in FMCW radar.

I. INTRODUCTION

Primary radar should detect all the objects in its vicinity to give clear picture of its surrounding to its user. Radar detection scheme involve comparing received signal amplitude to specific threshold. Based on this comparison radar signal processor qualify it as target or not. Since background noise is not constant and clutter power is not known at any fixed location, fixed threshold for target detection cannot be used in modern radars. Radars have to be adaptive to variation in background clutter so that they can identify the targets presents in clutter. This can be achieved using Constant False Alarm Rate (CFAR) detector. CFAR is one of the most important part of radar signal processor. CFAR not only avoid overloading signal processor by clutter fluctuation but also obtain high detection performance. CFAR employs adaptive threshold relative to clutter level to maintain constant rate of false alarm irrespective of clutter power and maximize target detection.

Lot of research is done in this area over past many decades. Detecting radar target in unknown clutter and noise environment is studied in detail in [1]. Mathematical formulation of CFAR detector is also presented in [1]. Analysis of Cell Averaging CA-CFAR, Ordered Statistics OS-CFAR and the combinations of these two is presented in [2]. In [2], performance comparison was done based on Probability of False Alarm (PFA) and Probability of Detection (PD). Real time implementation of CFAR detectors over FPGA is also discussed in [2]. The comparison of different CFAR detectors is complicated because of numerous unknown clutter situations possible in reference window of CFAR. Comparison of censored algorithm, Smallest-of (SO) algorithm and (OS) CFAR detector is presented in [3]. Some CFAR schemes for target detection are presented in [4]. CFAR detectors presented in [4] can be applied to multiple target situations as well to avoid any masking situation. A number of

CFAR algorithms are discussed in detail in [5] with respect to their operational flexibility and cost of operation. A new CFAR detector Switching Variability Index SVI-CFAR that combines the advantages of both Variability Index VI-CFAR and Switching S-CFAR is also proposed in [5].

Hardware architecture for adaptive filtering based on energy-CFAR processor for radar target detection is presented in [6]. Proposed design in [6] allows for easy configuration of adaptive filtering in order to adjust the system according to its environment. A configurable hardware architecture for target detection in noisy environment is presented in [7-8]. Three different CFAR detectors were implemented on FPGA for target detection through adaptive processing of noisy signals. Hardware implementation of OS-CFAR processor for target detection is presented in [9]. The proposed implementation architecture over FPGA in [9] allows for optimization of FPGA hardware resources as compared to direct implementation approach.

In this paper, we have presented mathematical formulation and carried out simulation for six different CFAR detectors. Real time implementation of CFAR algorithms over DSP kit is also presented in this paper. Rest of paper is organized as follows. Problem statement is given in section II. Mathematical formulation and simulation of six different CFAR detectors are given in section III. Real time implementation and experimental results are presented in section IV and finally conclusion is given in section V.

II. PROBLEM STATEMENT

Frequency Modulated Continuous Wave (FMCW) radar uses a very Low Probability of Intercept (LPI) waveform, which decreases its Electronics Support Measure (ESM) detection range to an extent and making it virtually undetectable. FMCW is widely used in applications such as naval navigation radars, altimeters, smart ammunition sensors and automotive radars. Block diagram of FMCW signal processing is shown in Fig. 1. Our aim is to develop a CFAR processor for FMCW radar. After initial signal processing, CFAR processor will be used for detecting targets.

Figure 1. Block Diagram of FMCW Radar Signal Processor

Proceedings of 2014 11th International Bhurban Conference on Applied Sciences & Technology (IBCAST)Islamabad, Pakistan, 14th – 18th January, 2014 466

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III. CFAR DETECTOR

General diagram of CFAR processor is shown in Fig. 2. CFAR processor consists of window of length N+1.Where N is number of cell surrounding the Cell Under Test (CUT) [2].

Figure 2. General Diagram of CFAR Processor

Processing of CUT, leading and lagging windows produce an estimate Z which is later used to target detection. We assume that output for any range cell is exponentially distributed with Probability Density Function (PDF) given by (1)

(1) where is the total background clutter plus thermal

noise power given as μ under the null hypothesis H0 and is defined as μ(1+S) where S is the average signal to noise ratio(SNR) of a target [2]. The PFA is given by (2)

(2) where Y0 denotes the fixed optimum threshold.

Similarly the optimum detection probability PD is given by (3)

(3) For CA-CFAR scheme the PFA is given by (4)

(4)

(5)

Where Mz() denotes the Moment Generating Function (MGF) of the random variable Z [2]. Similarly, the detection probability PD is given by (6)

(6) Under the signal present hypothesis H1 the mean 2 =

2μ(1+S), one can determine the PD by simply replacing μ with μ(1+S)[2]

(7)

Six different CFAR detectors are explained below. Mathematical descriptions as well as simulation results are also shown for each CFAR detector.

A. CA-CFAR In CA-CFAR estimate Z is estimated based on sum of

total noise power of N range cells in reference window. This gives a complete sufficient statistic for the noise

power with μ under the assumption of exponentially distributed homogeneous noise background [2]. Block diagram of CA-CFAR processor is shown in Fig. 3.

Figure 3. Block diagram of CA-CFAR processor

The statistic Z is defined by (8) (8)

where Xi’s are range cells surrounding the CUT. PD is given by (9)

(9)

The constant scale factor T can be found by setting S=0

(10) Simulation of CA-CFAR detector is shown in Fig. 4. It

can be seen that CA-CFAR threshold adapted according to clutter level. CA-CFAR detector has correctly identified all targets as shown in Fig. 4.

Figure 4. CA-CFAR Simulation Results

B. GOCA-CFAR In Greater Of GOCA-CFAR, both leading and lagging

windows calculate the estimate of noise and greater of them will be used further in calculations. Mathematically it is given by (11) [10]

(11)

Proceedings of 2014 11th International Bhurban Conference on Applied Sciences & Technology (IBCAST)Islamabad, Pakistan, 14th – 18th January, 2014 467

Simulation results show that GOCA-CFAR correctly identified all targets as shown in Fig. 5.

Figure 5. GOCA-CFAR Simulation Results

C. SOCA-CFAR In Smaller Of SOCA-CFAR, both leading and lagging

windows calculate the estimate of noise and smaller of them will be used further in calculations. Mathematically it is given by (12)

(12)

Simulation of SOCA-CFAR concluded that it correctly identified all targets and is shown in Fig. 6.

Figure 6. SOCA-CFAR Simulation Results

D. OS-CFAR In OS-CFAR, first of all, cells in reference window are

sorted in ascending order and then threshold is obtained from one of the ordered samples. Block diagram of OS-CFAR processor is shown in Fig. 7.

Statistic Z is taken as kth largest samples X(k). PDF of Z=X(k) is given by (13) [2]

(13) where f is the PDF with =1/2. PD is computed using

(14)

(14)

Similarly the PFA can be given by (15) (15)

Figure 7. Block Diagram of OS-CFAR Processor

Simulation of OS-CFAR is shown in Fig. 8. Simulations results show that OS-CFAR identified all targets successfully.

Figure 8. OS-CFAR Simulation Results

E. AND-CFAR AND-CFAR and OR-CFAR are combination of CA-

CFAR and OS-CFAR algorithms. Their general block diagram is shown in Fig. 9.

In AND-CFAR, the target must be greater than both the CA-CFAR and OS-CFAR threshold to be declared as target. This means target should pass through both CA-CFAR and OS-CFAR detector to be qualified as target. Mathematically it is given by (16) [2]

(16) If amplitude of CUT is greater than ZAND, then it is

declared as target, else no target. Simulation results of AND-CFAR are depicted in Fig. 10 which shows that it successfully identified all targets.

F. OR-CFAR In OR-CFAR target must be greater than either CA-

CFAR or OS-CFAR thresholds to be qualified as target. This means that target should pass any one of the detector to be declared as target [2]. Mathematically it is given by (17)

(17) Simulation of OR-CFAR is shown in Fig. 11.

Simulations results show that OR-CFAR identified all targets successfully.

Proceedings of 2014 11th International Bhurban Conference on Applied Sciences & Technology (IBCAST)Islamabad, Pakistan, 14th – 18th January, 2014 468

Figure 9. General Block Diagram of AND-CFAR and OR-CFAR

Figure 10. AND-CFAR Simulation Results

Figure 11. OR-CFAR Simulation Results

Data and all CFAR thresholds are shown in Fig. 12. It can be observed that all CFAR detectors were successful in extracting targets. CFAR detectors threshold adjusted automatically according to the levels of clutter. This adaptability of CFAR detectors helps to detect targets under different noise levels and environmental conditions.

Figure 12. Data and CFAR Detectors Threshold

IV. HARDWARE IMPLEMENTATION Digital Signal Processing (DSP) kits are primarily used

to keep processing pace of system with some external event or real time system. With embedded system such as DSP kit or FPGA, a non-real time system can be set to overcome timing constraints and increase overall performance of the system. Non-real time systems doesn't have any strict timing constraints; their data can be recorded and signal processing can be done offline to achieve desired results. After signal processing algorithms are finalized, they are implemented on DSP kit or any embedded system to operate stand-alone and match timing constraints. DSP kits and FPGA's are primarily used for real time implementation of a system [11]. DSP kit such as TI TMS320C6713 have high processing speed and it is easy to use, flexible, and economical [12-13]. Six different CFAR detectors discussed above were successfully implemented on TMS320C6713 DSP kit. Block diagram of embedded implementation is shown in Fig. 13.

Figure 13. Block Diagram of Hardware Implementation

We used two signal generators and combined their output so that we can mimic two targets in our signal processor. This signal was then converted to digital signal using ADC. After some initial signal processing CFAR detectors were applied to data. Real Time Data Exchange (RTDX) was used to transfer data between DSP kit and PC. Experimental setup is shown in Fig. 14.

All CFAR detectors were successful in detecting targets. Output of CFAR detector is shown in Fig. 15. Since two signal generators were used, therefore there are two frequency components in FFT and hence two targets. When we change the frequency from signal generators, targets move accordingly with frequency change indicating effectiveness of real time implementation.

Proceedings of 2014 11th International Bhurban Conference on Applied Sciences & Technology (IBCAST)Islamabad, Pakistan, 14th – 18th January, 2014 469

Figure 14. Experimental Setup

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Figure 15. CFAR Output

We also profiled CFAR detectors to see which CFAR detector is computationally less expensive and best suited to our current environment. Results of profiling are listed in Table 1.

It can be seen that CA-CFAR detector has least time for

execution and also detected targets successfully therefore in our current system we will use CA-CFAR detector.

V. CONCLUSION

Six different CFAR detectors are simulated and implemented in this paper. Mathematical formulations of CFAR detectors are also presented. Simulation results

show that target detection was achieved successfully using CFAR detectors. Real time implementation over DSP kit TMS320C6713 was also carried out. Experimental results show effectiveness of real time implementation. Profiling of CFAR detectors concluded that CA-CFAR has least execution time and also successfully detected all targets therefore it is best suited for our current environment. Any CFAR detector that successfully detect targets in its environment and has time limit within coherent processing time of FMCW radar can be used for target detection. With little modification, developed system can be used in other radars as well.

REFERENCES

[1] M. B. El Mashade, “Performance Analysis of OS Structure of CFAR Detectors in Fluctuating Target Environments,” Progress In Electromagnetics Research C, Vol. 2, pp. 127–158, 2008.

[2] P. Ramesh Babu and R. Prasanthi, “Analysis of CFAR Techniques and FPGA Realization for Radar Detection,” Proceedings of International Conference on Intelligent Knowledge Systems, 2004.

[3] H. Rohling, “Robust Algorithms for Point Target Detection in Different Background Situations,” GRETSI, Groupe d’Etudes du Traitement du Signal et des Images, 1987.

[4] H. Rohling, Some Radar Topics: Waveform Design, Range CFAR and Target Recognition.

[5] J. J. Jen, A Study Of CFAR Implementation Cost and Performance Tradeoffs in Heterogeneous Environments, MS Thesis, California State Polytechnic University, Pomona, 2011.

[6] S. L. Estrada and R. Cumplido, “Hardware Architecture for Adaptive Filtering based on Energy-CFAR Processor for Radar Target Detection,” IEICE Electronics Express, Vol. 7, No. 7, pp. 628-633, 2010.

[7] C. T. Huitzil, R. C. Parra and S. L. Estrada, “Design and Implementation of a CFAR Processor for Target Detection,” Mexico.

[8] R. Cumplido, C. Torres and S. Lopez, “On the Implementation of an efficient FPGA-based CFAR Processor for Target Detection,” International Conference on Electrical and Electronics Engineering (ICEEE) and X Conference on Electrical Engineering, September 8-10, 2004.

[9] B. Magaz, T. Mabed and A. Abbadi, “Design and Implementation of a Real Time FPGA Based CFAR Processor for Radar Target Detection Using ML403 FPGA Development Board,” 5th International Conference on Sciences of Electronic, Technologies of Information and Telecommunications, March 22-26, 2009.

[10] F. Olah, M. Baracskai and R. Horvath, “CW and FM-CW radar adaptation for vehicle technology,” HU ISSN 1418-7108: HEJ Manuscript no: TAR-080404-A.

[11] N. kehtarnavaz, Real-time digital signal processing based on the TMS320C6000, ELSEVIER, 2005.

[12] R. Chassaing, Digital Signal processing and applications with the C6713 and C6416 DSK, A John Wiley and Sons, Inc., Publications, 2005.

[13] (2010, May.) [Online]. Available: Texas instruments DSP developer’s village. World Wide Web, www.dspvillage.ti.com

TABLE I. PROFILING OF CFAR DETECTORS

S. No CFAR Detector Time

1 CA-CFAR 170.05 us

2 GOCA-CFAR 205.03 us

3 SOCA-CFAR 205.03 us

4 OS-CFAR 2.061 ms

5 AND-CFAR 2.243 ms

6 OR-CFAR 2.243 ms

Proceedings of 2014 11th International Bhurban Conference on Applied Sciences & Technology (IBCAST)Islamabad, Pakistan, 14th – 18th January, 2014 470