On/Off Control of a Modular DC-DC ConverterBased on Active-Clamp LLC Modules

Hien Nguyen, Dragan MaksimovicColorado Power Electronics Center

University of Colorado BoulderBoulder, CO 80309-0425

Email: {Hien, Maksimov}@Colorado.edu

Regan ZanePower Electronics LabUtah State University

North Logan, UT 84341Email: Regan.Zane@USU.edu

Abstract—This paper studies on/off control of a dc-dc systemthat contains multiple active-clamp LLC resonant modules oper-ating in parallel. The architecture and the on/off control methodyield high overall efficiency and fast transient responses. Twoconverter models are introduced for different purposes: (1) ahigh-frequency model to determine a gate timing sequence thatenables fast on/off control, and (2) an averaged model to assist inthe system control loop design. The models and the on/off controlmethod are verified by experiments on a 1 MHz, 24 V-to-3.3 V,5.5 W active-clamp LLC module prototype. The performanceof PI and PID system controllers is analyzed and compared bysimulations of a twenty-module system.

I. INTRODUCTION

In point-of-load (POL) applications, multi-phase buck-basedconverters are widely used to meet the high-current low-voltage load demand, and to improve transient performanceand efficiency over wide load range [1]–[3]. The number ofphases can be changed dynamically to improve light load effi-ciency further [4]. In radio-frequency dc-dc power conversionapplications, the approach of turning the number of modules(or phases) on or off has been developed not only to improvelight load efficiency but also to improve output voltage regula-tion [5]. This cell-modulation-regulated approach is illustratedin Fig. 1. Each module in the system is designed to operate atone operating point at its highest efficiency. In order to providethe required output power and to regulate the output voltage,the controller fully turns on a certain number of modules,while fine control is accomplished by turning one module

ON/OFF controls

Module 1

Module 2

Module N

Vin V

out

Iout

c1

c2

cN

c1

c2

cN...

Fig. 1. Cell-modulation-regulated architecture

on or off in a pulse-width-modulated (PWM) manner. Suchcontrol method requires the converter modules to have quickturn-on/off feature and relatively high output impedance. Thisarchitecture has been verified by experiments using hystereticcontrol or fixed-frequency PWM with hysteretic override onone module [5]–[11]. A sigma-delta modulator is suggestedfor multiple-module systems [5], but has not been studied indetail.

A similar approach has been pursued in POL applications[12]–[14] where an interleaved multi-phase buck converteris treated as a multi-level power analog to digital converter(ADC). In this case, each buck phase is equivalent to a voltagesource in series with a low output impedance. Moreover, thebuck converter has limitations in large-step-down, high-currentand high-frequency applications because of the low duty-cycleand relatively high switching losses. In order to address theselimitations, an active-clamp LLC resonant converter shown inFig. 2 has been proposed [15]. In this converter, all devicesoperate at nearly 50% duty cycle, and switching loss arereduced significantly thanks to soft-switching operation. Theconverter has high output impedance, which makes it suitablefor the architecture shown in Fig. 1.

This paper presents an approach to on/off control in themultiple-parallel-module architecture, using the active-clampLLC resonant converter as the module topology. Section IIgives an overview of the converter modeling. Section III showssystem modeling and compensator design steps, including

+

-

+�

R

+

-

+

-

+

-

+

-

+ -1:n:n

Cf

Vout

vCs

Vg

Q1

Q2

vsw

Cs i

sLs

Lm

Llk1

Llk2

io

i1

i2

Qa

Qb

SR1

SR2v

avb

Cclamp

Vclamp

Iout

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-

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1:n:n

R

+

-

Vg

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vsw

is

Ls

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io

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Vout

Iout

+

-

+�

1:n:n

R

+

-

Vg

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vsw

is

Ls

Lm

io

i1

i2

SR1

SR2

Cf

Vout

Iout

ix

Fig. 2. Active clamp LLC resonant converter

978-1-4673-4916-1/13/$31.00 ©2013 IEEE

vsw

i1

t0

Vg

t

t

t

is

0

i2

vth

0

/2nkVclamp

Q1

SR1, Q

b

Q1

Q2

Qa , SR

2

Q2

Qa , SR

2SR

1, Q

b

0t1 T

s

0.5io

/2nk-Vclamp

0.5ix

0.5Llk<i

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+ -v

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is

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o

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(a)

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+

-

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Iout

Rload

0.5rsec

c

Co

+

-

vout

Iout

Rload

non

Io

(b)

0.5rsec

t2

t3

t4

CfcI

o

4Cclamp

(a)

+

-

0.5vclamp

+

-

vout

Iout

Rload

R//

Rdamp

c

Fig. 3. Converter models: (a) high-frequency model, and (b) averaged model

vsw

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t0

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t

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/2nkVclamp

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(a)

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+

-

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Iout

Rload

0.5rsec

c

Co

+

-

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Iout

Rload

non

Io

(b)

0.5rsec

t2

t3

t4

CfcI

o

4Cclamp

(a)

+

-

0.5vclamp

+

-

vout

Iout

Rload

R//

Rdamp

c

Fig. 4. Typical waveforms in one switching cycle

hysteretic control of one module using a 1 MHz, 24 V-to-3.3 V, 5.5 W experimental prototype, as well as simulationresults for a twenty-module system. Conclusions are given inthe final section.

II. CONVERTER MODELING

The on/off control of the active clamp LLC resonant con-verter requires two types of models. The first one is a high-frequency model including details of the four sub-intervals ina switching cycle. The second one is an averaged model forthe output current, as well as the output and clamp voltages.From this averaged model, the multiple-parallel-module dc-dcsystem model can be derived, leading to a system compensatordesign approach.

A. High-frequency model

According to [15], an active-clamp LLC converter can bemodeled as an equivalent LC circuit shown in Fig. 3a, where

k = 1 +Llk/2n

2

Lm, (1)

TABLE IEXPERIMENTAL PROTOTYPE COMPONENTS LIST

n 0.4Cs (nF) 11.6Ls (µH) 3.14Lm (µH) 6.90Llk (nH) 320Cclamp (µF) 4.4Cf (µF) 47Magnetics core 0L42020UGQ1, Q2 CSD17313Q2SR1, SR2, Qa, Qb CSD16301Q2Gate driver EL7104ADC for vout THS1030CDWADC for vsw AD9280ARSZ

Leq = Ls +[(Llk/2n

2)//(Lm)]. (2)

The voltage vsw and vth waveforms can be found in Fig. 4,along with the list of switches to be turned on during each sub-interval. In order to study the relationship between primary-side current is and the current ix transferred to the secondarysides, another equation is required,

disdt

= nkdixdt

+ kvthLm

. (3)

Note that current ix is a component of the secondary sidecurrents: i1 = 0.5(io + ix) and i2 = 0.5(io − ix), where iois the unfiltered output current. State plane analysis is used todetermine t1→4 in steady state, in order to obtain zero-currentswitching on the secondary side devices, and to calculate aturn-on timing sequence to reach steady state within the firstswitching cycle [15].

B. Averaged model

By averaging the unfiltered output current io, output voltagevout and clamp voltage vclamp over Ts, the averaged modelshown in Fig. 3b is derived from a set of equations:

Cfd 〈vo(t)〉

dt= 〈io(t)〉 − Iout (4)

Cclampd 〈vclamp(t)〉

dt= 0.5 [|〈ix(t)〉| − 〈io(t)〉] (5)

Llkd 〈io(t)〉dt

= 〈vclamp(t)〉 − 2 〈vout(t)〉 − rsec 〈io(t)〉 , (6)

where rsec is the total parasitic resistance on one secondaryside. A simpler averaged model based on this derivation ispresented and verified in section III-B.

III. CONTROLLER DESIGN FORMULTIPLE-PARALLEL-MODULE DC-DC SYSTEM

A. Hysteretic control of one module

A 1 MHz, 24 V-to-3.3 V, 5.5 W experimental prototypeis built to evaluate hysteretic on/off control of one module.Table I lists the resonant tank values and device part numbers.In the control loop diagram (Fig. 5), the hysteresis band is

Vref + -

e c Gate-timing

Converter

vsw H2

H1

vout t1 4

Vref + -

e non N-module

system

vout

nq

Compensator

non 1 2 0

1

2

…

…

nq

c1

c2

cN

…

N

H

Fig. 5. Hysteretic control diagram for one module

vsw (20V/div)

is (2A/div)

vout, ripple (50mV/div)

vclamp, ripple (100mV/div)

(a) 4μs/ horizontal div

vsw (20V/div)

is (2A/div)

vout, ripple (50mV/div)

vclamp, ripple (100mV/div)

45k

130k

115k

vout, ripple (50mV/div)

(b) 10ms/ horizontal div

100mV

vout, ripple

vclamp, ripple

60mV

(c) 40μs simulation time

(a) 10μs/ horizontal div

vout, ripple (50mV/div)

(c) 10ms/ horizontal div

vout, ripple

100mV

vclamp, ripple

136mV

(b) 100μs simulation time

Fig. 6. Hysteretic control of one module: (a) experiment at 90% load, (b)simulation of simple model at 90% load , and (c) experiment at no load

chosen to be ±50 mV. The gate-timing block is implementedas follows: at the rising edge of control signal c, the gate-timing block reads the initial value of vCs

, and uses a six-row look-up table to determine the turn-on timing sequencethat brings the converter to steady state operation within thefirst switching cycle; after that, steady state timing is used.The initial vCs can be obtained easily by sensing voltage vswacross the input switching node.

Fig. 6a shows experimental waveforms of switching nodevoltage vsw, primary-side current is, output voltage ripplevout,ripple, and clamp voltage ripple vclamp,ripple at 90% load(or 1.5 A). It can be seen that is comes close to steady state in

88

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90

91

92

0.0 0.5 1.0

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(%

)

Normalized output power (Pout/Pmax)

N=1

N=2

N=4

N=8

88

89

90

91

92

0.0 0.2 0.4 0.6 0.8 1.0

N=1

N=2

N=4

N=8

Normalized output power (Pout/Pmax)

Eff

icie

ncy (

%)

Fig. 7. Efficiency at various loads of one module (experimental) and multiple-module systems (projected)

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Iout

Rload

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c

Co

+

-

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Iout

Rload

non

Io

(b)

0.5rsec

t2

t3

t4

CfcI

o

4Cclamp

(a)

+

-

0.5vclamp

+

-

vout

Iout

Rload

R//

Rdamp

c

Fig. 8. Simple averaged models of (a) one module for simulation, and (b)N-module system for compensator design

less than 1 µs. Output voltage varies from 3.25 V to 3.35 V at45 kHz on/off (PWM) frequency. At mid-range load currents,the PWM frequency can reach up to 130 kHz. The controlleris able to regulate output voltage at no load as shown inFig. 6(c). The converter’s efficiency is recorded at variousloads and shown in Fig. 7. Compared to fixed frequency PWM,the hysteretic controller reduces the PWM on/off frequencyat light load, which helps improve the light-load efficiency.Predicted overall efficiency of a system containing up to 8modules is also shown in Fig. 7, based on the fact that insteady state at most one module is operating in the on/offPWM mode while the others are either fully on or off. It is seenthat systems of eight or more modules perform at efficiencyhigher than 90% over a wide load range.

B. Simplified averaged model

The averaged model in Fig. 3b is a third-order system withdamping resistance equal to 0.5rsec. Based on the observationfrom experiments that the output voltage is well-damped, theleakage inductance in the averaged model can be omitted.Additionally, since |〈ix(t)〉| can quickly reach its steady stateIo (maximum supply current of the converter), the output isapproximated as a constant current source controlled by the

Vref + -

e c Gate-timing

Converter

vsw H2

H1

vout t1 4

Vref + -

e non N-module

system

vout

nq

Compensator

non 1 2 0

1

2

… …

nq

c1

c2

cN

…

N

H

Fig. 9. Control loop set up for simulation of N-parallel-module system

on/off control signal c. Based on these assumptions, a simplermodel (Fig. 8a) is then obtained and verified by experiments.Figs. 6a and b show an example of how the simple modelpredicts vout and vclamp similar to the experimental results at90% load.

Using the simple averaged model of one module, an idealfirst-order model for an N-parallel-module system is derivedand shown in Fig. 8b, where Co = Cf +4Cclamp. The controlvariable for this system is the number non of on modules.The control-to-output transfer function, from non to the outputvoltage vout is found,

Gvn(s) =IoRload

1 + s1/(CoRload)

=G0

1 + s2πf0

. (7)

C. Controller design

A compensator is designed for a dc-dc system containinga number (twenty, for example) modules in parallel, eachbeing the same 1 MHz, 24 V-to-3.3 V, 5.5 W module. GivenCclamp = 22 µF and Cf = 680 µF respectively, the DCgain and the pole frequency of the control-to-output transferfunction at maximum load are

G0,maxload =VrefN

= 0.165 = −16 dB,

f0,maxload =NIo

2πCoVref= 2.2 kHz .

The compensator can be of PI or PID type. The criteria tochoose a suitable compensator for this application is that thesystem has to respond quickly to a step load transient. A PIcompensator is simpler, while a PID compensator can resultin faster response. This section shows design examples forthese two compensators. A performance comparison is thendiscussed in Section III-D.

The transfer functions of the PI and PID compensators are

GPI(s) = G∞

(1 +

2πfLs

), (8)

0

1 c1

0

20

nq

3.3

3.24

vout (V)

0

1 c20

(b)

0

iload (A) 40

20

vout (V) 3.3

3.24

nq

0

20

(a)

(b)

Set x axis: 1.42ms, 2ms Set x axis: ?ms, ?ms

Set vout axis: 3.225 3.31V

vout (V)

(a)

nq

20

0

3.24

3.3

3.24

vout (V)

nq

20

0 c14

0

1

c15

0

1

c19

0

1

(a)

3.30

Fig. 10. Simulation results for a load step from 0.1 A to 34 A with (a) PIcompensator and (b) PID compensator (100 µs/div)

GPID(s) = G0

(1 + 2πfL

s

)(1 + s

2πfz

)(1 + s

2πfp

) , (9)

respectively. For both controller designs, the cross over fre-quency fc is chosen at 100 kHz (one-tenth the switchingfrequency), and the low-frequency zero fL is set at 730 Hz(one-third the corner frequency f0,maxload). The gain G∞ ofPI compensator can be calculated easily,

G∞ =fc

f0,maxloadG0,maxload= 278. (10)

For the PID controller, the phase margin ϕm is set at 50◦,which yields G0 = 596, fz = 215 kHz, and fp = 47 kHz,using the methods in [16].

D. Simulation results

The control loop for a twenty-module system is set up inSimulink with built-in PLECS libraries (Fig. 9). A quantizer-with-hysteresis block converts non into a quantized numbernq , and also limits the number range from 0 to 20. The

0

1 c1

0

20

nq

3.3

3.24

vout (V)

0

1 c20

(b)

0

iload (A) 40

20

vout (V) 3.3

3.24

nq

0

20

(a)

(b)

Set x axis: 1.42ms, 2ms Set x axis: ?ms, ?ms

Set vout axis: 3.225 3.31V

vout (V)

(a)

nq

20

0

3.24

3.3

3.24

vout (V)

nq

20

0 c14

0

1

c15

0

1

c19

0

1

(a)

3.30

Fig. 11. Simulation results at load step from 0.1 A to 25 A with (a) PIcontroller and (b) PID controller (50 µs/div)

hysteresis band is chosen to be ±0.3. This value along withcompensator’s cross-over frequency affect the on/off PWMfrequency of one module in steady-state operation. The sensingblock H models an ADC with a sampling rate of 10 MHzand a delay of three sampling periods. The sampled valuesare averaged over Ts/2 to cancel the switching ripple in vout.

Simulation results with the designed PI and PID controllersare shown in Fig. 10 for a full load step (0.1 A to 34 A), and inFig. 11 for a 75% load step (0.1 A to 25 A). In the simulationwaveforms, ci is the on/off control signal of the correspondingith module. Table II compares the two controllers’ performancein terms of: (1) the time delay from the load step moment towhen nq starts ramping up, (2) the time it takes nq to rampfrom 0 to its steady-state value, (3) undershoot percentage ofvout, (4) the time it takes vout to settle within 1% of steadystate value, and (5) steady-state PWM frequencies of a moduleat light load and heavy load. Note that the delay time includes0.3 µs delay of the ADC.

At full load step, the PI controller has the same outputvoltage undershoot as the PID one, and slightly shorter delay

TABLE IIPERFORMANCE COMPARISON BETWEEN PI AND PID CONTROLLERS

Full load step 75% load stepPI PID PI PID

tdelay of nq (µs) 0.4 0.6 0.4 0.5trise of nq (µs) 4.7 2.2 5.4 2.3vout undershoot (%) 2 2 1.5 1.5t1%settle of vout (µs) 163 97 96 5PWM frequency (kHz)- Before load step 45 34 45 34- After load step 132 86 186 115

time. However, its rise time and settling time are about twotimes longer compared to the PID controller. Besides, itstarts on/off PWM of the twentieth module at an increasingfrequency before vout reaches 1% of the steady-state value.On the other hand, the PID controller turns on the maximumnumber of modules quickly, and then on/off modulates thetwentieth module when vout settles. The dynamic performancefor the full load steps is affected by saturation of the controlaction, i.e., saturation of the number of on modules. Theconverter configuration is not capable of supplying loads largerthan the sum of the module output currents. A simulation at75% load step is performed to evaluate the performance ofthe compensators away from saturation. The results are shownin Fig. 11. In this case the PID controller has a faster risetime and turns on more modules at transient (up to nineteenmodules). This results in significantly faster dynamics, wherevout reaches 1% steady state in 5 µs (one nineteenth thesettling time of PI controller). During the first 12 µs transienttime before nq reaches its steady state, the pulse widths ofall on/off conttrol signals are longer than twice the modules’switching cycle, which is achievable in practice.

IV. CONCLUSIONS

This paper presents methods to model and design an on/offcontroller for a multiple-parallel-module dc-dc system usingactive-clamp LLC resonant converter modules. The architec-ture and the control method yield high overall efficiencyand fast transient responses. Two converter models are in-troduced for different purposes: (1) a high-frequency modelto determine gate timing sequence leading to fast moduleturn-on capability, and (2) an averaged model to assist thesystem control loop design. The standard frequency-domaintechniques is proposed to design system control loop, using thenumber of on modules nq as the control variable The modelsand the on/off control method are verified by experiments on a1 MHz, 24 V-to-3.3 V, 5.5 W active-clamp LLC module proto-type. Steady-state and transient response simulation results areshown for a point-of-load dc-dc system consisting of twenty1 MHz, 24 V-to-3.3 V, 5.5 W LLC modules operating inparallel. The results show that a PID compensator can regulatethe output voltage in steady state, and has a faster responsethan a PI controller upon large step load transients.

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