Implementation of Dithering DigitalRipple Correlation Control for

PV Maximum Power Point Tracking

Christopher Barth, Robert C.N. Pilawa-Podgurski

UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN

URBANA, ILLINOIS 61801

EMAIL: cbarth2@illinois.edu

Abstract—This work demonstrates a method for rapid max-imum power point tracking in photovoltaic applications usingdithered PWM control. Constraints imposed by power consump-tion, cost and component size, limit the available PWM resolutionof a power converter, and may in turn limit the MPP trackingefficiency of the PV system. PWM dithering can be used toimprove average PWM resolution. However, additional trackingdelays are also introduced. By applying digital dithering ripplecorrelation control to the ripple caused by PWM dithering itis possible to achieve high tracking speed in addition to highPWM resolution. We present a theoretical derivation of theprinciples behind DDRCC, as well as experimental results thatshow excellent tracking speed and accuracy with basic hardwarerequirements.

I. INTRODUCTION

The need for maximum power point tracking (MPPT) arises

from the non-linear I-V curve of photovoltaic panels, and the

fact that panel characteristics change with insolation, tempera-

ture and age. Effective MPPT requires adequate measurement

resolution of the power flowing into the converter as well as

sufficient resolution on converter control. The control resolu-

tion of a switching power converter is determined by the PWM

resolution of the controller. Many modern systems depend on

microprocessor-based controllers that employ digital counter-

based PWM. In these implementations, the PWM resolution

of the converter is proportional to the clock speed of the

microcontroller and inversely proportional to the switching

frequency of the converter. Because microcontroller clock

speed may be limited by hardware constraints in low cost,

low power applications and current trends toward integration

often require smaller passive components and accompanying

higher switching speeds, there are instances when the available

PWM resolution becomes a constraining factor in efficient

MPPT operation. Moreover, for high efficiency operation,

control losses must be kept low. In low power applications

the power consumed by a high-frequency microcontroller can

be significant [1], [2].

This work was supported in part by the Illinois Center for a Smarter ElectricGrid, through Illinois Department of Commerce and Economic Opportunity(DCEO) under grant 12-197001

In these cases the technique of PWM dithering can be used

to increase the effective resolution of the converter without

increasing digital logic frequency. By alternating between

adjacent native PWM ratios at a predetermined dithering fre-

quency, an intermediate average PWM ratio can be obtained.

Unfortunately, the use of dithering imposes additional delay on

the update speed of the MPPT algorithm as both the switching

ripple and the dithering ripple must be adequately averaged in

order to achieve a high resolution measurement. This creates

a trade-off between PWM resolution and tracking speed.

Ripple correlation control (RCC) has been shown to be an

adaptable approach for system optimization in the presence

of a sustained ripple [3]. Further work has demonstrated that

RCC is exceptionally well suited for stable digital implemen-

tation [4]. This work builds on the theoretical introduction of

dithering digital dipple correlation control (DDRCC) [5] and

demonstrates that DDRCC can be applied to the system ripple

created by PWM dithering to achieve excellent PV MPPT

speed and convergence in MPPT systems which use dithered

PWM control. Additionally, by applying RCC to the average

ripple caused by dithering, DDRCC avoids the limitations

placed on switching frequency in RCC controlled converters

[6].

II. DITHERING FOR INCREASED EFFECTIVE RESOLUTION

As mentioned previously, precise MPPT requires good

converter control resolution and by extension, finely adjustable

PWM signal. The duty ratio resolution of a counter-generated

PWM signal is limited by the clock speed of the microcon-

troller as shown in (1). For example, an 8 MHz counter clock

driving a 250 kHz PWM signal results in a resolution limit of

3.132%.

FPWM

Fclk= ∆Dmin (1)

One well-known technique to circumvent this limitation

is to dither between the available duty ratios at appropriate

intervals, in order to generate a PWM signal with an average

value between the duty ratios available in hardware [7]. The

978-1-4673-4916-1/13/$31.00 ©2013 IEEE

0% 20% 40% 60% 80% 100%

20%

40%

60%

80%

100%

Desired Duty Ratio

Available Duty Ratio

Native resolution

Dithered resolution 52%

53%

54%

55%

Δ Dmin Native = 3.13%

Δ Dmin Dither = 0.079%

Fig. 1. Measurements of average duty ratio resolution with both native PWMand dithering.

Time

Scaled Amplitude

PWM S ignal

Panel Current

Panel Voltage

t = RdTd

t = 0 t = Td

Fig. 2. Simulation of dithering voltage and current waveforms resulting fromchanges in PWM duty ratio.

percentage of time the converter runs at either duty ratio is ad-

justed to generate an average duty ratio between the two native

values of the hardware. In theory this approach generates an

arbitrarily fine PWM resolution as shown in (2). In practice

the increase in resolution is limited by the input capacitance

of the converter and the maximum acceptable ripple. For the

PWM generator described above, averaging over 40 cycles

allows for an average resolution of 0.078%. Figure 1 shows

measurements of the duty ratios attainable with both native

resolution and dithering for an MSP430G2553 microcontroller

running at an 8 MHz clock speed and generating a 250 kHz

PWM signal.

∆Dmin

N= ∆Ddithered (2)

As the MPPT converter dithers between native duty ratios,

the average current and voltage of the panel will change

approximately linearly in time, with the current rising and

voltage falling over periods of high duty ratio, and the reverse

over periods of low duty ratio. This ripple in the average I

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Current [A]

Power [W]

A BP*

I*

Fig. 3. Power vs. current characteristic for PV panel under illumination inexperimental setup.

and V of the PV panel can be used as a means of maximum

power point tracking and will be explored in this work.

Figure 2 shows a simulation of the input current and voltage

of a buck converter when it is used as a PV power converter

with dithering applied. The dithering period is denoted as Td,

and extends from the time at which the converter shifts to the

native duty ratio which is just above the desired average duty

ratio until the converter has finished running at the ratio which

is just below the desired average duty. The native duty ratio

above the desired duty ratio can be referred to as the “high”

duty ratio, and the one below as the “low” duty ratio The

dithering ratio, denoted as Rd marks the point in the dithering

period at which the converter transitions from the high to the

low duty ratio. By adjusting the dithering ratio (not to be

confused with the duty ratio) the converter is able to vary

the average PWM duty ratio between the high and low native

values.

III. PRINCIPLES OF DDRCC

The principle of ripple correlation control has been pre-

sented in both analog and digital form [3], [4]. With some

modifications, the concept of RCC can be extended to an

average basis for application to the ripple resulting from

converter dithering. The main points of the derivation will be

repeated here to illustrate the approach.

Extracting maximum power from a PV array requires the

panel to be operated at some optimal value of current and

voltage. Since I and V are interdependent, panel power can

be plotted as a function of either variable. Figure 3 shows the

power extracted from a 20 W, 9.5 V, solar panel in the lab over

a range of currents [8]. It is clear that power is maximum at a

value of I* for which the derivative of power with respect to

current is zero. For portions of the power vs. current graph to

the left of I*, for instance the point marked A, the derivative

of power with respect to current is positive. Conversely, the

derivative of power with respect to current is negative for all

points on the curve with I greater than I*, such as at point

B. These relationships are presented in (3) and (4).

dP

dI> 0 =⇒ I < I∗ (3)

dP

dI< 0 =⇒ I > I∗ (4)

The power converter input current (and thus the PV panel

current) is proportional to the duty ratio which makes it

possible to traverse the power curve of Fig. 3 by controlling

the duty ratio. For a buck converter, equations (3) and (4)

can be restated as shown in (5) and (6) to determine the

direction of the change in duty ratio required to reach the

panel maximum power point. The direction of inequalities will

change depending upon the type of converter used.

dP

dI> 0 =⇒ D < DMPP (5)

dP

dI< 0 =⇒ D > DMPP (6)

For a buck converter, panel current increases as the duty

ratio increases, and the sign of the required change in duty

ratio is the same as the sign of dPdI

. Therefore, integral control

with a suitable scalar gain can be applied over time to drive

the average converter duty ratio to DMPP as shown in (7).

The duty ratio will be adjusted until dPdI

is equal to zero.

This relationship holds as long as I(D) is monotonic and the

average duty ratio, D, is adjustable in time [4].

D = k

∫

dP

dIdt (7)

Since the derivative of (7) is not easily measurable, this

expression can be restated by multiplying by a positive con-

stant. Since measurement of power and current are routinely

performed in the time domain, the term ( dIdt

)2 can be used to

restate (7) in terms of derivatives with respect to time as shown

in (8) [4]. Note that ( dIdt

)2 is not only positive, but also constant

with respect to the power vs. current relationship depicted in

Fig. 3. Hence it does not effect the ability of (7) to drive the

duty ratio to DMPP .

D = k

∫

dP

dI

dI

dt

dI

dtdt = k

∫

dP

dt

dI

dtdt (8)

A deeper intuition for (8) and the operation of DDRCC in

general can be seen by considering the relationship depicted

in Fig. 3 as power and current are changed over time. As

discussed, an increase in the panel current for I < I* will

result in an increase in power. With prime denoting the new

value and nought the original, this can be stated as Po < P ′ as

long as Io < I ′ and Io < I*. Conversely, Po > P ′ for Io > I*

also holds. These relations can be combined to determine the

direction of change in I required, and hence the direction of

change in D required to reach the maximum power point [6].

dI

dt

dP

dt> 0 =⇒ I < I∗ =⇒ D < DMPP (9)

dI

dt

dP

dt< 0 =⇒ I > I∗ =⇒ D > DMPP (10)

The time-based approach in (9) and (10) therefore yields (8)

directly, however the underlying relationship between power

and current which is the basis for DDRCC is somewhat

obscured by the introduction of time derivatives.

Equation (8) can be simplified by considering that the aver-

age panel current and voltage change approximately linearly

as the converter dithers. Noting the waveforms in Fig. 2, it

is justifiable to approximate dIdt

as a positive and a negative

constant over the region of high and low duty ratio respectively

as shown in (11) [4].

dI

dt=

S+ mod(t, Td) ∈ [0, RdTd)S− mod(t, Td) ∈ [RdTd, Td)

(11)

By making use of (11) and taking the initial duty ratio into

account, the integral in (8) can then be rewritten as the sum

of two integrals each multiplied by the corresponding constant

current slope as shown in (12). Symbolic evaluation then leads

to (13).

D(t) = D(0) + kS+

∫ RdTd

0

P dt+ kS−

∫ Td

RdTd

P dt (12)

D(t) = D(0)+kS+(P (RdTd)−P (0))+kS−(P (Td)−P (RdTd))(13)

When the converter is operating in equilibrium, the variation

in average values of input voltage, current, and power will all

be periodic over the dithering cycle. This means that (14) and

(15) will hold.

I(0) = I(Td) (14)

P (0) = P (Td) (15)

In order for this to be true, the product of the rise time

of the average current and the positive slope of the average

current must be equal to the product of the period over which

the current is decreasing multiplied by the rate of decrease. Or

equivalently, ∆t ∗ dIdt

must be equal on the falling and rising

slope. Because the period of rising current is given as TdRd,

and that of the falling current is Td(1 − Rd), it is possible

to solve for the negative slope of the current in terms of the

dithering ratio (Rd) and the positive slope as shown in (16).

S+Rd = S−(Rd − 1) =⇒ S− =−S+Rd

1−Rd

(16)

Equations (15) and (16) can then be used to simplify (13)

into (17).

D(t) = D(0) +kS+

1−Rd

(P (RdTd)− P (0)) (17)

Depending upon the resolution of the dithering process,

and the constant gain (k) used, there may be no discernible

difference between using the magnitude of the difference in

(17) and only the sign of the difference with a constant

gain. With an appropriate k′ value, (18) can be considered

functionally equivalent to (17).

0.01 0.012 0.014 0.016 0.018 0.02 0.022

15.63%

18.75%

21.88%

25%

Time [sec]

Increasing Average Duty

3−Way TransitionInstaneous Duty Ratio

0.0165 0.017 0.0175 0.018 0.0185

15.63%

18.75%

21.88%

25%

Increasing Average Duty

3−Way Transition

Fig. 4. Three-Way dithering process. Left plot shows instantaneous duty in time as average duty is progressively increased. Right plot shows closeup ofthree-way transition used to maintain ripple.

D(Td) = D(0) + k′sgn(P (RdTd)− P (0)) (18)

Equation 18 is the essence of DDRCC. By sampling the

power of the panel at the beginning of the dithering cycle

(P (0)) and at the transition in duty ratio (P (RdTd)), and

then adjusting the duty ratio accordingly, the converter will

iteratively converge to the optimal average duty ratio for MPP

operation.

Because DDRCC makes use of the dithering frequency

instead of the switching frequency to perform MPPT, the

DDRCC dithering frequency/tracking frequency can be cus-

tomized at design time or adaptively during operation.

DDRCC is well-suited for mobile applications, because the

tracking speed of the converter can be a respectable percentage

of the switching frequency, and the fact that the dithering

strategy is most applicable to low-power applications, and low-

cost control hardware.

IV. HARDWARE IMPLEMENTATION

In traditional dithering approaches, when the desired duty

ratio is equal to a native value, the converter would typically

stop dithering and run at a constant duty ratio. Since ripple is

essential for DDRCC operation, the dithering approach must

be modified to maintain a ripple. In the present implementa-

tion, the required dither is ensured by entering a 3-way mode

in which the instantaneous duty ratio is switched between the

native resolution value needed and the native values above

and below. In practice, the three-way mode must be extended

beyond the single desired duty ratio at which it is required

to maintain ripple, in order to maintain the continuity of the

average signal. When the average duty ratio has increased

beyond the transition region, the system will return to two-

way dither. This sequence of increasing the dithering ratio and

then using a 3-way pattern repeats as the average duty ratio

is increased. The transition to three-way mode and the timing

of transitions during the three-way mode are chosen such that

the average duty ratio increases linearly.

TABLE ICOMPONENT VALUES FOR CONVERTER

Device Value/Model Manufacturer

Microcontroller MSP430G2553 Texas Instruments

Op amp LMP8602 Texas Instruments

DrMOS FDM6704V Fairchild

Rsense 0.05 Ω Vishay

Lbuck DR127, 22 µH Cooper Bussman

Rdiv1 7.5 kΩ Yageo

Rdiv2 2.4 kΩ Yageo

C1 2 nF Taiyo Yuden

Cin 44 µF Taiyo Yuden

Cout 20 µF Taiyo Yuden

R1, R2 8.2 kΩ Yageo

C2, C3 2.2 µF Velleman

Rload 1.4 Ω

Solar Panel

−+

Op Amp

R2R1

C1

C2

Microcontroller

DrMOS

C3

Rsense Lbuck

Cout

Rdiv1

Rdiv2

Cin

Rload

Fig. 5. Schematic of the buck converter used for DDRCC verification.

Figure 4 shows a simulated plot of the instantaneous PWM

duty ratio used by the converter micrcontroller as the dithering

ratio (Rd) is increased over time [9]. The y-axis of Fig. 4 gives

the instantaneous duty ratio of the converter. In this example

the PWM counter is running at 8 MHz, and the converter at

a switching speed of 250 kHz. Therefore, there are 32 clock

pulses per PWM period, and a native duty ratio resolution of

3.13%. However, by adjusting the amount of time the converter

HP6060BMagna-PowerPQ375-27

Buck Converter

Electronic LoadDC Power Supply

Agilent 34410A

Agilent 34410A

V DC

I DC

Rload

Fig. 6. Converter test setup.

0 0.5 1 1.5 2 2.50

2

4

6

8

10

12

Panel Voltage [V]

Time [S]0 0.5 1 1.5 2 2.5

0

0.5

1

Panel Current [A]

Panel Current

Panel Voltage

Fig. 7. Current and voltage during MPP convergence.

operates at the native duty ratios of 18.75% and 21.88%, the

average duty ratio can be set at an intermediate value. In

Fig. 4, the converter is averaging over 40 PWM switching

cycles. Therefore, as seen in (2) the average effective duty

ratio resolution is increased to 0.078%.

Figure 5 shows a schematic of the buck converter used

to demonstrate DDRCC, and component values are given in

Table I. DDRCC control for the buck converter was imple-

mented on an MSP430G2553. The G2553 microcontroller is

part of Texas Instruments’ Value Line series and is available in

quantities of 2000 for approximately $1.00 USD. It was chosen

to demonstrate the minimal hardware required to perform

DDRCC.

V. EXPERIMENTAL RESULTS

Panel illumination for testing was provided by DC powered

halogen lights to eliminate the 120 Hz ripple in panel power

caused by AC illumination. The complete test setup is depicted

in Fig. 6.

The MPP convergence of the DDRCC algorithm was tested

over a range of panel power levels by adjusting the light-

ing intensity on the panel. The panel maximum power was

identified by an automated I-V sweep conducted with an

HP6060B electronic load and Agilent 34410A multimeters

to measure current and voltage. After measuring Pmax, the

converter was started and allowed to converge to the MPP.

Figure 7 shows panel current and voltage as the duty ratio

of the converter is raised to DMPP. In this implementation the

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6

7

Time [S]

Power [W]

Fig. 8. DDRCC algorithm converging to the MPP.

duty ratio of the converter is adjusted each dithering cycle, so

by decreasing the number of PWM cycles per dithering cycle

the convergence speed could be increased. As shown in (2)

this would also decrease the effective control resolution of the

converter. Figure 8 shows a plot of panel power vs. time as

panel power converges to the MPP.

Figure 9 shows the operation of the converter when it is

rippling with a duty ratio below DMPP (left), at DMPP (center),

and above DMPP (right). Arrows on each graph highlight the

logic waveform at the top of the screen which marks the

intervals of high duty ratio. This logic signal returns low when

the converter enters low duty ratio for normal operation, or

mid-duty ratio for three-way operation.

As outlined by (18), the DDRCC algorithm measures con-

verter input power at time t = 0 and t = RdTd corresponding to

the beginning and end of the period of high duty ratio. During

this interval, average panel current flowing into the converter

rises, and average panel voltage falls. If P(0) is less than

P(RdTd) it is clear that the panel MPP exists at some higher

current and average duty ratio, than the present operating point.

This situation is shown in the left plot of Fig. 9. As indicated

by (18) the DDRCC algorithm will raise the average duty ratio

of the converter.

When P(RdTd) is equal to P(0), a point of peak power has

occurred during the interval and the converter is operating

at the maximum power point. This is the case shown in the

center plot of Fig. 9. In this instance, the difference portion of

(18) will evaluate to approximately zero and, with a tolerance

implemented, the average duty ratio of the converter will be

unchanged.

The right plot of Fig. 9 shows the operation of the converter

when the duty ratio is above the MPP. It is evident that P(RdTd)

is lower than P(0), which means that the average value of the

duty ratio must be lowered to reach the maximum power point

as indicated by (18).

In addition to assessing each case from the perspective of

(18), it is also helpful to apply the relationships given by (9)

and (10). In the left plot of Fig. 9 it can be seen that dIdt

dPdt

> 0indicating that the average current must be raised to reach the

MPP according to (9). Conversely in the right plot, dIdt

dPdt

< 0indicating that the average duty must be lowered to operate

At MPP Above MPPBelow MPP

Power

Voltage

Current

t=0 t=RdTd t=Td t=0 t=RdTd

t=Td t=0 t=RdTd t=Td

High Duty

Low Duty

Fig. 9. Oscilloscope screenshot of dithering voltage and current, and power waveforms when the average duty ratio (D) is below, at, and above the MPPduty ratio. Note: DC levels are shifted in each plot for suitable viewing, and current scale on right plot has been increased.

the system at the ideal current, I*, according to (10).

TABLE IIEXPERIMENTAL TRACKING EFFICIENCY

Pmpp [W] DDRCC ηMPPT P&O ηMPPT

5.8755 99.87% 97.55%

4.6368 99.84% 97.89%

3.2238 99.97% 96.82%

2.6085 99.50% 97.04%

1.3404 96.26% 93.18%

A comparison between the tracking efficiency of undithered

perturb and observe (P&O) and dithered DDRCC is shown

in Table II [10]. Tracking efficiency (ηMPPT ) is as defined

in (19). This data is acquired using automated triggering of

Agilent 34410A multimeters to average the power flowing

into the converter for several seconds after the converter has

converged to the MPP. It can be seen that the DDRCC tracking

efficiency is excellent over the range tested, and an average of

2.6 percentage points higher than undithered P&O. Both algo-

rithms were tested at a microprocessor clock speed of 8MHz

and a 250 kHz converter switching frequency. It can be seen

that both methods have a decreased efficiency at 1.3 W of input

power. At this very low power level, MPPT performance is

not limited by PWM resolution, but rather by the resolution of

current sensing. As is to be expected, in this situation DDRCC

fares no better than conventional techniques. Increased light

load tracking efficiency would require improved hardware for

current sensing in this implementation.

ηMPPT =Pavg

PMPPT

(19)

It should be noted that the circuit requirements for both

algorithms are the same except for the cutoff frequency of

the low-pass filter at the input of the ADC. When applying

DDRCC control, the objective of the low-pass filter is to

remove extraneous switching noise. It is not necessary to

completely filter the switching waveform because the ADC

measurements are triggered by the PWM module and occur

at the same location in each dithering cycle. By sampling at

approximately the same location on each dithering and switch-

ing cycle the switching waveform stays consistent between

samples and the change in the average ripple is observable.

When performing P&O, the low-pass filter is designed such

that it removes both the switching and dithering signal. This

places a delay in the maximum MPPT speed because the

controller must wait multiple dithering cycles in order to take

advantage of the increased resolution provided by dithering.

Because it is common for PV panels with bypass diodes to

have multiple power peaks during periods of partial shading,

a commercial implementation of DDRCC would likely use a

mode switching algorithm in which the converter first adjusts

its duty ratio for a panel voltage of around 70% of Voc and

then converges to the maximum power point using DDRCC.

This would be necessary to prevent the DDRCC algorithm

from converging to one of the lower power peaks instead of

the true global maximum power point [4].

VI. CONCLUSIONS

DDRCC has been shown to be an excellent method of

accomplishing high control resolution and fast MPPT in PV

applications. Using dithering, DDRCC is able to achieve

high control resolution at low controller clock speeds and

high PWM frequencies. By conducting maximum power point

tracking based on dithering ripple, DDRCC is able to achieve

fast convergence and tracking at a significant fraction of the

switching frequency. Instead of averaging the dithering signal

and then perturbing the duty ratio to track the maximum power

point, DDRCC uses carefully timed measurements to track at

the fastest rate achievable in a dithered system.

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