![Parallel VLSI CAD Algorithmszhuofeng/EE5900Spring2012... · Parallel VLSI CAD Algorithms Lecture 1 Introduction ... Various IEEE journal and conference papers: IEEE[1] Various IEEE](https://static.fdocuments.net/doc/165x107/5e88f1299475ec1f5a74fb96/parallel-vlsi-cad-algorithms-zhuofengee5900spring2012-parallel-vlsi-cad-algorithms.jpg)
Ieee 2012 titles for vlsi
2
Further more details visit : http://www.temasolution.com/downloads.html send your request to : [email protected] 28,South Usman Road,, TNagar, Chennai-17. Ph : 044-43855940 Mobile : +91-9042085008 Web : www.temasolution.com email : [email protected] S.NO PROJECT TITLE CODE YEAR VLSI 1. Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees VLSI01 2012 2. A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time VLSI02 2012 3. Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master– Slave Flip-Flops VLSI03 2012 4. Hierarchical Design of an Application-Specific Instruction Set Processor for High- Throughput and Scalable FFT Processing VLSI04 2012 5. Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials VLSI05 2012 6. VL Architecture of Arithmetic Coder Used in SPIHT VLSI06 2012 7. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders VLSI07 2012 8. Loop Acceleration Exploration for ASIP Architecture VLSI08 2012 9. Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis VLSI09 2012 10. A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security VLSI10 2012 11. Pipelined Parallel FFT Architectures via Folding Transformation VLSI11 2012 12. Scalable Hardware Trojan Diagnosis VLSI12 2012 13. Transactions Briefs: Novel Interpolation and Polynomial Selection for Low- Complexity Chase Soft-Decision Reed-Solomon Decoding VLSI13 2012 14. A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio Receivers VLSI14 2012 15. Optimizing Floating Point Units in Hybrid FPGAs VLSI15 2012 16. Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance VLSI16 2012 17. Transactions Letters: Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC Codes VLSI17 2012 18. Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators VLSI18 2012 19. FPGA-Based Track Circuit for Railways Using Transmission Encoding VLSI19 2012 20. Nonlinear Trellis Codes for Binary-Input Binary-Output Multiple-Access Channels with Single-User Decoding VLSI20 2012 21. A Novel All-Digital Multichannel Multimode RF Transmitter Using Delta-Sigma Modulation VLSI21 2012 22. A Subspace-Based Two-Way Ranging System Using a Chirp Spread Spectrum Modem, Robust to Frequency Offset VLSI22 2012 23. Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems VLSI23 2012 24. The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures VLSI24 2012
-
Upload
soundar-msr -
Category
Education
-
view
90 -
download
2
Transcript of Ieee 2012 titles for vlsi
Further more details visit : http://www.temasolution.com/downloads.html
send your request to : [email protected]
28,South Usman Road,, TNagar, Chennai-17. Ph : 044-43855940 Mobile : +91-9042085008 Web : www.temasolution.com email : [email protected]
S.NO PROJECT TITLE
CODE YEAR
VLSI 1. Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock
Trees VLSI01 2012
2. A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan
Activation Time
VLSI02 2012
3. Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops
VLSI03 2012
4. Hierarchical Design of an Application-Specific Instruction Set Processor for High-
Throughput and Scalable FFT Processing
VLSI04 2012
5. Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials
VLSI05 2012
6. VL Architecture of Arithmetic Coder Used in SPIHT
VLSI06 2012
7. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
VLSI07 2012
8. Loop Acceleration Exploration for ASIP Architecture
VLSI08 2012
9. Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis
VLSI09 2012
10. A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set
for Embedded Network Security
VLSI10 2012
11. Pipelined Parallel FFT Architectures via Folding Transformation
VLSI11 2012
12. Scalable Hardware Trojan Diagnosis
VLSI12 2012
13. Transactions Briefs: Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding
VLSI13 2012
14. A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio
Receivers
VLSI14 2012
15. Optimizing Floating Point Units in Hybrid FPGAs
VLSI15 2012
16. Investigating the Impact of Logic and Circuit Implementation on Full Adder
Performance
VLSI16 2012
17. Transactions Letters: Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC Codes
VLSI17 2012
18. Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width
Modulators
VLSI18 2012
19. FPGA-Based Track Circuit for Railways Using Transmission Encoding
VLSI19 2012
20. Nonlinear Trellis Codes for Binary-Input Binary-Output Multiple-Access Channels
with Single-User Decoding
VLSI20 2012
21. A Novel All-Digital Multichannel Multimode RF Transmitter Using Delta-Sigma
Modulation
VLSI21 2012
22. A Subspace-Based Two-Way Ranging System Using a Chirp Spread Spectrum
Modem, Robust to Frequency Offset
VLSI22 2012
23. Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems
VLSI23 2012
24. The LUT-SR Family of Uniform Random Number Generators for FPGA
Architectures
VLSI24 2012
Further more details visit : http://www.temasolution.com/downloads.html
send your request to : [email protected]
28,South Usman Road,, TNagar, Chennai-17. Ph : 044-43855940 Mobile : +91-9042085008 Web : www.temasolution.com email : [email protected]
25. Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI
Architecture
VLSI25 2012
26. VLSI signal processing oriented segmentation based serial parallel multiplier
VLSI26 2012
27. VLSI Architecture of Arithmetic Coder Used in SPIHT
VLSI27 2012
28. VLSI Friendly ECG QRS Complex Detector for Body Sensor Networks
VLSI28 2012
29. VLSI Based Robust Router Architecture
VLSI29 2012
30. An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
VLSI30 2012
31. A novel VLSI architecture for generation of Six Phase pulse compression sequences
VLSI31 2012
32. VLSI Implementation of Advanced Encryption Standard
VLSI32 2012
33. A Network-Efficient Nonbinary QC-LDPC Decoder Architecture
VLSI33 2012
34. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions
Based on Fast FIR Algorithm
VLSI34 2012
35. Area and power efficient VLSI architecture for DCT
VLSI35 2012
36. CORDIC Designs for Fixed Angle of Rotation
VLSI36 2012
37. Algebraic Soft-Decision Reed–Solomon Decoding
VLSI37 2012
38. Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-
Grid Analysis
VLSI38 2012
39. Architectural design of a highly programmable Radix-2 FFT processor with efficient addressing logic
VLSI39 2012
40. A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers
VLSI40 2012
41. Developing ARM based PDA using Inferno OS
VLSI41 2012
42. FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture
VLSI42 2012
43. A High Performance and Memory Efficient LU Decomposer on FPGAs
VLSI43 2012
