Comparison of Electrical, Optical and Plasmonic

On-Chip Interconnects Based on Delay and Energy Considerations

Abstract—With continued shrinking of device dimensions onchip, major advancements in intra chip interconnect technologyare required to minimize delay, energy dissipation and cross-talk.In this paper, two alternative on-chip interconnect technologyoptions are studied, namely the plasmonic and optical intercon-nects. It is shown that plasmonic interconnects can be 3 ordersof magnitude faster than minimum sized CMOS interconnects atthe 2016 technology node. However, their propagation length islimited to few microns and hence they can be used only as shortlocal interconnects. Energy per bit of plasmonic interconnects isshot-noise limited and it increases exponentially with interconnectlength. Cross-over length beyond which plasmonic interconnectsbecome less energy efficient compared to CMOS interconnects iscalculated. It is found to be 10 µm for Ag cylindrical plasmonicwaveguides of 100-nm diameter embedded in SiO2 dielectric atfree-space wavelength of 1µm. Although plasmonic interconnectsshow potential as future local interconnects, plasmonic switchesare needed for their implementation at the GSI(GigaScale Inte-gration) level. Without plasmonic switches the energy and circuitoverhead associated with signal conversion will be prohibitive.Optical interconnects, on the other hand, are limited to be usedonly at the global level due to the fundamental limitations ontheir size. Although the native interconnect delay of opticalinterconnects is quite less, their bandwidth density is limited dueto the fundamental limitations on the minimum pitch. Wavelengthdivision multiplexing is identified as one of the solutions towardsincreasing the bandwidth density of optical interconnects. Criticallength beyond which optical interconnects offer higher bandwidthcompared to copper interconnects is identified to be equal tothe chip edge in absence of WDM. In presence of 4 channelWDM, the critical length improves to 0.4cm. Critical lengthassessment based on energy comparison with CMOS interconnectis evaluated to be 0.15cm.

Keywords - Interconnects, Optics, Wavelength DivisionMultiplexing, Plasmons

I. INTRODUCTION

SHRINKING of device sizes in integrated circuits hashelped sustain the Moore’s law by increasing the operating

frequency with every technology node. However, with dimen-sional scaling of devices the performance of interconnectsdegrades in a number of parameters. Most prominent are thedelay, energy per bit and cross-talk among wires. The problemassociated with conventional interconnects arises due to thefundamental physics of information transport through theinterconnect. In order to transmit information the interconnectcapacitance needs to be charged and discharged [1], [2].

While scaling of transistors decreases their delay, scaling ofinterconnects increases the delay in the absolute sense. Alsowith scaling, interconnect energy increases relative to that of

the transistors. In this respect, the present work aims to focuson two alternative technology options that can augment CMOSinterconnects on chip - Plasmonic and Optical Interconnects.

Plasmonics is a new technology of manipulating and routinglight at the sub-micron length scales in metallic nanostructuresembedded in dielectric. The propagation velocity of plasmonscan be comparable to the speed of light [3] and hence theyoffer the speed advantages of optical interconnects. It is how-ever equally important to analyze their energy dissipation andalso study some fundamental limitations of plasmonic modepropagation. In this respect, compact models of delay andenergy dissipation are developed. COMSOL [4] simulationsare used to determine the fundamental mode velocity for dif-ferent structures of plasmonic waveguides. Finally cylindricalwaveguide of Ag embedded in dielectric and metal-insulator-metal waveguide were used as the waveguides of choice forcomparison with CMOS interconnects.

Optical interconnects have been widely studied as alterna-tive solutions to chip-chip and chip-board interconnects wherebandwidth is a critical metric [5],[6]. Many researchers havehighlighted their applicability for intra-chip communication[7],[8]. However due to an order of size mismatch betweennanoelectronic components and the wavelength of light, theuse of optical interconnects is restricted to the global in-terconnect level. In the present work, electrical and opticalinterconnects are compared using delay, bandwidth density andenergy dissipation metrics.

This paper is divided in four sections. Fundamentals ofplasmons, and plasmonic waveguides is discussed in SectionII. This section also discusses the modeling and comparisonof plasmonic interconnects with electrical interconnects andchallenges associated with implementation. In Section III,modeling, simulation and comparison of optical interconnectswith CMOS interconnects is provided. Section IV concludesthe paper.

II. PLASMONIC INTERCONNECTS

Surface plasmons are light waves that propagate along thesurface of a conductor, usually a metal. It can be viewed as acoupled electron and light oscillation, also known as “langmuirwaves”. Surface plasmon waves are polarized in the transversemagnetic direction [9]. Silver is the material of choice forconductor since it offers the lowest loss over a wide frequencyspectrum [10]. The most attractive feature of plasmons overconventional dielectric devices is their ability to confine light

Shaloo Rakheja and Vachan Kumar

Georgia Institute of Technology

978-1-4673-1036-9/12/$31.00 ©2012 IEEE 732 13th Int'l Symposium on Quality Electronic Design

to below the diffraction limit and realize high field intensitiesin relatively small volumes. This could help to miniaturizephotonic circuits that have typically been much larger thantheir electronic counterparts. Plasmonic waveguides can alsobe used to propagate light and serve as the interconnect forplasmonic circuits. However, in order to utilize plasmonictechnology as local interconnects on chip, plasmonic switchesneed to be made. Otherwise the overhead associated withsignal conversion (energy and circuit area overhead) will beprohibitive.

A. Plasmonic Waveguides

High speed surface plasmon polariton waves can also beused as communication signal between plasmonic devices onchip. Some useful structures that can help to route light at thenanoscale level are:

• Metal cylinder in dielectric• Metal-Insulator-Metal• Insulator-Metal-Insulator• Chain of metal nanoparticlesIn this paper, the focus is on cylindrical metal waveguide

embedded in dielectric and metal-insulator-metal waveguide.The reason for selecting these two cases is related to optimumpropagation characteristics for these two kinds of waveguides.It has been shown in [11] that reducing the pitch in insulator-metal-insulator and chains of metal nanoparticles waveguidegeometries leads to poor light confinement. The field patternsand propagation characteristics are obtained by simulationusing COMSOLTM [4]. The general definitions of the wavepropagation velocity (vp), the propagation length (Lprop) andthe coupling length (L25%) are as follows:

vp =c

Re(neff )(1)

Lprop =λ0

4πIm(neff )(2)

L25% =λ0/2

|Re(neff,1)−Re(neff,2)|(3)

where neff is the effective mode propagation index, λ0 is thefree space wavelength, neff,1 is the effective mode index ofthe symmetric “supermode” of the two wire system, and neff,2

is the effective mode index of the anti-symmetric “supermode”of the two wire system. L25% is defined as the length at which25% of the plasmon power has been transferred from onewaveguide to the adjacent waveguide.

1) Ag cylinder embedded in a dielectric: The electric fieldpattern of cylindrical waveguides is given in Fig. 1. In caseof two adjacent Ag cylinders in dielectric, two “supermodes”are obtained, as illustrated in Fig. 2.

The propagation characteristics of a cylindrical waveguidein a dielectric are given by the following set of equations whichhave to be solved self-consistently.

γdiI1(γma)K0(γdia)

γmI1(γma)K1(γdia)= − εdi

εm(4)

γdi/m =

(k2 − εi

ω2

c2

)1/2

(5)

Fig. 1. (Left) Electric field pattern in z-direction of Ag cylinder in dielectric(εd = 2.25). (Right) Time-average power flow in z-direction. Note that the z-direction is perpendicular to the plane of the paper. The free space wavelengthis 632nm. The refractive index of Silver at this wavelength is 0.119-j3.964.The size of the single cylinder is 50nm.

Fig. 2. The two supermodes (electric field profile in z direction) of twoadjacent Ag cylinders embedded in dielectric at λ0=500nm. The diameterof the cylinders is 100nm and their center-to-center spacing is 165nm. Theeffective mode propagation indices are (2.25+i*0.089) and (2.45+i*0.088)respectively for the top and bottom supermodes.

where γdi/m denotes the evanescent field decay in the di-electric and the metal respectively, and In and Kn are thenth order modified Bessel functions of the first and secondkind. Propagation velocity and propagation length at differentdiameters and free-space wavelength obtained using COMSOLare tabulated in Table I. Our results are in good agreement withthe results provided in [12]. The attenuation of plasmons (asin Table I) is weak at long wavelengths and large diameterwires, where plasmon confinement is weak and much of theplasmon energy lies in the relatively loss free dielectric.

2) Metal-Insulator-Metal Waveguide: The electric field andthe magnetic field pattern for a 50nm × 50nm dielectricsandwiched between silver is shown in Fig. 3. The propagationmodes are given by the following characteristic equation:

tanh

(d

2

√k2 −

(ωc

)2

εd

)=

− εdεm

√k2 − (ω/c)2εmk2 − (ω/c)2εd

(6)

where d is the gap width.The power of the wave is localized near the corners of the

core, indicative of the fact that corners play a large role in theconfinement of the wave along with the metallic sidewalls.

TABLE IPROPAGATION VELOCITY OF SURFACE PLASMON MODES IN CYLINDRICAL

AG WAVEGUIDE EMBEDDED IN A DIELECTRIC. 500NM IS USED AS THEREPRESENTATIVE WAVELENGTH OF HIGHLY CONFINED MODES AND

1000NM IS USED AS THE REPRESENTATIVE WAVELENGTH OFMODERATELY CONFINED MODES. c0 IS THE VELOCITY OF LIGHT IN

VACUUM. OUR RESULTS OF PROPAGATION VELOCITY MATCH VERY WELLWITH THE RESULTS QUOTED IN [12]. HOWEVER, THE RESULTS OF

PROPAGATION LENGTH OBTAINED BY US ARE EXACTLY ONE-HALF OF THERESULTS QUOTED IN [12]. THIS COULD PERHAPS BE DUE TO DIFFERENT

DEFINITION OF THE PROPAGATION LENGTH.

Diameter (nm) Free space wavelength (nm) Velocity Lprop(µm)

10 500 0.07c0 0.04

10 1000 0.12c0 0.25

50 500 0.3c0 0.21

50 1000 0.44c0 1.66

100 500 0.4246c0 0.43

100 1000 0.55c0 4.42

Fig. 3. The left plot shows the Ez profile and the rhs plot shows the Bzprofile for an M-I-M waveguide with the width and height of the dielectricequal to 50nm each. The effective mode index is 2.54-j0.06 at 632nm. Thiscorresponds to the propagation velocity of 1.18×108m/s and a propagationlength of 0.9µm.

The propagation velocity and propagation length are tabulatedin Table II at different free space wavelengths and heightof the dielectric slab. Increasing the sandwiched dielectricwidth and/or height increases the propagation speed and thepropagation length of the fundamental propagation mode. The

TABLE IIPROPAGATION VELOCITY OF SURFACE PLASMON MODES IN M-I-M

WAVEGUIDE EMBEDDED IN A DIELECTRIC. THE METAL IS SILVER. c0 ISTHE SPEED OF LIGHT IN VACUUM.

Size(h×w) λ0 (nm) vp Lprop in µm.

50nm × 50nm 500 0.3c0 0.159

50nm × 50nm 1000 0.46c0 2.652

100nm × 50nm 500 0.36c0 0.3

100nm × 50nm 1000 0.47c0 3.32

50nm × 100nm 500 0.42c0 0.273

50nm × 100nm 1000 0.56c0 3.89

propagation length of various plasmon waveguide geometriesas a function of free space wavelength is plotted in Fig. 4.

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Fig. 4. Propagation length through various plasmonic waveguides as afunction of the free space wavelength. The propagation length is maximumat around λ0 = 1.2µm where the loss through silver is minimum. In allcases, however, the propagation length is not long enough to have long rangesurface plasmons for interconnect applications. In case of 100nm cylindricalwaveguides, the propagation length is close to 5µm which is equivalent to 14gate pitches at the 2016 technology node. Hence, these plasmonic waveguidescan be used for short local interconnect applications.

B. Comparison of plasmonic interconnects with Copper inter-connects

Having obtained the propagation characteristics of variousplasmonic waveguide structures, we are equipped to comparetheir performance, energy dissipation, and cross-talk withconventional CMOS interconnects.

1) Performance Comparison: For CMOS interconnects,only RC delay model is used since for local interconnectsinductive effects can be ignored. The CMOS interconnectdelay is given as:

tCMOS = 0.69RON (Cpar,dr + CL) + 0.69(Roncint

+ rintCfan)L+ 0.38rintcintL2 (7)

From the ITRS, at the 2020 technology node (minimumfeature size=14nm), the on-resistance RON of a minimum sizen-FET is extracted as 24 KΩ, and the parasitic capacitance ofminimum-sized driver Cpar,dr is ≈ 7.56 aF. CL is the loadcapacitance of the fan-out gate whose value is approximately15aF for minimum size inverter load. The interconnect per-unit length resistance, rint, and capacitance, cint values are2× 106Ω/cm and 1.65pF/cm, respectively [2].

The resistance at small dimensions is affected by the scatter-ing due to side-walls and line width variation. These effects areincorporated through a modified resistivity model from [13].The interconnect capacitance model including fringing effectsand coupling capacitance is taken from [14]. The RC delay ofa delay-optimized RC interconnect is given as per:

td,RC = 2.5√R0C0rintcintL2 (8)

where R0 is the output resistance of minimum size driver, C0

is the input capacitance of the minimum size receiver. Theoptimum number of repeaters and their optimum size is thesame as given in [15].

The plasmonic interconnect delay is given as:

tplasmon = tsw +L

vp(9)

where tsw is the plasmonic switch delay.Plotted in Fig. 5 is the CMOS interconnect delay and the

delay of cylindrical plasmonic interconnects for different di-ameters and different free-space wavelengths. Ideal plasmonicswitches are assumed. Plasmonic interconnects can be ordersof magnitude faster than CMOS interconnects in most cases.

100 101 10210 3

10 2

10 1

100

101

102

103

Interconnect length (in units of gate pitch)

Dela

y (p

s)

0.36 µm 3.6 µm 36 µm

Light Line

dia=50nm(@1000nm)

CMOS (not optimized)dia=10nm(@1000nm)

dia=50nm(@500nm)

dia=10nm(@500nm)

CMOS (delay optimized)

Fig. 5. Delay versus length of CMOS interconnect and plasmon interconnect.As the speed of plasmonic interconnects is comparable to the speed of light,they can be orders of magnitude faster than CMOS interconnects.

Although the plasmonic interconnects are much faster com-pared to CMOS interconnects, they are limited to be used onlyat the local interconnect level because their propagation lengthis only a few microns.

2) Energy Comparison: The energy of CMOS intercon-nects is given as per:

ECMOS = 1/2CV 2 (10)

where C is the sum of the total interconnect capacitanceand the load capacitance and V is the supply voltage. Theinterconnect capacitance increases linearly with interconnectlength.

For plasmon interconnects, shot noise limited transmissionis considered. The bit error rate (BER) for information trans-mission on an integrated circuit is roughly estimated to be10−30 based on transistor performance estimates of 1000 faultsin 109 hours on a chip with 109 components operating at aclock frequency of several GHz. Shot noise limited detectionof an ideal coherent noise source with a mean number of< m > plasmons for state “1” and “0” results in a bit errorrate of 1/2exp(− < m >). If the bit error rate is equal to10−30, then mean number of plasmons < m > is equal to 68.However due to loss on the plasmonic interconnect, minimumenergy transmitted per bit (assuming unity quantum efficiency)is given as [12]:

Esp =1

2hω < m > exp(αL) (11)

where α = 1/Lprop. The shot noise limited energy dissipationof plasmonic interconnects increases exponentially with theratio of interconnect length and the plasmon propagationlength. Hence, for interconnects longer than the propagationlength, energy dissipation of plasmonic interconnects increasesquite drastically. The cross-over length at which the energy

dissipation of plasmon interconnects exceeds the energy dissi-pation of CMOS interconnects can be obtained by equating(10) and (11). Plotted in Fig. 6 is the cross-over lengthfor different sizes of cylindrical Ag waveguides and M-I-Mwaveguides as a function of the free space wavelength.

0.5 1 1.5x 10 4

100

101

102

Free Space Wavelength (µm)

Cro

ssov

er L

engt

h (µ

m)

cylinder (dia=100nm)M I M (50nm × 50nm)cylinder (dia=50nm)

Fig. 6. Cross over length beyond which it is more energy efficient tocommunicate via conventional electrical interconnects rather than via SPinterconnects due to attenuation os SPs.

3) Crosstalk assessment: Cross talk refers to the signalenergy leakage from one interconnect to its neighbor. Cross-talk is typically characterized by a coupling length of thevictim wire such that an aggressor will locally induce a signalchange equal to 25% of that required for a complete inversionof the logical value. Surface plasmons suffer from evanescentfield coupling between neighboring wires wherein energy islost from one signal wire carrying energy to another notcarrying any energy initially. In order to quantify the cross talkcoupling length of two neighboring SP waveguides, COMSOLis used to find the supermodes of the two wire system. Thenthe crosstalk coupling length definition as in (3) is used toobtain the 25% coupling length. The coupling length is plottedin Fig. 7 for cylindrical Ag waveguides.

0 50 100 150 200 250 300 350 40010 2

10 1

100

101

102

103

104

Pitch (nm)

Cro

ssta

lk le

ngth

(µm

) 10nm(@500nm)

10nm(@1000nm)

100nm(@1000nm)

50nm(@500nm)

100nm(@500nm)

50nm(@1000nm)

Fig. 7. The coupling length for SPs (10nm, 50nm, 100nm) diameters at twooperating frequencies of 300THz and 600THz.

Crosstalk coupling length in SPs degrades at lower oper-ating frequencies and/or larger diameter of the waveguides.Although an assessment of the coupling length for electricalinterconnects was not performed by the authors, the results

from literature [12] are indicative of the fact that SPs sufferfrom at least as much cross talk as electrical interconnectsexcept at small size and higher frequencies.

III. OPTICAL INTERCONNECTS

Due to the limitation on propagation length, plasmonicinterconnects can be used only as short local interconnects.To address the interconnect problem at the global interconnectlevel, optics emerges as a promising technology [16],[17].Since the latency of an optical signal is given by the speed oflight in the medium,variations in transmission delay are verylow, so the timing of these optical signals can be modeledand predicted accurately. This is very advantageous in theuse of optical interconnects in clock distribution network.Optical interconnects offer higher bandwidth compared toelectrical interconnects–their bandwidth being limited only bythe optical modulators and receivers. Optical interconnectshave very low attenuation and hence no repeaters are required.

A. Components of On-chip Interconnect system

An on-chip optical link as in Fig. 8 consists of the followingcomponents: a) A Laser source that is generally assembled offchip and is coupled to the modulators; b) Optical modulatorthat is used to manipulate a property of light often of anoptical beam such as a laser beam. Silicon optical modulatorsare one of the key building blocks which have been extensivelystudied; (c) an optical waveguide which can be implementedas a silicon strip waveguide or a rib waveguide for a 2-Dconfinement, (d) photo-detector that generates current propor-tional to the incoming light intensity and (e) a transimpedanceamplifier followed by gain stages.

Fig. 8. Block diagram of optical link. The optical link consists of a modulatordriven by a tapered chain of electrical drivers, the optical waveguide and aphoto-detector followed by a trans impedance amplifier.

In order to compare the optical interconnect, followingmetrics related to the performance and energy dissipation areconsidered.

1) Delay: This metric is more relevant for clock distributionand control signal transfer.

2) Bandwidth Density: This metric is relevant for heavydata transfer applications

3) Bandwidth Density/Delay: This metric is relevant inthose applications that are sensitive to both delay andbandwidth.

4) Energy Dissipation: This metric is generally importantfor all applications.

B. Modeling the delay of optical interconnects

The delay of an optical link topt is given as in (12)

topt = ttx + twg + trx (12)

where ttx is the delay of the transmitter, twg is the delay ofthe waveguide and trx is the receiver delay.

A transmitter is composed of an electro-optical modulatorand a driver circuit in order to drive the huge capacitanceof the modulator. The design of a fast and cost efficientCMOS compatible electro-optical modulator is one of the mostchallenging tasks on the path towards realizing on-chip opticalinterconnects. Unlike todays commercially available opticalmodulators which use III-V semiconductors, [18] or LiNbO3[19], achieving modulation in crystalline silicon is challengingdue to the fact that it exhibits no linear electro-optic (Pockels)coefficient and has a very weak Franz-Keldysh effect [20]. Oneof the few suitable mechanisms for varying the refractive indexin pure silicon is the free carrier plasma dispersion effect [20].The two electrical structures that achieve free carrier plasmadispersion effect are the (i) MOS capacitor based modulatorand (ii) PN diode silicon modulator. However, the capacitanceassociated with current silicon modulators is tens of pico-farads. Hence, tapered electrical driver chain is needed to drivethe huge capacitive load at the modulator. Thus, the delay ofthe transmitter can be expressed as:

ttx = Noptuoptτr (13)

where Nopt is the optimum number of stages in the driverchain and is equal to Nopt = ln (Cmod/C0) /ln(3.6) whereCmod is the modulator capacitance and C0 is the inputcapacitance of a minimum size driver. uopt is the optimumsize which is assumed to be 3.6 and τr is the delay of theminimum size driver.

The performance of optical waveguides is primarily limitedby the wavelength of the utilized light and the choice ofoptical material. Although novel waveguide platforms, suchas photonic crystal waveguides, can potentially reduce thewaveguide pitch, optical losses in such structure will likelydiminish this advantage. For applications requiring dense andshort waveguide arrays, a silicon-on-insulator (SOI) structureis more beneficial due to the smaller waveguide pitch. In thispaper we consider a waveguide comprising of a silicon core(refractive index of 3.5), a SiO2 cladding as the transmissionmedium. The delay through the optical waveguide is expressedas:

twg = neffL

c(14)

where neff is the effective refractive index of the mode in thewaveguide medium, c is the speed of light in vacuum and Lis the waveguide length.

The receiver has two components: a photo-detector thatconverts light into electricity followed by receiver circuitsthat amplify the analog electrical signal to a digital voltagelevel. There are many different kinds of photodetectors suchas the photodiodes with a p-n or a p-i-n structure, M-S-Mphotodetectors, avalanche photodetectors and photomultipliers[21]. The M-S-M photodetector has the fastest response with

a good quantum efficiency. The response time of the M-S-Mphotodetector depends on the carrier transit time and the RCcharging time of the detector capacitance. Thus the responsetime is given as [22]:

Tr = (τ2tr + τ2RC)1/2 (15)

τtr =X

v(16)

τRC = 2.2RC (17)

where v is the carrier drift velocity and X is the driftdistance travelled by the carriers. The delay of the M-S-Mphotodetector is expressed as [22]:

TD = 0.315Tr (18)

The limiting factor in the delay of photodetectors is in carriertransit time [22]. The response time of the photodetectorreduces as the electrode is made smaller in area. However,there exists an optimum area at which the response time ofthe detector is minimum [22]. The reason for this is that whenthe electrode is too narrow then the response time is dominatedby RC and when it is too wide the response time is dominatedby the transit time.

The transimpedance amplifier (TIA) is needed in order toamplify the photo current signal generated by the photode-tector before the signal is fed into the digital gates. Thus theoptical link delay must incorporate the delay of the TIA. Thedelay of the TIA is calculated by assuming that the system isa one-pole system and hence the delay is approximated as per[23]:

TD =0.693

2π∆f(19)

where ∆f is the bandwidth requirement. Thus the net delayassociated with the optical receiver using (18) and (19) is:

trx = 0.315√

(2.2RC)2 + (X/v)2 +0.693

2π∆f(20)

In order to compare the performance of optical interconnectsand electrical interconnects at the technology node of 2016,delay of optical modulator and photodetector based on apredictive model in [22] is used. The data is reproduced herein Table III.

TABLE IIIDELAY (PS) OF AN OPTICAL TRANSMITTER AND RECEIVER BASED ON

PREDICTIVE MODELS IN [22].

Component 2010 2013 2016

Mod. Driver 25.8 16.3 9.5

Modulator 30.4 20.0 14.3

Photo-detector 0.3 0.3 0.2

Receiver Amplifier 10.4 6.9 4.0

C. Modeling the bandwidth density of optical interconnects

Bandwidth density (or data flux density) is defined asthe product of the bandwidth and reciprocal pitch of aninterconnect, and represents the number of bits per second

that can be transferred across a unit length bisectional line.The bandwidth density is given as:

φD =BW

P=

1/τ

2W(21)

where BW is the bandwidth of an interconnect and P isthe wiring pitch. It has been assumed that the bandwidth isdetermined by the reciprocal latency and the spacing betweenthe wires is equal to the wire width. It has been shownearlier in [24] that maximizing φD maximizes the bisectionalbandwidth of the chip. Thus the definition of bandwidthdensity as in (21) will be used as a figure of merit to comparethe electrical and the optical interconnects.

The wiring pitch or the density of wiring in optical intercon-nects depends very strongly on the waveguide structure andthe wavelength of light. As per the diffraction limit, the sizeof optical interconnects cannot be reduced below λ/2 where λis the wavelength of light. If the wavelength used is 1000nm,then the minimum size of the optical interconnect is limitedto be 500nm. The exact relationship between the waveguideheight, width and pitch is complex. In this analysis, we usethe data in [25] for the pitch of the SOI waveguide in Siliconwith a top SiO2 cladding.

Due to the fundamental limitations on the wiring pitch inoptical interconnects, the data flux density as in (21) tendsto be the critical figure of merit deciding the performance ofoptical interconnects relative to the electrical interconnects.In order to address the issue of pitch, wavelength divisionmultiplexing (WDM) has been considered for optical intercon-nects. WDM refers to a technology which multiplexes multipleoptical carrier signals on a single optical interconnect by usingdifferent wavelengths of laser light to carry different signals.This allows for multiplication in capacity. A WDM uses amultiplexer at the transmitter to join signals together and ademultiplexer to split them apart at the receiver. However,the overhead in latency associated with multiplexing and de-multiplexing signals has to be considered appropriately in theperformance model of a WDM optical interconnect. The modelof delay in optical interconnects that incorporates the overheadin WDM is given as:

tWDM = (ttx + trx)(1 + θlog2N) +neffL

c(22)

where θ is the overhead fraction and N is the number ofwavelengths multiplexed. In simulations, θ is assumed to be10%.

D. Modeling the energy dissipation of optical interconnects

The energy dissipation of CMOS interconnects is due tothe charging and discharging of load capacitance and theinterconnect capacitance through the supply voltage. Thisenergy dissipation is mathematically given as:

ECMOS = 1/2CV 2DD = 1/2(cwL+ C0kopthopt)V

2DD (23)

where cw is the per unit length capacitance of the interconnectof length L, C0 is the input capacitance of the minimumsize driver, kopt is the optimum number of repeaters in theinterconnect and hopt is the optimum size of the repeaters for

an interconnect that is delay-optimized. Reference [15] is usedfor closed form expressions of hopt and kopt.

The energy dissipation in optical interconnects consists ofthree components- energy dissipated to charge the modulatorcapacitance, the energy needed at the photo-detector to gen-erate the photocurrent proportional to the incoming light andthe static power dissipation in the transimpedance amplifier.The three components are given as:

Emod = 0.7CmodV2DD (24)

Epd = 1/2CdetVDDEph

η(25)

Estatic = PstatTr (26)

where Cdet is the detector capacitance and is approximatelyequal to 350fF at the 2016 technology node, Eph correspondsto the photon energy of the incoming light and η is thequantum efficiency (= number of electron hole pairs generatedper incoming photon.) and Tr is the response time of thereceiver as expressed in (17). The data for static powerdissipation has been provided in [22] based on predictivemodels. For the capacitance values in [22] almost 70% energyis dissipated in the modulator followed by energy dissipationin the photodetector. In the present work we have ignored thelaser power since laser is generally off the chip.

E. Comparison of Electrical and Optical Interconnects

In order to address the interconnect problems, it is importantto compare the performance of alternative technologies againstelectrical interconnects. In this respect, the metrics of delay,bandwidth-density, bandwidth-density/delay and energy per bitare compared for electrical and optical interconnects. Onlylong global interconnects that have been optimized by repeaterinsertion are considered. A unified RLC model is used for thedelay of electrical interconnects [15].

The critical interconnect length as a function of the width ofthe interconnect is plotted in Fig. 9 for different metrics relatedto performance. Critical length in this context is defined as thelength beyond which optical interconnects offer superior per-formance compared to their electrical counterparts. The criticalinterconnect length is decided by one of the metrics-bandwidthdensity, delay, energy or “bandwidth density/delay”. The crit-ical length with respect to energy dissipation is less than0.2cm for the typical values of parameters selected fromliterature. Hence, for a single channel optical interconnectenergy dissipation is not the limiting factor to determine therelative merits of the two interconnect technology options.

It can be seen in Fig. 9 that if WDM is not employed thenthe critical interconnect length for pitch of 1µm is greaterthan the chip edge. Depending on how many wavelengthsare multiplexed, the performance advantage of WDM opti-cal interconnects will progressively increase, as is shown insimulation results in Fig. 10. However, the circuit, area andenergy overhead in WDM must be accounted for in order toassess the feasibility of WDM on chip. Currently there aremultiple challenges with WDM on chip such as integration,manufacturability, size, weight and cost. It is shown in [26]that the number of WDM channels needed in a polymer

0 2 4 6 8 1010 2

10 1

100

101

W/Wmin

Critic

al L

engt

h (c

m) Optical

interconnectpitch = 1µm

D/D

Fig. 9. Critical length of optical interconnects as a function of the width ofelectrical interconnects at the 2016 technology node.

waveguide are around 8 at the 2016 technology node inorder to be superior to electrical interconnects. For a siliconwaveguide the number of WDM channels is around 4 at the2016 technology node. The reason for this is primarily dueto the fact that a polymer waveguide cannot be scaled indimension as much as a silicon waveguide [25]. Silicon-on-insulator waveguides offer the best pitch at the cost of delay.

0 2 4 6 8 100

0.2

0.4

0.6

0.8

1

1.2

1.4

W/Wmin

Crit

ical

leng

th(in

cm

)

Critical Length Based on D(WDM)

N=2N=4N=8N=16N=32

Fig. 10. Critical interconnect length with wavelength division multiplexingas a function of the width of the electrical interconnect. With a 10% overheadassociated with multiplexing signals, the critical length for optical intercon-nects is small enough for N=4 to be used as global on-chip interconnects.

A summary of critical length of optical interconnects usingthe metrics discussed above has been provided in a conciseform in Table IV. The results highlight that (a) optical inter-connects as on chip interconnects have superior performancethan electrical interconnects only at the global level, (b)Bandwidth density is the limiting metric, and (c) wavelengthdivision multiplexing helps to alleviate the problem of opticalinterconnects associated with higher pitch.

IV. CONCLUSIONS

Due to the increasing problems of energy dissipation andlatency of copper interconnects in modern and future highperformance microprocessors, faster and energy efficient in-terconnect options are being investigated. In this paper we

TABLE IVCRITICAL LENGTH OF OPTICAL INTERCONNECTS AT THE 2016

TECHNOLOGY NODE BASED ON COMPARING THE SPECIFIC METRIC WITHTHE ELECTRICAL INTERCONNECT. THE METRIC “BANDWIDTH DENSITY”

YIELDS THE LARGEST CRITICAL LENGTH.

Metric Critical Length (cm)(2016 Tech Node)

Delay 0.7Bandwidth-Density 3.2

Bandwidth-Density/Delay 0.74Energy dissipation 0.15

WDM (Bandwidth-Density) with N=4 and 0.310% overhead of MUX and De-MUX

have discussed two possible alternative technologies that canaim to augment the current Cu-low κ technology: plasmonicinterconnects and optical interconnects.

It is shown that due to their high speeds of propagation,plasmons are orders of magnitude faster compared to CMOSinterconnects. The cross-over length beyond which plasmonwaveguides become less energy efficient than CMOS intercon-nects increases with the free space wavelength and becomesmaximum around 1200nm. The cross over length ranges fromfew microns (at smaller diameter and lower wavelength) totens of microns (at higher wavelength and larger diameters).Finally, an assessment of the coupling length of plasmonwaveguides based on crosstalk among adjacent waveguides isdone. The results show that crosstalk length of the victim wireat which 25% of signal energy of the aggressor is transmittedonto the victim wire is as low as 0.1µm at 30nm pitch for10nm diameter Ag cylinder at 6THz operating frequency. Thecross-talk length increases to 1000 µm for 100nm pitch forthe same waveguide. However, cross-talk length worsens asoperating frequency is reduced.

Analysis of optical interconnects highlights the limitationsthat the transmitter and receiver circuitry can impose on theoverall performance of the interconnect. In addition, due tothe fundamental limitation in scaling the pitch below 1µm inmost cases, the bandwidth density of optical interconnects isgenerally inferior than the on-chip global electrical intercon-nects. Wavelength division multiplexing can be beneficial inorder to improve the “effective pitch” of optical interconnects.However as many as 4 signals need to be multiplexed in orderto gain substantial benefit for global optical interconnects.Energy dissipation analysis of optical interconnects showsthat due to the huge modulator capacitance, most of theenergy is consumed in the electrical driver chain. However,energy dissipation of optical interconnects is lower than thatof electrical interconnects for interconnects longer than 0.2cm.

The paper attempts to highlight critical length scales atwhich plasmonic and optical interconnect technologies maytake over electrical interconnect technology. Plasmonic issuitable at short local interconnect level while optical intercon-nects are viable at the global interconnect level. However, thereare multiple challenges associated with these technologies ifthey must augment the CMOS technology. Issues related tointegration, cost and reliability need to be addressed.

ACKNOWLEDGEMENT

The authors are grateful to Prof. Jeffrey A. Davis and Prof.Azad J. Naeemi for all their support, feedback and insightfuldiscussions.

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