Simulation, Design and Analysis of a Low Power MIMO-OFDM System and its Implementation on

FPGA Subhankar Bhattacharjee#, Sanjib Sil#, Sayan Dey#, Amlan Chakrabarti*,

#ECE Department, Techno India College of Technology, NewTown, Rajarhat, Kolkata-700156. 1subhankarb42002@yahoo.co.in.

2sanjib_sil@hotmail.com. 3sayandey34@yahoo.in.

*A.K.Chowdhury School of Information Technology, University of Calcutta, Kolkata, India.

4acakcs@caluniv.ac.in.

Abstract— In the world of modern communication systems, several newer techniques have come around to replace the conventional techniques of high speed data communication. As wireless communication protocols developed and user pressure started to increase, it became an absolute necessity to develop multi-user supporting techniques like Orthogonal Frequency Division Multiplexing (OFDM), Multi Carrier Code Division Multiple Access (MC-CDMA) for data security and reliability of data transmission. In this work, an effort has been made to simulate and design a low power consuming custom hardware for MIMO-OFDM system based on Field Programmable Gate Array (FPGA). Both the transmitters and the receivers were designed in the simulation environment targeting Xilinx Spartan 3E and Spartan 3A FPGA devices. The design was also implemented on the mentioned FPGA hardware and real experiments were carried out for the verification of the design. Our design proves that a very low power system can be designed using an FPGA device which can provide much higher data rate and very less power as compared to the conventional systems and it can also be reconfigured according to the requirement. Keywords— MIMO, OFDM, FPGA, System on Chip, Low Power Design

I. INTRODUCTION Multiple Input Multiple Output (MIMO) systems are one of

the latest developments in the field of communication engineering and is a significant departure in the architecture and technology from the existing Single Input Single Output (SISO) communication system[1,2,3]. In radio, multiple-input and multiple-output, or MIMO is the use of multiple antennas at both the transmitter and receiver to improve communication performance.[4] It is one of several forms of smart antenna technology which is poised to make a significant impact in the overall performance of wireless communication system.

MIMO technology draws an attention in wireless communications due to significant increase in data throughput and link range without additional bandwidth or transmitted power. It achieves this by higher spectral efficiency (more bits per second per hertz of bandwidth) and link reliability or

diversity (reduced fading). Because of these properties, MIMO is a current theme of international wireless research [5,6]. Thus, it has become an absolute necessity to develop MIMO systems for effective wired and wireless communication and replace the conventional Single Input Single Output (SISO) systems. The SISO systems offered very less data rate and reliability as compared to the MIMO systems [1,4]. Thus, the present study aims at developing a MIMO transreceiver system based on FPGA based target hardware which offers very high data rate, high noise immunity, reliability and very low bit error rate. The choice of FPGA based design over the traditional VLSI design is also a challenge in this work to achieve an appreciable performance in much less design cost and design time.

A. Modulation techniques The traditional conventional techniques of modulation and data transmission are not sufficient to meet the increasing demands of the global communication customers. The effective usage of bandwidth is an important need in terms of modern communication where channel and bandwidth sharing is required at every point of time. Thus, newer technique Orthogonal frequency-division multiplexing (OFDM), essentially identical to coded OFDM (COFDM) and discrete multi-tone is a frequency division multiplexing (FDM) scheme used as a digital multi-carrier modulation method. In this scheme a large number of closely spaced orthogonal sub-carriers are used to carry data. The data is divided into several parallel data streams or channels, one for each sub-carrier. Each sub-carrier is modulated with a conventional modulation scheme (such as quadrature amplitude modulation or phase-shift keying) at a low symbol rate, maintaining total data rate similar to conventional single-carrier modulation schemes in the same bandwidth.[10,11] It is achieved through Gram Schmidt Orthogonalization[1,2,4] process and carrier multiplexing in orthogonal planes[4] where each hyper plane is orthogonal to all other planes. Hence, the carrier interference or rather signal interference is avoided. Thus, the whole

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bandwidth is effectively shared using the Orthogonal Frequency Division Multiplexing technique. Carriers are divided into their respective sine and cosine parts in each plane. Thus the two components are orthogonal to each other in that plane and are also orthogonal to all the other carrier components that are present in the other orthogonal planes. Thus, bandwidth sharing and carrier multiplexing can be achieved successfully. In this work, such an OFDM transmitter is designed using 64 QAM such that the bandwidth can be effectively shared and the data rate is increased to a considerable extent.

B. Hardware design After the communication part is designed according to the needs, it is now important to implement the whole design in hardware in the System on Chip (SoC) form. The most important constraint of the VLSI design is the effective power consumption and all VLSI designers aim at reducing the power consumption of the chip [12,13]. Nowadays, FPGA is a much-favoured platform for digital VLSI design due to the high flexibility, reusability, low power, moderate costs, easy upgrading (due to usage of hardware description languages (HDLs)) and feature extension (as long as FPGA is not exhausted) facilities available in the FPGAs. This design is implemented on a FPGA Spartan 3 series kit and the real output is compared with the simulated result from the computer using the Cathode Ray Oscilloscope. Several attempts were made to design and implement MIMO systems with special attention to the receiver [19] . FPGA based System on Chip designing is another criterion which is a topic of discussion for many researchers in the field of SOC and ASIC designing. Several implementation works have been performed based on FPGA [16,17,18] but no significant work has been focused on the VLSI design issues like reduction of effective power consumption, reduction of junction temperature etc. Several algorithms for decoding the MIMO signals using the concepts of state-space analysis have also been developed in the form of sphere decoders [19], channel estimation method [13] have been developed which effectively decodes the MIMO signals successfully during a real time operation. In all these algorithm implementations, nothing has been discussed about the time, space and computational complexities of the design. The simulation of MIMO-OFDM systems have also been performed in the past [16,17] but more focus is put on the antenna parameters of the design rather than its hardware implementation and circuit level analysis. Also, no significant efforts have been made in providing the design with channel flexibility, which provides different channel transfer function that brings the simulation close to real time operation or communication of data.

II. PROPOSED METHODOLOGY

A. The Simulation of the design model Our work deals with the design, simulation analysis and implementation of different order MIMO-OFDM systems. The design is first simulated in MATLAB using the Simulink

library and then it is implemented on the Spartan 3A FPGA using the Xilinx System Generator. The design of the whole communication system can be broadly divided into three parts, which are as follows:

• Transmitter • Channel • Receiver

Transmitter The design of the 4th order system is considered here but higher ordered as well as lower ordered systems are also designed in this project. The transmitter consists of several parts, which are individually explained below. The whole module is responsible for the Orthogonal Frequency Division Multiplexing of the baseband signal and transmission by the use of multiple antennas.

Fig. 1 OFDM Modulator design

In the transmitter part, raw data was fed to the transmitter from a particular data source (Bernoulli Binary Generator in this case). Two types of design were made: one feeding the same data to four different transmitters of the MIMO system [Fig.2] and the other feeding different parts of the same frame to the different transmitters and the frame is equally divided among the modulator systems. The modulator [Fig.1] is based on Orthogonal Frequency Division Multiplexing technique as described in section (I-A). The modulator uses the Quadrature Amplitude Modulation technique (64 QAM) and then this signal is Orthogonally Frequency Division Multiplexed to form the required signal.

Fig. 2 A 2X2 OFDM-MIMO Modulator System

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Channel After the signal is being modulated in our design, it has to be transmitted successfully through different types of noisy channel [Fig.3]. In practical cases, to modulate and transmit a message signal over the free spaces, the signal has to pass through the various types of noisy channel. It depends upon the climate and weather condition of that particular channel. These channels have different transfer functions, which may vary according to time and weather change. Due to this reason different types of fading effects are involved in the channel.

Fig. 3 Design of Different channel transfer functions

In this design, after OFDM modulation, we pass the

modulated signal through various type of noisy channel. Such as AWGN channel, Rician fading channel, Rayleigh fading channel etc. These are generally fading channels, which are of great importance in the modern wireless communication. Different transfer functions were designed using a combination of different types of channels. Series and parallel combination of these channels define newer transfer functions, which can be used to represent the actual channel (the environment in case of wireless communication channel). The motivation here is to design the transmitter and receiver according to the channel transfer function because the communication engineers can successfully design the transmitter and the receiver under their scope of design but the channel is completely unpredictable in the worst-case scenario. In this work we have tried to simulate the communication systems close to the actual and analyse our design based on experimental results. Receiver The last part of the system is the receiving [Fig.4] part. After being transmitted through the various types of noisy channel, the modulated signal needs to be demodulated to retrieve the original data. In our design we have used an algorithm called Least Mean Square LMS algorithm for adaptive equalization of the received signal.

Fig. 4 OFDM Demodulator

The second important part of the receiving system is Signal recovery system where LMS technique is actually implemented. LMS algorithms are a class of adaptive filter used to mimic a desired filter by finding the filter coefficients that relate to produce the least mean squares of the error signal (difference between the desired and the actual signal). It is a stochastic gradient descent method in which the filter is only adapted based on the error at the current time. The receiver module is designed to demodulate the faded and distorted signal received from the channel.

Fig. 5 Design of correlation filter

In our design we have implemented the LMS equalizer and have also designed correlation algorithm [Fig.5] to recover the distorted MIMO-OFDM signal. The complexity of the system is analysed and was compared with the standard systems in existence [13] and was found to give a successful and better result in terms of the Bit Error Rate,[Table-I,II] data rate [Fig.8] and efficiency of demodulation and prediction of the received signal.

B. Analysis of the framewise design The framewise design was designed and simulated using the MATLAB Simulink blockset library. Five different systems were designed as shown in the Table-I below and the effective Bit Error Rates were recorded. The first system is the conventional SISO system, which has a comparatively high bit error rate as shown in Table-I. As for the MIMO systems, four different types of MIMO systems were designed being respectively 2nd, 4th, 8th and 12th order systems. These are the multiple antenna systems transmitting the same signal in this design. From Table-I it can be observed that the MIMO systems have much less bit errors and the errors decrease as the order of the system increases.

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TABLE I BER COMPARISON (FRAMEWISE DESIGN)

C. Analysis of Bitwise design In this type of design, the bit error rate is comparatively

lower as compared to the framewise transmission and the data rate is also higher. The detailed results are shown below in the following Table-II.

TABLE II

BER COMPARISON (BITWISE DESIGN)

D. Graphical comparison of BER of Bitwise and Framewise design

The Fig.6 and Fig.7 below shows the graphical representation of the experimental results stated in Table-I and Table-II of the two designs. It is clear from the two tables that

the bitwise design offers more accuracy as compared to the framewise designs in terms of data transmission. Hence, the bitwise design is best fit for practical implementation in real time operations in the field of modern wireless communication where accuracy is the main need eg. Defence, Aviation etc.

Fig. 6 BER Comparison for framewise design

Fig. 7 BER Comparison for Bitwise design

III. FPGA DESIGN ISSUES

A. Power Estimation on FPGA The hardware implementation of the design brings out a few important FPGA design issues like power consumption, operating temperature, operating frequency, time delay that are very important parameters while designing a chip. The following Table-III shows the design parameter readings were taken with the help of Xilinx System Generator for Spartan 3A FPGA kit.

SNR (dB) SISO MIMO 2 MIMO 4 MIMO 8 MIMO 12

10 0.7439 0.335963 0.007466 0.002039 0.000832

20 0.7535 0.190037 0.005718 0.001214 0.000471

30 0.6823 0.024268 0.003601 0.000444 0.000244

40 0.6023 0.036887 0.001851 0.000151 0.000091

50 0.5564 0.018425 0.000565 0.000124 0.000045

60 0.4881 0.015598 0.000217 0.000081 0.000038

70 0.4324 0.007788 0.000128 0.000024 0.0000019

80 0.3816 0.000925 0.000021 0.000007 0.0000006

SNR (dB) SISO MIMO 2 MIMO 4 MIMO 8 MIMO 12

10 0.7439 0.1359631 0.004466 0.00103988 0.0005327

20 0.7535 0.090037 0.00271848 0.000214627 0.0000971

30 0.6823 0.0242682 0.00086016 0.000144488 0.0000744

40 0.6023 0.0086887 0.00035112 5.10536E-05 0.0000314

50 0.5564 0.0038425 6.5255E-05 6.89072E-06 0.0000035

60 0.4881 0.0015983 7.8183E-06 0.0000021 0.0000001

70 0.4324 0.0007882 4.2548E-06 0.00000007 0.00000001

80 0.3816 0.0001255 0.0000001 5.24E-08 0.000000006

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TABLE III FPGA BASED DESIGN RESULTS

Design Issue

SISO MIMO 2

MIMO 4

MIMO 8

MIMO 12

Total Dynamic Power (in

Watt)

0.0107 0.0216 0.03211 0.0858 0.1285

Total Quiescent Power (in

Watt)

0.03585 0.0718 0.10754 0.2868 0.4305

Total Power (in Watt)

0.04655 0.0932 0.13965 0.3724 0.5586

Junction temperature

(in ○C)

27.85 27.9 28.1 28.17 28.2

Maximum Frequency (in MHz)

216.612 192.12 186.463 178.62 172.145

Maximum Period (in

ns)

1.788 3.575 5.363 14.304 21.456

No. of IOB used

114 228 456 912 1368

No. of 4 Input LUTs

used

39 78 156 312 468

No. of Slice Flip flops

used

64 128 256 512 768

No. of Slices used

60 120 240 480 720

B. Data rate Analysis The data rates for the different MIMO systems of different order are also analysed. It is observed that as the order of the system increases, the data rate also increases. After we reach the 12th order system, the data rate ceases to increase in a significant amount. Moreover, as the number of antennas increase, the hardware cost also increases. Thus, it is best to use an optimum system to get the best results. As seen in the graph (Fig.8) below, the data rate reaches above 1 Gbps (precisely 1.025 Gbps) in case of 12th order system that is one of the aims of the experiment and study.

Fig. 8 Data rate Comparison

C. Time complexity analysis The time complexity is another important issue in designing real time communication systems. It mainly depends on the adaptive equalizing algorithms used for decoding of the received signal. In this design, the signed LMS and Correlation Algorithms are used. The performance of this new algorithm in terms of time complexity was analysed. In 1 second, 3126 frames are successfully transmitted for the 4th order system. The number of frames increases as the order of the system increases. Thus, time complexity of the 4th order system comes out to be (1/3126) frames = 0.032 msec. A detailed Table-IV is provided below showing the time complexity of the different order systems.

TABLE IV TIME COMPLEXITY OF DIFFERENT MIMO SYSTEM

IV. CONCLUSIONS From the above study, it can be inferred that a low power

low cost FPGA based reconfigurable architecture can be designed which offers effective communication. As it uses the Orthogonal Frequency Division Multiplexing, it offers faster data transmission and huge amount of data transmission without significant interference. It is observed that the data rate increases considerably as the order of the system increases. Thus, this design is a very simplified yet low power consuming and promises to be an effective communication chip, which can be used for application development in the growing field of communication.

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