The design and realization of data asynchronous exchange protocol based on USB and FPGA

Guoyong Zhen, Yanhu Shan* National Key Laboratory for Electronic Measurement Technology, Key Laboratory of

Instrumentation Science & Dynamic Measurement, Ministry of Education, North University of China Taiyuan, Shanxi, China shanyanhu@126.com

Abstract—A data exchange protocol between test system and PC computer is designed based on USB2.0 controller chip CY7C68013 and FPGA. The system transmission adopts mainly GPIF mode, has achieved high-speed transmission of a variety of data between the test system and the PC host, and has met new demands of generalization of the missile telemetry automatic test system for interface technology between the test system and the PC. The paper gives the physical layer hardware circuit design of system interface, and describes how to make full use of internal resources of CY7C68013 and FPGA to achieve the transfer protocol. At present the transport protocol has been successfully used in a missile telemetry universal test instrument project.

Keywords- telemetry system; GPIF; Asynchronous mode

I. INTRODUCTION At present, the Universal Serial Bus USB interface, with

its advantages of high transfer rate, plug-and-play, flexibility of connectivity, and easy installation has gradually become the data transfer mainstream between the host PC and test system [1]. The automatic test of missile telemetry system has the upgrade requirements of generalization and modularization. With the increasing of function module in the test system, how to achieve high-speed, reliable and seamless transmission of data sources with different transmission rate presents the new challenges to USB interface technology. The main approach of dealing with multiple data sources is to mix data for many times, which will increase the difficulty of development. For the design of a general-purpose telemetry test equipment, the data asynchronous exchange protocol based on USB and FPGA is designed, which adopts asynchronous driving mode and makes full use of CY7C68013’s internal resources in order to make the transmission of data sources with different transmission rates handled more simply and reliably, and the transmission speed between the PC host and test system improved effectively.

II. THE DESIGN OF PROTOCOL HARDWARE CIRCUIT According to design requirements of a missile telemetry

universal test system, as shown in Figure 1, the hardware of this protocol consists of USB module which uses the chip CY7C68013 of CPRESS Corporation, logic control FPGA module, external FIFO cache module, and LVDS interface

module. Host PC downloads commands and data through the USB bus to the master control module of the test system. After receiving PC data, the USB module retransmits them to FPGA, and then downloads to other functional modules through the LVDS module and backboard bus. Due to different transmission speed and quantity of uploading, all of uploading data will be cached in the external FIFO through LVDS module, and then FPGA completes communication through controlling USB transmission module. In the process, host PC sends out reset command to external FIFO before sending the command of uploading data, so the data cached in FIFO are those which will be uploaded, therefore, this will reduce the complexity of PC data analysis to a great extent.

The connection between the USB module and FPGA is achieved through GPIF and FIFO from the point of view of timeliness of data transmission[2]. The CY7C68013 is a high-speed USB2.0 transmission control chip, with advantages of high-speed instructions, on-line "soft configuration" and providing a general programmable interface (GPIF), etc. GPIF is a user-programming interface, with fast, flexible features, etc. a variety of agreements can be used to complete the seamless connection of external devices. It can generate six control signals CTL [5:0], 9-bit address output GPIFADR [8:0], and receive six signals of external instrumentation and two internal signals of READY state. The user can control state machine through the compilation profile descriptor. CY7C68013 almost allows producing four waveform descriptor, that is, FIFO read, FIFO write and single-byte read and single-byte write[2]. Rich resources of CY7C68013 single-chip contribute to the realization of the protocol. In this paper, two waveform descriptors are mainly compiled, that is, FIFO read, FIFO write.

LVDS interface

Logic control FPGA

Back-plane inter-face

External FIFO

USB CY7C68013

PC

control bus

Data bus control State

USB

Test system control module

Data bus

control bus

Data bus

Data

Figure 1. Physical layer hardware connection

2010 Third International Conference on Information and Computing

978-0-7695-4047-4/10 $26.00 © 2010 IEEE

DOI 10.1109/ICIC.2010.56

196

2010 Third International Conference on Information and Computing

978-0-7695-4047-4/10 $26.00 © 2010 IEEE

DOI 10.1109/ICIC.2010.56

196

III. PROTOCOL DESIGN

A. The design of data exchange protocol EZ2USB FX2 includes fixed 64 B endpoint buffer for

EP0，EP1IN and EP1OUT and 4 KB endpoint configured buffer for EP2,EP4,EP6 and EP8. EP2, EP4, EP6 and EP8 are data transmission endpoints with advantages of large-capacity and high-bandwidth, which can complete the external high-speed data transmission circuits without the interfere of firmware. These endpoints which have very flexible configurations can be configured in double, three or four buffer. When the speed of reading and writing data are similar, they can effectively increase the USB bandwidth, smoothing bandwidth jitter and reduce the wait time of both sides in order to adapt to different bandwidth requirements.

Taking into account system requirements of downloading and uploading data and commands, status and serial data, major endpoints including EP2, EP4, EP6, EP8 are fully used to be double buffer of 512 bytes to achieve different functions[3]. Figure 2 shows the connection method of the external logic and the FIFO endpoint such as EP2, EP4, EP6 and EP8. EP2 are configured to 16-bit output double buffer for downloading addresses, commands and data required by the test system; EP4 is used to control CY7C68013 for PC and produce the control commands to the FPGA; EP6 is configured to 16-bit dual-input buffer endpoint for uploading PCM codes, CAN data, test impedance data from the test system; EP8 is used to upload external FIFO status and power monitoring serial data through command strobe. CTL [1:0] are read signal and write signal generated by CY7C68013 GPIF after it is triggered, and RDY0 is status signal returning from the FPGA.

According to logic control relationship between FPGA and CY7C68013, as shown in Figure 3, in order to complete the transmission of data or commands from PC to the test system, firstly PC sends commands "14 6F" to EP4 endpoint of CY7C68013, and then single-chip sends handshake signal

EP81:0 EP6

EP4 EP2

FIFO

FD[15:0]

FLAGS SLRD SLWR SLOE SLRD

GPIF

Address, command, data

8051 RDY

8051 INT

2 CTL[1:0]RDY0

30MHz 48MHz

IFCLK

IFCLK

Figure 2. the connection method of GPIF mode endpoint EP2, EP4,EP6 and EP8

to FPGA through setting pin PA5 which means that the PC will download data. At the same time, FPGA sets data port as downlink state. CY7C68013 downloads data through EP2 endpoint by using FIFO write, one of the GPIF main control mode.

When test system uploads data, firstly the PC transmits the exterior FIFO reset commands “FA F2”to EP4, and then single-chip sends out a low pulse through PA0, when FPGA detects a low pulse, it will immediately reset the FIFO, and clear the FIFO data. Then PC sends out the command “FA F5” of reading the half-full status of FIFO, and CY7C68013 uploads the FIFO state through EP8. The PC judges PA4 whether to set at ‘0’. When FIFO reaches half-full state, the PC sends out the command “FC FE” of reading 32KB to EP4, and FPGA establishes the data port as the uploading condition, and uploads 32KB data through the EP6 automatically packing. The PC in the leisure time of USB bus will continue to read power monitor data through EP8 endpoint to display real-time voltage and current values.

For the realization of data communication of a communication protocol, the data format of the communication protocol must be unified so that data can be framed and unframed in accordance with the fixed format. Therefore, it is very important to design rational and clear message data form for stable, accurate and reliable data transmission. The correspondence’s data format between and USB module is as shown in Table 1.

The data is uploaded with the 16-bit format and downloaded with 10-bit format. Among them D8~D9 are the marking position, and D0~D7 are data position.

D9~D8: the combined expression indicates the downloading data format, ‘01’ denotes writing address character, ‘11’ means writing order character, ‘10’ indicates writing data

D7~D0 denotes address, order and concrete data

FPGALogic

controlFD[15 : 0]

GPIF

FIFO

CPU

USB

Control signalControl signal

data

CY7C68013

PC

PA5 PA0 PA1 PA4

WRCLKRCLK

Power Monitor

TXD0

Figure 3. logic control relationship between FPGA and CY7C68013

Table1 USB Communication data format

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15Upload data X X X X X X X X X X X X X X X X

Download data X X X X X X X X 0 1 0 0 0 0 0 0Address Card address District Address 1 0 0 0 0 0 0 0

Command Command 1 1 0 0 0 0 0 0Invalid data 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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B. Firmware program design The function of single-chip firmware is to communicate

on with the host and control partly the external device. In the Keil C development environment, frame program and peripheral control program are mainly developed. Frame program achieves the main cycle of USB communication, which achieves the initialization and enumeration of the USB controller, the implementation of devices and USB interrupt request, as well as suspend, wake-up management, and also the realization of the communication protocol USB2.0. In accordance with the protocol, USB devices can only work in a passive manner, and a request can only be sent by the host, through interpreting the firmware protocol layer to call corresponding subroutine to deal [4]. Peripheral modules achieve the connection and communication between peripherals and FX2. In the system, FX2 communicates with external FIFO with GPIF mode. GPIF is different from the past addressing system or the DMA way in the USB correspondence, which is a new interface compiled by users programming connection. Users can control the peripheral device and realize the peripheral device correspondence by designing the working wave pattern of every controlling foot [5].

This design uses the GPIF master control pattern, therefore the GPIF profile is needed to design. The GPIF Designer created by Cypress Corporation provides a very simple visualization window. The source document about waveform descriptor in *.c format can be produced by making some simple revision on the graphical interface. Figure 4 shows the waveform of CY7C68013 FifoRd mode. According to the time sequence of the external FIFO read operation, three states including S0, S1, S2 are defined as follows.

S0 is a non-decision state. Rclk signal maintains an IFCLK high level, and data bus access NEXTDATA.

S1 is a non-decision states, it degrades the signal Rclk three IFCLK clock cycle to ensure that the data from external FIFO have enough established time to ensure the accuracy.

S2 is a decision state to determine whether the external FIFO reaches half-full state. The external FIFO reaches the half-full state, GPIF adopts data bus used to read external data directly to the internal endpoint EP6 FIFO, and the data transmission does not require the involvement of CPU. When it does not meet the half-full state, the external FIFO will jump to the state of IDEL. If the status of the waveform

S0 S1 S2 IDLEStates

Data

Status

Wrclk

Rclk Figure 4. wave pattern of FifoRd mode

descriptor is less than seven, the state needs a clear directive to jump into the state machine IDEL state, which does not automatically enter the state IDEL.

A large amount of data can be read and downloaded for one time by compiling the waveform of FIFO read and FIFO write, and reasonable allocating control register.

C. Driver and dynamic link libraries design In this paper, we choose the universal USB driver

CyUSB.sys provided by the Cypress as the USB driver of this project so that development time can be saved. PC software is developed by LabWindows / CVI, and dynamic link library is needed to design in order to complete USB communication. Previous USB transmission adopted synchronous read-write mode, however, in a state of abnormal reading, USB device couldn’t receive data, which will block the channel access of reading. The only method to return to normal transmission is to pull the USB port. In order to solve this problem and improve the stability of the system, we adopt asynchronous I/O mode of reading. By calling such functions as BeginDataXfer, WaitForXfer, FinishDataXfer, a reading can be completed.

IV. CONCLUDE At present, data asynchronous exchange protocol based

on USB and FPGA has been successfully used in a missile telemetry universal test instrument project. The test results confirm that the data exchange protocol makes PCM code, CAN data, the test impedance value and the system self-test data with different rate uploaded simply, reliably and efficiently. Two level FIFO buffers in the physical layer can achieve high-speed transmission with the uploading speed value of 19.2MB/s. The programmable characteristic of CY7C68013 enhances the reliability of the system, its rich internal resources simplify the design of the physical level, and CY7C68013 shows strong anti-interference ability, all of these advantages of CY7C68013 contribute to transmit and deal with data in high speed, as a result, the cost of the project and development cycle can be reduced.

ACKNOWLEDGMENT Identify applicable sponsors here. Project supported by

the National Natural Science Foundation of China (Grant No. 60871041).

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