Investigating Noise Reduction Capabilities in CMOS Pre-Amplifier Circuits

M.Afham, S. Sakrani, N. Intan , Shahab.N, Asyraf

Shari ICmic-UniKL Academy

Cyberjaya, Malaysia afham@icmic-unikl.com

M. Amir Abas UniKL BMI, Gombak, Selangor

drmamir@bmi.unikl.edu.my

Abstract—This paper presents the design of low noise CMOS pre-amplifiers. Phone IC is one of the applications that pick-up voice signal from a microphone and the preamp amplifies to audible signal. Normally when the sound signal is very weak the amplifier amplifies signal as well as noise. This may result an amplified sound with low signal to noise ratio (SNR). A simulation study has been conducted to compare the noise characteristic of Claus’ and Eduard’s CMOS preamp design. The simulations were conducted by using SIMUCAD SmartSpice, mainly to analyze the gain of those design circuits, besides the input signal and noise spectral density for the SNR analysis. The result then is used to improve the SNR of CMOS based operational amplifiers and finally facilitate the actual design work of pre-amp using 0.18µm CMOS Technology.

Keywords—Preamp, Noise, SNR, Gain

I. INTRODUCTION The demand of high performance preamplifier in phone

industries has greatly increased. The industries require significant improved in size, noise reduction and performance. The size of preamplifier must be small which can be integrated together with microphone. Low noise specification is to ensure high quality of sound signals being captured and transmitted. Performance often relate to the power consumed by the small device which should be small.

Apparently noise is unavoidable and exists in any electronics devices. It cannot be eliminated but could be minimized. In CMOS microphone preamplifier it becomes highly demand and supersede the earlier version of preamp e.g. JFET microphone preamplifier with regards to its noise reduction capabilities and fair gain. The factors of noise reduction, Deruginsky [10] described that by implementing big area for devices contributing noise could reduce 1/f noise and white noise. Deruginsky also use PMOS device instead of NMOS. It has been studied that PMOS generates low noise compared to NMOS.

Therefore this paper is highlighting a minimizing technique for noise in electronics system by investigating Noise parameters: Noise Figure (F) and Signal-to-Noise Ratio (SNR).

Noise Figure is used for specifying the noise performance of a circuit or device. [1] It has been used to measure noise performance in communication systems where the source impedance is often resistive [1] while SNR indicates the strength of signals in an electronics system or the ratio between the powers of signal against the power of noise.

The next section of this paper describes the comparison of circuit performance in getting low SNR and followed by the simulation results. Some of the improvements from the previous designs were analyzed and discussed in Section IV. In Section V simulation results are presented to characterize the difference of noise-aware in preamp circuit techniques. Finally section VI and V concludes the findings of this research study.

II. PRE-PERFORMANCE ANALYSIS In this particular study all the simulation works were

carried out by using SIMUCAD Smart-Spice while SIMUCAD Gateway was used to design the schematic diagrams. Two preamp circuits were constructed namely Claus’s and Eduard’s preamps with the aim to study the circuit performance against the noise effect. The expected results from the simulation are noise spectral density curve (V2/Hz or A2/Hz) for the input and output of the circuits.

The two circuits as shown in Fig.1 and Fig. 2 were simulated using BSIM3v3 model library.

Fig.1: Claus’ Preamp Schematic

Fig.2: Eduard’s Preamp Schematic

M13, M14

2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), October 3-5, 2010, Penang, Malaysia

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III. RESULT AND ANALYSIS Fig.3 (a) shows the graph for the input Noise Spectral

Density Curve (iNSD). Eduard’s preamp (red) has iNSD 13.059 µV²/1 kHz, which is lower compare to Claus’ preamp iNSD 18.892 mV²/1 kHz. However the input noise reported in [1] is much lower than the simulated result (Eduard’s iNSD=550 nV²/1 kHz, Claus’ iNSD = 1 mV²/1 kHz), the differences are presumed due to the different model and parameter for simulation model. It is known that BSIM3v3 has accurate model compared to BSIM [4].

Fig.4 shows the graph for the output Noise Spectral Density Curve (oNSD). Eduard’s preamp (red) has oNSD 1.8559 aV²/1 kHz, while Claus’ has preamp (blue) oNSD 433.64 zV²/1 kHz.

Fig.3 (a): Graph of input Noise Spectral Density Curve; Blue is Claus’s Preamp, and Red is Eduard’s preamp The source of the noise in both circuits is expected

comes from the flicker noise (1/f noise) due to the range of bandwidth that generate noise is in MHz. In this simulation Claus’ preamp design exhibits low input and output noise compare to the Eduard’s preamp design.

Fig.3 (b): To justify the Eduard’s Preamp Graph of input Noise Spectral Density Curve was not a straight line.

Fig.4: Graph of output Noise Spectral Density Curve; Blue is Claus’s Preamp, and Red is Eduard’s Preamp.

IV. DESIGN PROPOSAL The results of section III were used to construct an

extension for both circuits. A differential stage has been applied with the aim to study the effect of noise. Prior to the implementation, in Claus’ preamp, PMOS is used which structurally has more holes than electrons. As a result Claus’ preamp has much lower noise compare to the Eduard’s preamp. It is also known that PMOS generates 2 to 5 times less flicker noise than NMOS transistors due to electron permittivity. [5]

The basic concept is at input transistors size, they can be larger than other transistors within their stage to help reduce the overall noise in the circuit, at the same time to increase their transconductance which help in increasing the gain of the preamp.

Fig.5: Two differential-stage of Eduard’s preamp.

( )4184 MdsMdsMdsMd rrrgmA ⋅⋅⋅= (1) A two-differential stage was also introduced to improve

the preamp gain. In Fig.5, the gain of the preamp is derived from the equation 1. It is noticed that Claus’

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preamp implements folded-cascode topology which can improve its input swing besides to increase the gain. Refer to Fig.1, the drain terminals of M13 and M14 (output of the differential-stage), is connected to the source terminal of M17 and M18. Meanwhile the gain can be re-calculated using equation 2. As a result the gain for the Claus’ design has much higher than Eduard’s design, where Claus generates 120 dB while Eduard has 63 dB.

( )[ ] ( ){ }16164131018181311 ooooo rgmrrrrgmgmgmA ⋅⋅⋅⋅= (2)

( )( )dBNoisedBSignal

SNRinput

inputinput = (3)

output

input

SNRSNR

F = (4)

The SNR for both circuits were also calculated using

(3) to identify which has higher SNR. Claus’ preamp design has SNR 48.85 dB, compare to Eduard’s preamp design contributes 0.26 dB, which is hundreds times smaller than Claus’.

V. ANALYSIS AND IMPROVEMENT There are two proposed ideas that have been identified,

studied and simulated to improve the performance of the preamp. First, the study was investigating for the input signal of the preamp. It has been studied that passive component and active resistance can contribute high noise signals. In the simulation works (refer to Fig. 3(a)), the flicker noise is quite significant in the Claus’ design compare to Eduard’s design. The impact is highly caused by the number of passive components in the circuit compared to Eduard’s preamp. On the other hand Claus’ design uses PMOS transistor as its switching devices which contributes great release in the overall noise effect to the circuit performance.

Second factor that could contribute good SNR value is by increasing the gain. There are many topologies could be applied to increase the gain of the two circuits, however in this particular study the differential stage and the second stage techniques have been studied and analysed. After the simulation analysis in section III, Claus’ design shows great impact to reduce the noise effect but slightly reduce the gain of the circuit. To re-solve the unexpected characteristics of the Claus’ design an additional folded-cascode topology is added to boost up the gain of its preamp design. In Eduard’s design a differential stage is applied to boost up the gain but cause the design to generate higher noise at the output stage compared to the Claus’ design.

VI. FINAL DESIGN In the final design stage, the schematic diagram as shown in Fig. 6 was constructed and simulated. The thorough analysis was carried out to ensure the operation is fulfilling all the specifications as discussed in earlier section.

In the simulation work, parameter variations against process corner were investigated. Process corner involves a circuit running on devices fabricated at which may run slower or faster than specified and at lower or higher temperatures and voltages. The design margin considered

inadequate if the circuit does not function at all at any of these process extremes.

Fig.6: R2R Opamp Schematic Two types of differential-stage are used for this design

in order to allow the circuit to operate within Rail-to-Rail (R2R) input range, which is from VSS to VDD. The width over length for the PMOS differential-stage is higher than NMOS differential-stage in order to maintain the stability of the circuit operation, besides its low noise characteristic. Folded-cascode stage is implemented based on analysis studied from the Claus’s design, to improve the gain and the input swing of the input stage. Fig. 6 has been simplified its design by putting label at where the biasing circuits have been implemented.

Fig. 7, 8, 9, 10, 11, 12, 13 and Fig. 14 are input and output noise spectral density analysis of Fig. 6. The Fig. 6 schematic simulation ran together with its biasing circuits, to have its total noise. Fig.7 (input noise) and Fig. 8 (output noise) are the result of noise at difference process corner at 27°C, where the design has low input and output noise variation over process corner:

• Input Noise Different: 12.92 aV²/1 kHz ≥ typical

input noise ≥ -15.05 aV²/1 kHz, • Output Noise Different: 1.582 pV ² /1 kHz ≥

typical output noise ≥ -1.305 pV²/1 kHz. Significantly the results are very low compared to

Claus’s and Eduard’s preamp design. Fig. 9 till Fig. 14 is the input and output noise spectral

density based on temperature variance against the process corner. Temperature -40°C, 27°C, 85°C and 125°C have been chosen for comparison because those temperatures are also used in the benchmark datasheets. The process corner used for comparison is typical, fast and slow. Overall average difference between the minimum and maximum value of the noise for the input is around 470.29 aV²/1 kHz and the output is 16.594 pV²/1 kHz. The input noise figure is seems to be large but the prefix of the figure is small, so it is also to be considered as a small different, which in prefix at to (a), ten to the power of negative eighteen.

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Fig.7: Comparison of Noise Input Spectral Density of R2R at 27°C for different Process Corner; fast, typical and slow.

Fig.8: Comparison of Noise Output Spectral Density of R2R at 27°C for different Process Corner; fast, typical and slow.

Fig.9: Comparison of Noise Input Spectral Density of R2R at -40°C for different Process Corner; fast, typical and slow.

Fig.10: Comparison of Noise Output Spectral Density of R2R at -40°C with Process Corner; fast, typical and slow.

Fig.11: Comparison of Noise Input Spectral Density of R2R at 85°C for different Process Corner; fast, typical and slow.

Fig.12: Comparison of Noise Output Spectral Density of R2R at 85°C for different Process Corner; fast, typical and slow.

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Fig.13: Comparison of Noise Input Spectral Density of R2R at 125°C for different Process Corner; fast, typical and slow.

Fig.14: Comparison of Noise Output Spectral Density of R2R at Slow Fab Process Speed with Temperature Variance; 127°C, 85°C, 27°C and -40°C.

VII. PHYSICAL FACTOR Layout also play very signification factor to reduce

noise in many CMOS circuits. The correct technique should be emphasized in minimizing the noise. First the pair PMOS transistors are multi-fingered using fingering method and inter-digitated to avoid mismatched and offsets. Next symmetry is employed together with the cross-couple technique in the layout to reduce sensitivity for compensating process variations (process corner) and improve matching issue to help improves supply noise rejection. Guard rings are also implemented as close as possible around the transistors for isolation. Routing within the circuit is minimized to avoid parasitic between metals and active devices. The layout for the pair PMOS transistor with all the implemented techniques is shown Fig.15.

Fig.15: Fingering, Cross-Couple, and Symmetry Layout of Pair PMOS.

VIII. CONCLUSION In general R2R is an adaptation of Claus’ and Eduard’s

design which has great impact in noise reduction. The evaluation of the two designs is to facilitate the design of R2R for the application circuit, Phone IC. The next stage of this research work is to investigate the interconnect issues of the full preamp layout with the application block and finally to test the functions of the whole design.

ACKNOWLEDGMENT Special thanks to the main supervisor, M.Amir Abas for

guidance and motivation toward completing this paper, field supervisor, S.Sakrani, Shahab A. Najmi, team members N.Intan and Asyraf Shari for the discussion and guidance toward the completion of the circuit design, UniKL BMI and ICmic-UniKL Academy Sdn Bhd, for facilitating to pursuit my master degree and providing EDA tools for my research study.

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