+– RC

L

Vg

1

2

i+

v

_

Vref

+

_

Gc(s)VM = 1

PWM u

c

Switching power converter

H v

dTs

H = 1

Figure 1(a): Switching DC-DC converter with analog voltage-mode control

vref

+

_

Gc(s)u

v

Ts

Equivalent hold

Gh(s)

d Tsδ(t − nTs), d = u

Figure 1(b): Small-signal sampled-data model of the analog-controlled DC-DC

converter

sTnd ]1[ˆ −

sTn )1( − snTss TDTn ')1( +−

]1[ˆ −nx

dx

]1[ˆ −Φ nx

]1[ˆ −ndγ

12

ps tt =

)(tx

)(ˆ)( txtx +

sTnd ]1[ˆ −

sTn )1( − snTss TDTn ')1( +−

]1[ˆ −nx

dx

]1[ˆ −Φ nx

]1[ˆ −ndγ

12

ps tt =

)(tx

)(ˆ)( txtx +

Figure 1(c): Waveforms illustrating the discrete-time model derivation for the

analog-controlled DC-DC converter

Small-signal Discrete-time Modeling of

Digitally Controlled DC-DC ConvertersDragan Maksimovi and Regan Zane

Colorado Power Electronics Center

Department of Electrical and Computer Engineering

University of Colorado at Boulder, USA

Email: maksimov, zane@colorado.edu

Abstract—The paper presents an exact small-signal

discrete-time model for digitally controlled dc-dc converters.

The model, which is based on well-known approaches to

discrete-time modeling and the standard Z-transform, takes

into account modulator effects and delays in the control loop.

The model is well suited for direct digital design of digital

compensators.

I. INTRODUCTION

Discrete-time modeling of dc-dc switching converters has

had a long history of contributions, including [1-6]. Recently,

the growing interest in practical digital control for high-

frequency DC-DC converters has prompted renewed interest in

discrete-time analysis and modeling to facilitate precise direct-

digital compensator design. Delay effects in averaged models

have been discussed in [7]. However, with the exception of [6],

the modulator effects and the effects of delays in the digital

control loop have not been fully taken into account. The

approach presented in [6], which is based on the modified Z-

transform, is straightforwardly applicable only to buck-type

converters. In this paper, we propose a simple extension of the

well-known discrete-time modeling approaches [1-4] to take

into account the modulator effects and the delays in a digitally

controlled converter. The result is an exact small-signal

discrete-time model applicable to any converter.

II. DISCRETE-TIME MODELING

Our approach to discrete-time modeling of digitally-

controlled converters is an extension of the well known

discrete-time modeling approach for constant-frequency pulse-

width modulated (PWM) analog-controlled converters [1-4].

The approach is briefly reviewed with reference to Figure 1.

Figure 1(a) shows a DC-DC converter (e.g. a buck converter)

with a standard analog voltage-mode controller. In the

discussion, without loss of generality, we assume a sensing

gain of H = 1, and a constant-frequency naturally-sampled

trailing-edge PWM with a saw-tooth amplitude VM = 1. The

converter operates in continuous-conduction mode. In each

state of the switch (1 or 2), the converter circuit is linear, time-

invariant, with the corresponding state-space description:

,2,1, =+=

+=

iVexCy

VbxAx

gii

gii (1)

where x is the vector of converter states (e.g. inductor current

and capacitor voltage, x = [v i]T), and the input voltage Vg is

constant, since we are interested only in the control-to-output

responses. The solution to (1) for operation within a single

switch state is given by

0-7803-9724-X/06/$20.00 ©2006 IEEE.

231

2006 IEEE COMPEL Workshop, Rensselaer Polytechnic Institute, Troy, NY, USA, July 16-19, 2006

0-7803-9725-8/06/$20.00 ©2006 IEEE.

+– R

C

L

Vg

1

2

i

+v_

Vref

+

_

Gc(z)VM = 1

DPWM u

c

Switching power converter

H v

dTs

H = 1

A/D

+

vout

_

RL Resr

Figure 2(a): Switching DC-DC converter with digital voltage-mode control

vref

+

_

Gc(z)

vd[n]Ts

Equivalent hold

Gh(s)

Ts

u[n]Delay

td

Figure 2(b): Small-signal model of the digitally-controlled DC-DC converter

sTnd ]1[ˆ −

sTn )1( − snT1)1( ds tTn +−

]1[ˆ −nx

dx

x]1[ˆ −Φ nx

]1[ˆ −ndγ

1 2

st

)(tx

)(ˆ)( txtx +

2

pt

1dt

1)1( dss tDTTn ++−

sdd DTtt += 1 sTnd ]1[ˆ −

sTn )1( − snT1)1( ds tTn +−

]1[ˆ −nx

dx

x]1[ˆ −Φ nx

]1[ˆ −ndγ

1 2

st

)(tx

)(ˆ)( txtx +

2

pt

1dt

1)1( dss tDTTn ++−

sdd DTtt += 1

Figure 2(c): Waveforms illustrating discrete-time model derivation for the

digitally-controlled DC-DC converter

ττdbVexetx g

t

tA

o

tA ii −+=0

)()( , (2)

where xo is the initial condition and the matrix exponential can

be expressed as:

+++==∞

=

22

0 2!t

AAtIt

n

Ae

n

nn

At . (3)

Figure 1(b) shows a small-signal sampled-data model

according to [2, 8]. The pulse-width modulator is a sampler,

the output of which is a string of delta functions

)(ˆss nTtTd −δ . Note that a sampling instant tp = nTs coincides

with the modulated edge of the trailing edge PWM output

signal, i.e. with the switch transition from state 1 to state 2, as

illustrated by the waveforms of Fig. 1(c). The samples

)(ˆss nTtTd −δ affect the converter state perturbations x

through the equivalent hold Gh(s) which models the converter

responses between the samples. The complete small-signal

continuous-time model in [8] included derivation of the

equivalent hold Gh(s). Since we are interested only in the

values ][ˆ nx of the state variables at the sampling instants, the

derivation of Gh(s) is not necessary.

We proceed by finding the discrete-time model according to

the waveforms shown in Fig. 1(c). The output can be written as

a linear combination of the small-signal state and duty cycle

perturbations,

]1[ˆ]1[ˆ][ˆ −+−Φ= ndnxnx γ . (4)

The matrix and vector coefficients can be solved by

propagating the effect of each perturbation during the

converter switch states according to (1) and (2) and Fig. 1(c).

Consider first the effect of only a perturbation of the states.

The resulting perturbation after one period is given by:

( )0ˆ

]1[ˆ][ˆ 21

=

′ −=d

TDADTAnxeenx ss . (5)

D is the steady-state duty ratio and D’ = 1 − D. Next, consider

only the effect of perturbation in the duty cycle. The initial

perturbation in the states dx occurs at the modulation edge of

the PWM output signal and can be written from (1) as linear

extensions of the previous and next switch states:

( ) ( ) sgpsgpd TdVbXATdVbXAx ˆˆˆ2211 +−+= , (6)

where Xp are the steady-state states at the PWM sampling

instant, Xp = x(tp). The perturbation dx then propagates

through the system over one period in the same manner as

given in (5). Thus, the model of (4) can be written in the

following form:

]1[ˆ]1[ˆ][ˆ −+−Φ= ndnxnx γ ,

ss TDADTAee

'21=Φ ,

sTαγ Φ= ,

( ) ( ) gp VbbXAA 2121 −+−=α . (7)

The model (7) is the same as the discrete-time models

presented in [1,2].

III. ACCOUNTING FOR DIGITAL CONTROLLER DELAYS

Let us now consider the digitally controlled converter shown

in Fig. 2(a). The A/D converter samples the output voltage

error. The error signal samples are processed by a discrete-time

compensator Gc(z). The compensator output samples u[n]

control the switch duty cycle via a digital pulse-width

modulator (DPWM). This modulator can be viewed as a D/A

converter including a sample-and-hold followed by the PWM

232

sampling as shown in Fig. 2(b). The resulting relationship

between ][ˆ nu and ][ˆ nd is represented by the total delay td

between the A/D sampling at ts = nTs and the PWM sampling

at tp, as illustrated by the waveforms shown in Fig. 2(c). In a

practical realization, the total delay td includes the A/D

conversion time, the computation delay (i.e. the time it takes to

compute u[n]), as well as the modulator delay (i.e. the time

between the update of u[n] and the switch transition from state

1 to state 2). It is important to note that a sampling instant

ts = nTs in Fig. 2 now corresponds to the time the A/D

converter samples the output voltage error, whereas the PWM

sampling at tp is delayed by td with respect to the sampling

instant. This is the key difference between the models in

Fig. 2(b) and Fig. 1(b). To account for the delay td, which is

not necessarily an integer multiple of the sampling period Ts,

reference [6] employs the modified Z-transform. The

derivation is more complicated and straightforwardly

applicable only to buck-type converters. Instead, we follow the

same steps as in the derivation of the discrete-time model (7).

Figure 2(c) shows the relevant waveforms with trailing edge

modulation for the case when sds TtDT ≤≤ . Note how the

sequence of states and the time the modulator affects the state

perturbations are different compared to the waveforms in

Fig. 1(c). A similar figure can be drawn for the case when

sd DTt ≤≤0 , which places the A/D sampling instant ts during

switch state 1. The resulting model for both time delay cases is

as follows:

]1[ˆ]1[ˆ][ˆ −+−Φ= ndnxnx γ , (8)

<≤≤≤=Φ −

−−

sdtATDAtDTA

sdsDTtADTAtTA

DTteee

TtDTeee

dsds

sdsds

0,

,

121

212

')(

)()(

, (9)

<≤≤≤= −

−

sdsTDAtDTA

sdsstTA

DTtTee

TtDTTe

sds

ds

0,

,')(

)(

21

2

ααγ , (10)

( ) ( ) gp VbbXAA 2121 −+−=α , (11)

A delay td greater than Ts, td = kTs + td’, can be taken into

account by replacing ]1[ˆ −nd with ]1[ˆ knd −− and td with td’.

The output state-space equation can also be added according

to (1) as follows:

][ˆ][ˆ nxCny i= . (12)

Note that Ci is the state-to-output matrix in the subinterval

when the A/D sampling occurs (subinterval 2 according to the

timing diagram in Fig. 2(c)). The standard Z-transform of (8)

and (12) gives the desired discrete-time control-to-output

transfer functions.

Although the model (8)-(12) has been derived for the

trailing-edge PWM, the same approach can be extended to

leading-edge or triangle-wave PWM. Similar figures to

Fig. 2(c) can be drawn with duty cycle perturbation(s) on the

appropriate edge(s). Again, the A/D sample instant ts can be

considered for the two cases of occurring during switch state 1

or 2. Note that the previous interval perturbation in states

]1[ˆ −nx is always placed at the A/D sampling at ts = (n-1)Ts .

The resulting model for leading-edge PWM is still in the form

of (8) with coefficients given by:

<≤≤≤

=Φ −

−−

sd

tADTAtTDA

sds

TDtATDAtTA

TDteee

TtTDeee

dsds

sdsds

'0,

',

212

121

)'(

)'(')(

, (13)

<≤≤≤

= −

−

sds

DTAtTDA

sdss

tTA

TDtTee

TtTDTe

sds

ds

'0,

',

12

1

)'(

)(

ααγ , (14)

and (11) is still valid.

IV. BUCK CONVERTER MODEL EXAMPLE

As an example, consider the buck converter of Fig. 2(a) with

trailing edge PWM and: L = 5 µH, RL = 25 mΩ, C = 5 µF,

Resr = 16 mΩ, R = 1 Ω, Vg = 10 V, Vref = 2 V, D = 0.2,

fs = 1/Ts = 1 MHz. In the buck converter, A1 = A2 = A, b1 = b,

b2 = 0, C1 = C2 = C, ei = 0. The coefficients in (1) are given by:

( ) ( )+−+−

++−

=

LRRR

LRR

R

CRR

R

CRRA

esrL

esr

esresr

1||

1

)(

1

, (15)

==L

bb 10

1 , (16)

+= esr

esr

RRRR

RC || , (17)

=i

vx , outvy = . (18)

Note that only the output voltage vout is used in (18) since the

primary interest is in solving the control-to-output voltage

transfer function. In order to simplify the analysis, losses are

neglected except for the dominant effect of the capacitor ESR,

Resr, in (17). Resulting simplified equations for A and C are

given by:

−

−

≈0

1

11

L

CRCA , (19)

[ ]esrRC 1≈ , (20)

for RRRR Lesr <<<< , . The model (8)-(10) then simplifies

to:

233

103

104

105

106

-450

-360

-270

-180

-90

0

Phase (

deg)

-40

-20

0

20

40

Magnitude (

dB

)

Bode Diagram

Frequency (Hz)

Figure 3: Magnitude and phase responses of Gvd(z) for the digitally-controlled

buck converter example operating at fs = 1 MHz, Resr = 16 mΩ, for four values

of the total delay td: td = 0 (blue), td = 0.2Ts (green), td = 0.5Ts (red), td = Ts

(cyan).

-60

-40

-20

0

20

40

Magnitude (

dB

)

103

104

105

106

-270

-225

-180

-135

-90

-45

0

Phase (

deg)

Bode Diagram

Frequency (Hz)

Figure 4: Magnitude and phase responses of Gvd(z) for the digitally-controlled

buck converter example operating at fs = 1 MHz, td = 0.5Ts, for four values of

the capacitor ESR: Resr = 0 Ω (blue), Resr = 8 mΩ (green), Resr = 16 mΩ (red).

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

Root Locus

Real Axis

Imagin

ary

Axis

Figure 5: Root loci for the digitally-controlled buck converter example

with a proportional compensator, Gc = const, Resr = 16 mΩ for four values

of the total delay td: td = 0 (blue), td = 0.2Ts (green), td = 0.5Ts (red),

td = Ts (magenta).

]1[ˆ]1[ˆ][ˆ −+−Φ= ndnxnx γ , (21)

sATe=Φ , (22)

sgtTA

TbVe ds )( −=γ , sd Tt ≤≤0 (23)

][ˆ][ˆ nxCny = . (24)

Approximate expansions of the matrix exponentials in (22)

and (23), such as sAT

ATIe s +≈ or the alternatives proposed

in [5], can be employed to obtain an approximate closed-form

analytical discrete-time model. Using the

approximation sAT

ATIe s +≈ , the Z-transforms of (21) and

(24) yield the control-to-output transfer function in closed

form:

)(

)()(

ˆ

ˆ)(

zD

zNCRtT

LC

TV

d

vzG esrds

sgoutvd +−≈= ,

+−−−+−

+=s

desrds

s

esresr

esrds

s

T

t

L

RtT

T

CR

R

R

CRtT

TzzN

)()( ,

+−+−−=LC

T

RC

Tz

RC

TzzD sss

22 12)( . (25)

Notice that the zero of the control-to-output voltage transfer

function depends on the total delay td in the control loop,

while the poles are not affected by the delay. It is also

interesting to note that the capacitor ESR does not add another

zero. Rather, it just shifts the zero in the direction opposite to

td. Figure 3 shows the magnitude and phase responses of Gvd at

the nominal Resr = 16 mΩ for td = 0, td = 0.2Ts, td = 0.5Ts, and

td = Ts. The delay effects are clearly visible, especially in the

phase responses. Figure 4 shows the magnitude and phase

responses of Gvd at td = 0.5Ts for Resr = 0 Ω, Resr = 8 mΩ and

Resr = 16 mΩ. The additional phase lead from the ESR zero

can be seen.

V. MODEL VERIFICATION AND DISCUSSION

To further verify the model validity, let us assume a simple

proportional compensator, Gc = constant in the digitally-

controlled converter of Fig. 2(a). Figure 5 shows the root-loci

for different values of the total delay td. Increasing Gc causes

one or both closed loop poles to leave the unit circle. The

model predictions for the stability boundary are shown in

Table 1. Transient simulations of the system are shown in

Fig. 6 for the case of Resr = 16 mΩ and td = 0.5Ts. The

Simulink model used is shown in Fig. 7, which is a transient

switching model of the system in Fig. 2(a) including the effects

of delay td, A/D sampling, PWM and Resr. The results are

shown after 1 ms of a startup transient. Waveforms shown

include the output voltage vout and the duty cycle command. It

can be seen that poles just within the stability boundary result

in a lightly damped system whereas the case with poles just

outside the stability boundary result in an under-damped

system. The simulation results reach a steady-state oscillation

in the under-damped case due to duty cycle saturation.

td = 0

td = Ts

Resr = 16 mΩ

Resr = 0 Ω

td = 0

td = Tstd = 0.5Ts

td = 0.2Ts

234

1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2

x 10-4

1

1.5

2

2.5

vout

1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2

x 10-4

0

0.2

0.4

0.6

0.8

duty

time

Figure 6: Startup transient Simulink simulations of the digitally controlled

buck converter example with a proportional compensator Gc = const. Shown

are the output voltage, vout, and duty cycle command with Resr = 16 mΩ and

td = Ts for two cases on each side of the model stability boundary: Gc = 0.45

(blue) and Gc = 0.65 (red).

Total delay td

Gain Gc at

the stability

boundary

0 8.9

0.2 Ts 4.7

0.5 Ts 1.3

Ts 0.55

Table 1. Verification of the model stability predictions: shows the

proportional gain Gc = constant values at the stability boundary. Results match

those obtained by transient Simulink simulations in Fig. 6.

Examples of direct digital design of PID and higher-order

compensators based on the discrete-time model presented in

this paper are discussed in [9,10].

VI CONCLUSIONS

The paper presents an exact small-signal discrete-time model

for digitally controlled DC-DC converters. The model, which

is based on well-known approaches to discrete-time modeling

and the standard Z-transform, takes into account modulator

effects and delays in the control loop. An application example

is presented, including validations of stability boundaries

predicted by the model against transient system simulations.

The model is well suited for direct digital design of digital

compensators.

REFERENCES

[1] D. J. Packard, “Discrete modeling and analysis of switching regulators,”

Ph.D. Thesis, California Institute of Technology, November 1976.

[2] A.R.Brown, R.D.Middlebrook, “Sampled-data modeling of switching

regulators,” IEEE PESC 1981.

[3] G.Verghese, U.Mukherji, “Extended averaging and control procedures,”

IEEE PESC 1981.

[4] G.C.Verghese, M.E.Elbuluk, J.G.Kassakian, “A general approach to

sampled-data modeling of power electronic circuits,” IEEE Trans. PE,

Vol.1, No.1, pp. 76-89, April 1986.

[5] V.Rajasekaran, J.Sun, B.S.Heck, “Biliner discrete-time modeling for

enhanced stability prediction and digital control design,” IEEE Trans.

PE, Vol.18, pp.381-389, January 2003.

[6] D. M.Van den Sype, K.De Gusseme, A.P.M.Van den Bossche,

J.A.Melkebeek, “Small-signal z-domain analysis of digitally controlled

converters,” IEEE Trans. PE, Vol.21, No.2, pp.470-478, March 2006.

[7] J.Sun, D.M.Mitchell, D.E.Jenkins, “Delay effects in averaged modeling of

PWM converters,” IEEE PESC 1999.

[8] B.Y.B.Lau, R.D.Middlebrook, “Small-signal frequency response theory

for piecewise-constant two-switched-network dc-to-dc converters,” IEEE PESC 1986.

[9] T. Takayama, D. Maksimovic, “Digitally controlled 10MHz monolithic

buck converter,” COMPEL 2006.

[10] H. Hu, V. Yousefzadeh, D. Maksimovic, “Nonlinear control for improved

dynamic response of digitally controlled dc-dc converters,” IEEE Power

Electronics Specialists Conference, June 2006, pp. 2584-2590.

1

s

capacitor

Zero-Order

Hold

1.8 Vref

10

Vg

Scope

Saturation

0.016

Resr

uc

PWM

Modulator

1

s

Inductor

0.65

Gc

Delay td1Delay

A/D sampling

1/1

1/R

1/5e-6

1/L

1/5e-6

1/C

u

u

iL

iL

v out

vout

Figure 7: Simulink model of the buck converter system in Fig. 2(a), including effects of delay td, A/D sampling, PWM and capacitor ESR zero.

235