NOTCHING CURRENT SOURCE AC/AC CONVERTERS FOR SOFT SWITCHED PWM

E d " R C. da Silva Dept. of Electrical Eng.

Federal University of Paraiba Caixa Postal 10.105

58.109-970 Campina Grande, PB. - Brazil

Abstract - This paper presents new dc link notclung current ac/ac converters with the feature of variable flat-topped current pulse width. Notches in the link current allow front rectlfier and current source inverter's switches to commutate at zero crossing and to synchronize with PWM strategy. Part of these new topologies has the additional ability to operate with adjustable notch width without any increase in devices' voltage stress. Design considerations for implementation of the converter and simulated results are presented.

I. INTRODUCTION

Series resonant dc-link converters (SRDCLC) were introduced to reduce device switchmg losses [1.2] in current source inverier (CSI) operating with PWM modulation. In SRDCLC, switching occurs only at zero crossing instants of the link current. Although these converters are able to operate at high power, they can only work at constant frequency and cannot synchronize with exzernal PWM strategies.

An alternative technique uses an auxiliary commutation circuit to &vert current from dc link and references [3] and [4] presented different converter topologies for soft switchmg. In these converters, a resonant transition provides a quasi-square-waveform for the dc link current pulses so that notches produced in the dc link current allow rectifier and inverter switches to commutate at zero current. Very recently, same features were obtained with a circuit that uses fewer components [5]. On the other hand, reference [6] showed the advantages of synchronizing current

Ld - -

Fig. 1 Current source inverter . ACC = Ausiliary Commutation Circuit

pulses of the dc link with the firing of the inverter switches. However, all converters mentioned above must have a minimal notch width to avoid h g h voltage stress on switchmg devices. Therefore, modulation indices must be restricted to h g h values, unless is provided a short circuit path for dc link current through the inverter itself. Unfortunately, these strategy results in a dc link current boost effect.

This paper introduces new topologies of the soft-switched notching current converter with the feature of variable flat-topped current pulse width. Part of these new converter circuits has the addtional ability to operate with adjustable notch width in the dc link current. without increasing the voltage stress on switching devices. T h s paper also indicates a procedure for design and topology choice. Finally, it establishes feature Merences among the proposed topologies and uses simulated results to demonstrate the feasibility of the method.

11. PRINCIPLES

The notching current source ac/ac converter in Fig.1 can be considered as composed by a front rectifier, a dc link reactor in parallel with an auxiliary commutation circuit (ACC), and an output inverter. Fig. 2 shows the equivalent circuit for this converter. As the input and output filter capacitors are much larger than other capacitors in the ACC, these elements can be represented by the voltage sources V, and V,. A switch T, represents four switches in series (two from the rectifier and two from the inverter).

The auxiliary commutation circuit. which can be

L f Ts

+ Vd

I 1 - I Fig. 2. Simplified circuit

0-7803-1993-1194 $4.00 0 1994 IEEE 1007

Dr Tr' (a) ACCl and (b) ACCP and (C) ACC3 and (d) ACC4 and (e) ACCS and (9 ACC6 and

ACCl D ACCPD ACCBD ACC4D ACCSD ACC6D

Ld Lo

..-, .:.m .... ......-. i .I............ . ... . . . ..+y .... .. . ... . . . . . . . .. . c.. . . . . . . . . . .......... ; d .......... Lc'

Lc

(9) ACC7 and (h) ACC8 and (i) ACCS and (j) ACC10 and (k) ACCl l and ACC7D ACC8D ACC9D ACCl OD ACCl 1 D

Fig. 3. Auxiliary commutation circuits

any one of the circuits presented in Fig. 3, diverts current from dc link. As a consequence, notches are introduced in dc link current, thus producing a quasi-square-waveform for dc link current pulses. Since the inductance L, is large enough to work as a current source, inductances and capacitances in the auxiliary circuit decide the resonant frequency. In this paper, the auxiliary circuits of Fig. 3 that include the dashed component (accelerating device) are referred as ACCD. Circuits without this dashed device are referred as ACC.

A. Usual inodes of operation The principle of usual operation for the proposed

circuits may be described with the help of the equivalent circuit shown in Fig. 4. in which the commutation circuit ACC 1D is used.

For usual operation, seven modes (usual sequency) are identified during an operation cycle, as shown in Fig. 4.

(a) Mode 1 (t,-to): Initially, current I, is flowing through Lo, T, and load. The polarity of capacitor C is as shown in Fig. 4.

(b) Mode 2 (t2-t,): Thyristor T, is turned-on and initiates a resonance between C and L, (first resonant interval). Then, the capacitor voltage vL oscillates from +V, to -Vc.

(c) Mode 3 (tl-t2): Switch T, keeps conducting. (d) Mode 4 (tl-to): When switch T, turns-on. the

current in Lo is softly transferred to the capacitor C. At same time a second resonance is initiated between C and L,, now through thyristor T,.

(e) Mode 5 (t,-t,): When current i, reaches the value of I,, current is becomes zero and the notch interval starts.

(f) Mode 6 (ti-to): The capacitor charge is com-

Simplified circuit (a) Mode 1 (tl-0)

+ fEpiz!:-gfl+m Vd

Vd Lr Tr

(b) Mode 2 (t2-tl) (c) Mode 3 (t3-t2)

Vd

(d) Mode 4 (t443) (e) Mode 5(t5-t4)

- - I - J (9 Mode 6 (t6-t5) (9) Mode 7 (t7-t6)

Fig. 4. Modes of operation for the circuit ACClD

pleted linearly. Thyristor T, is ensured to be off only if the reverse voltage interval of time is larger than the device's turn-off time t,.

(g) Mode 7 ( ti-to): From the instant in whch v,,=E+v,-V, becomes positive, thyristor T, may be turned-on again. Control circuit defines at what voltage T, must be turned-on. Turn-on of T, starts current transfer from auxiliary commutation circuit to circuit L,-T,-load.

Fig. 5 shows the principal waveforms denoting operation of the circuit. Minimal conduction time Ats for the switch T, is defined by the first resonant interval. The second resonant interval defines the minimal notch interval. At,.

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Fig.5 Principal waveforms for the circuit with ACC 1D

A variation of topology ACClD replaces the thrd auxiliary thyristor T, by a diode. In t h s

case T, has to be turned-on 7'cm s before the commutation of T, starts.

B New modes of operation Modified topologies ACC2(D), ACC4(D).

ACC6(D), ACC9(D), ACClO(D) and ACCl 1(D) expose new modes of operation To understand these new modes. consider now the equivalent circuit that uses the commutation circuit ACC3D, as shown in Fig 6

Fig. 6. Simplified circuit for CSI with ACC2D

Suppose that current Id is flowing through the circuit L,-T;load, and that the polarity of capacitor C is as shown in Fig.6. The initial sequence for commutating T, is the same as for usual operation modes presented in Fig. 4. New modes are possible after mode 6. and are presented in Fig. 7. Suppose that the zero current interval must synchronize with the PWM pattern. If T, is turned-on. instead of T,, capacitor voltage oscillates from Vc to -V, (mode IN). Switch T, keeps conducting and L, is short-circuited (mode 2N). Turn-off of T, is achieved by turn-on of T, (modes 3N and SN). Current I,, is then transferred to C (mode 5N) and

T, can be tumed-on again. These new modes determine an adjustable notching width. Fig. 8 shows the principal waveforms that describe the new modes. The combination of the sequence of usual modes and the sequence of these new modes will be referred as New Sequence Z(NS1).

Ld Ld

(a) Mode 1 N (t8-17) @) Mode 2N (t9-t8)

Vd +lF& F-17fi-J + 'Fi + Vd lpTa FlqfPz$?Fj

Tr r

(c) Mode 3 N (tl049) (d) Mode 4N (tl 1 41 0) Ld Lo Ts

(e) Mode 5N (t12-tll) (9 Mode6N (t13-t12)

Fig. 7. New modes in Sequence 1 (NS1)

' tsm

t i 2

Fig. 8. Principal waveforms for NSl

Fig. 9 indicates another possible sequence for the new modes (New Sequence 2 - NS2). Suppose that initial conditions are the same as in the previous case. T, turns-on and initiates a resonance between C and I,, (mode IN'). Suppose that the switch T, turns-on simultaneously with T,. At the moment in which the switch T, is forward biased the current flowing in T, is transferred to the auxiliary circuit (mode 3"). The instant in which current is reaches zero coincides with the beginning of new modes in sequence I. This new sequence opens the possibility to replace switch T, by a diode, thus reducing the total number of switches in the converter.

1003

(c) Mode 3"

Fig. 9. Initial modes for NS2

C. Comparison among the proposed topologies All auxiliary commutation circuits operate with

the usual sequence. ACCl and ACC3 are the simplest topologies for this type of operation. Nevertheless, they are more dependent on dc link current than topologies ACClD and ACCSD are. It should be noted that there is no sense in using the switch T, in circuit ACC3D because any con- duction of the accelerating device during the commutation interval of Ts will prevent this switch to be turned-off. This is the same case for circuits ACCSD and ACC9D. which are useless. Additionally. circuits ACC2(D). ACC4(D) or ACC6(D) are redundant for usual operation. in terms of number of components used.

Use of topologies ACC7 to ACCll practically eliminates the minimal conduction time for T,. However, circuits ACC7@), ACCS and ACC9 operate only at usual modes.

In reference to the new modes of operation. all topologies need to have two inductances to achieve operation with zero current switching. Never- theless, for ACC4(D), ACC 10(D) or ACC 1(D) with NS1. zero current commutation is obtained even though inductance Lo (or L,) is absent

Topologies ACC2 and ACC2D are able to operate in both sequences even with a diode replacing the switch Tr. ACC4 and ACC4D can only operate with NS1. ACC6 and ACC6D are able to operate with NS1, but in relation to NS2 they are dependent on input and output voltages. ACClO and ACCll can operate with NS1 and ACClO is dependent on input and output voltages to operate with NS2. ACCllD can only operate with NS1 and ACClOD can operate with both sequences. However, is dependent on input and output voltages to operate correctly with DS2.

All topologies mentioned above need at least one auxiliary switch for starting operation. In Ref. [ 5 ] a switch T, (Fig. loa) allows the converter to starr as a series resonant dc link converter 131. Fig. 10(b)

Ld Lo

Fig. 10. Starting circuits

presents an alternative solution to this problem. In this case. first charge of the capacitor C, at start, occurs through thyristor T, .

I . DESIGN PROCEDURE

The following operation aspects are important in

- Reduction of zero current interval, Atz, in- creases the maximal operating frequency;

- Reversal of the capacitor polarity imposes the minimal conduction time for T,;

- Total commutation time, t,. determines maxi- mum frequency of operation;

- Adequate choice of commutation capacitance. and inductance guarantees successful com- mutation for both switches T, and T,.

First aspect is reached with the use of the accelerating device as in topology ACC2D, for example. A minimal pulse width can be obtained with the use of topologies in whch a bridge reverses the capacitor polarity. Minimal commu- tation time and success of switch's turn-off depend on topology and commutating component's choice, respectfUlly. It should be noticed that the total commutation time is referred here as the sum of the individual commutation time of main and auxiliary switches. These parameters can be normalized as a function of x=I,&,. C,=V,tq/I,, L,=I,t,N, and To=CI,/VL VL is the value of capacitor voltage at start of commutation and t, is the device turn-off time. Their plot not only shows how an adequate choice of x avoids conflict between different values of these parameters but also gives information about the different configurations.

Normalized curbs in Fig. 11 represent the case in which V,=E and inductances are equal in value. Suppose that high frequency operation is desired.

design procedures and topology choice:

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Fig. 1 I(a) shows that the total commutation time is smaller with ACC5D (curb B) or ACC6D (curb C) than with other topologes, mainly for high values of x. The selection of x is a compromise between the values of capacitance, inductance, current peak in auxiliary devices and energy necessary for commutation. Higher values of x reduce the inductance values (Fig. llb), but in- creases the energy used (Fig. 1 la) and capacitance values (Fig. 1 lb). Moreover, the choice of the capacitance value in curb Fig. ll(b) must guarantee turn-off for both thyristor T, and T,. With ACClD or ACC6D, the capacitance value must be chosen from curb P in Fig. ll(b), once the commutation of the main switch needs a capacitance bigger than the one

ttmo, Wiwn A=ACCl to ACC6 B=ACClD,ACC2D C=ACCSD,ACC6D

C/Cn, LLa

1 2 3 4 5 6

PA=main and aux. switches for ACCl

P=main switch for ACClD and ACC6D A=aux. switch for ACClD and ACC6D

to ACC6

(b) Fig. 1 1. Normalized Parameters

needed by the auxiliary switch (curb A in Fig.

IV. INVERTER AND RECTIFIER CONTROL STRATEGY

Both rectifier and inverter units require P W M

control to produce sinusoidal voltage and current. Since the proposed converter has the ability of adjusting both pulse width and notch width, any technique of PWM control can be used. When the converter operates with usual modes, a larger notch width cannot be followed without increase in capacitor voltage of the auxiliary circuit or a dc link current boost effect if a short circuit path for the inductor current I, is provided through the inverter itself.

As discussed before, use of the adjustable notchmg techmque helps to solve this problem. However, four situations require a control decision, as examples show in Fig. 12 for ACC2D topology operating with NSl. For that topology, the ca- pacitor resonates during an interval of time Atc (modes 5 and 6 from Fig. 4). Therefore, when pulse notch width, At,,, is smaller than At, capacitor charge must conclude to satisfy the next commutation requirement. When Atc<Af<2.At,, control circuit can command a second capacitor resonance (Fig. 12c) or not (Fig. 12b). In these three cases, current i, looses synchronism with the P W M pattern. Finally. when At,,>2.AtC, inductor L, is short circuited during a period of time equal to Af-2.At,-Atc, (Fig. 12d).

V Ts

i S

Ts

i S

V

Atcl IC) (d)

Fig. 12. Situations for control decision 1 1 b).

In any case, regulation of current I, at dc link can be achieved through the rectifier. Voltages V,=+E and V,=-E and short circuit (V,=O) in Fig 13 represent the situations obtained by conveniently firing the rectifier bridge switches.

1005

Fig. 13. Possibilities of input control

V. SIMULATED RESULTS

Simulation was used to test the control strategies discussed above. Simulated waveforms for the converter employing the topology ACC2D (Fig. 6) with a simple scheme of variable pulse width and notch width are shown in Fig. 14. Current I, (Fig. 14a) was regulated through the rectifier with a sequence +E, -E, 0. +E. It can be observed from Fig. 14(b) that adjustable notch in dc link current is (Fig. 14c) can be obtained without any increase in

Id 7.57

2.G 2

0 ~ " ' I ' ~ " I " ' ' I " ~ ~ I " ~ ' ' 1 ' 1 7 ' ' ' f

0.025 0.05 0.075 0.1 0.0125 0.15 0.175 0.2 (a) Id regulation (A) t(s)

0.025 0.05 0.075 0.1 0.0125 0.15 0.2 (b) main switch voltage (V)

0.025 0.05 0.075 0.1 0.0125 0.15 0.175 0.2 (c\ dc link current ( A \ t o )

Fig 14 Simulation results for ACC2D nith NSl and C=O 5mF, LO=60pH. L,=60pH. Ld=40mH. V,,=190 3 V

voltage stress Finallj. dc link current is compared to a reference pattern to shou differences beh%een use of ACC2D and that of ACC2 It can be seen from Fig 15 that dc link current pulses obtained with ACC2D (Fig 15a) sjnchronizes better than

Ref.

0.01 0.0125 0.011 0.0115 0.012 t(s) (b)

Fig 15 Companson of dc link current synchromsm with (a) ACC2D and (b) ACC2

those ones obtained with ACC2D (Fig 15b)

VI. CONCLUSION

This paper examines twenty new topologies of notching current source aclac converters. Quasi- square current pulses may have variable width and are obtained with the help of a notching circuit in the dc link. Therefore, the front end rectifier and output inverter switches operate at zero current. Additionally, ten of the proposed topologies are able to operate with adjustable notches. In some of them, only two additional switches and two diodes are needed when compared with conventional GTO version of the rectifierhnverter system. Because of zero cur- rent switching, SCRs may be used for implementation. However. use of faster self- turned-off devices. as modified GTO or IGBT. allow higher frequency limit of operation for the inverter. A simplified circuit of one of the proposed scheme was simulated to demonstrate feasibility of the principle.

APPENDIX

Circuits ACC7(D) to ACClI(D) come from circuits ACCl(D) to ACC6(D) and, for that reason. nil1 not be mentioned in this Appendix Plots in

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Fig. 11 are based in the following relations.

A. Basic relations and expressions V d y

Id% T o = E , k = f i , (1)

- L,/L, in topologies ACC1, ACClD, ACC2, and

- L,/L, in topologies ACC2, ACC2D, ACC4 and

- L,/L, in topologies ACCS, ACCSD, ACC6 and

Also, to simplify the presentation of the normalized parameter equations, the following auxiliary expressions are used:

fix) = sin-'(:),

CId=yc, L N = T 1 Id

kl = E and k? = E where K are equal to

ACC2D,

ACC4D,

ACC6D.

g(x) = cos-'(; ,

h(x) = tg-'( J.2-1> -

The author would llke to thank the Brazilian National Research Council for h d m g ius research.

(2)

REFERENCES B. Commutation parameters for main and auxiliaiy switches [ l ] Murai Y. and Lipo, T.A. (1988). *'High

frequency series resonant dc link power - ACCl to ACC6 (main and auxiliary)

conversion", IEEE-IAS Annual Meeting Conference Record, pp. 772-779.

[2] Caldeira, P. (1 990). "High frequency series resonant dc link power conversion system", Ph.D. thesis, University of Wisconsin-

x L - w 1 c - c - - - - - - - C,v J'X2-1 ' L:v xib ' vC1dtq ' and (3 1 'r T o = $V(X) + Jxz-l + f ]

where x = kl = Id 1; E

with - L=L,,//L,, for main switch, and L=L, for

auxiliary switch in circuit ACCl and ACC2 - L=L,, for main and auxiliary switch in circuit

ACC3- L=L,+L,,. for main switch and L=L,, for auxiliary switch in circuit ACC4

- L=L,,, for main switch and L=L,+L,, for auxiliary switch in circuit ACCS and ACC6

Madison [3] G. Ledwich, E.R. da Silva, and T.A. L i p ,

"Soft switched notchmg current source inverters", IEEE-PESC92 Conference Record, 1992.

[4] E.R.C. da Silva, G. Ledwich. M. Aydemir, and T.A. Lipo, "DC link current notching inverter with soft commutation," in Conj Rec. 1992, 9th Brazilian Conf: on Aut. Contr., Bra=. Soc. on Aut. Contr., pp. 80-85.

[5] H. Nakamura. Y. Murai and T.A. Lipo. "Quasi current resonant dc link ac/ac converter," IEEE-PESC93 Conference Rec., 1993, pp. 279-284.

and

$= $ [ k S ( x ) + h , ( ~ ) + ? ]

- Circuit ACClD (auxiliary snitch)

c , 2g(r) L v zx iw i vcrdty - T(G)

[6] G Joos, G Moschopoulos. and P D Ziogas. "A high performance current source inverter," in Conf Rec 1991 Ann Meet IEEE Power Electrun Suc , pp 123-130

C - r I - CI' - 1 c - - - -

and (5)

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