REALIZATION OF COST-EFFECTIVE

MULTIPLIER FOR HIGH SPEED

DIGITAL SIGNAL PROCESSING

ARCHITECTURES

PRESENTED BY:

Veera Boopathy.E (M.E-VLSI DESIGN, VSBEC, Karur)

Bharath Kumar.M (Asst.Professor-ECE, VSBEC, Karur)

Saravanan.S (Asst.Professor-ECE, VSBEC, Karur)

ABSTRACT

Low-cost FIR designs using rounded truncated multipliers.

Bit width optimization and hardware resources are equally considered without sacrificing frequency response and output signal precision.

To minimize total area cost non-uniform coefficient quantization with proper filter order is proposed.

MCM in direct FIR structure is implemented using improved truncated multipliers.

Proposed designs achieve best area and power compared with previous FIR design approaches.

INTRODUCTION

FIR digital filter is vital component in DSP and communication systems.

Applied in portable applications with reduced area and power.

FIR filter of order M is

Two FIR structures are direct form and transposed form for a FIR filter.

PURPOSE OF WORK

In many multimedia and DSP applications multiplication operations have fixed-width property.

Thus required to truncate product bits to necessary precision to reduce area cost, leading to design of truncated multipliers.

A truncation algorithm is proposed for efficient hardware reduction.

The proposed algorithm considers following to minimize the overall error in the final result

elimination of unwanted LSBs of partial product

addition of correction bit at appropriate bit position

DIRECT FORM STRUCTURE

TRANSPOSED FORM STRUCTURE

Parallel multiplication of delayed signals with

respective filter coefficients then accumulation of entire

product terms.

Current input signal and coefficients are multiplied

then individuallygo through SA and delay

elements.

CLASSIFICATION OF FIR FILTER HARDWARE IMPLEMENTATION

DIGITAL FIR FILTER HARDWARE

IMPLEMENTATION

MULTIPLIER LESS BASED

MEMORY BASED

LOOK-UP-TABLE

(LUT)

DISTRIBUTED ARITHMETIC

(DA)

MULTIPLIER-LESS BASED

MEMORY BASED

LUT BASED DA BASED

Realize MCM with shift and add

operations and then use CSD and CSE to minimize adder

cost of MCM

LUT-based design stores odd multiples of input signal in ROMs to

realize constant multiplications in

MCM.

DA-based design recursively

accumulate bit-level partial results for inner product

computation.

STAGES IN DIGITAL FIR FILTER DESIGN AND IMPLEMENTATION

FREQUENCY RESPONSE SPECIFICATION

FINDING FILTER ORDER AND COEFFICIENTS

COEFFICIENT QUANTIZATION

HARDWARE OPTIMIZATION

PROPOSED DESIGN

• Low-cost FIR filters based on direct structure with faithfully rounded truncated multipliers is proposed.

• MCMA module is realized by accumulating all PPs where unnecessary PPBs are removed without affecting final precision of output.

• Bit widths of all filter coefficients are minimized using non-uniform quantization to reduce hardware cost still satisfying specification of frequency response.

TRUNCATED MULTIPLIER DESIGNS EARLIER VERSION

TRUNCATED MULTIPLIER DESIGNS IMPROVED VERSION

MCMAT PROCEDURE IN EARLIER VERSION

MCMAT PROCEDURE IN IMPROVED VERSION

EARLIER TRUNCATED MULTIPLIER ALGORITHMIC PROCEDURE

PROPOSED TRUNCATED MULTIPLIER ALGORITHMIC PROCEDURE

MULTIPLICATION / ACCUMULATION USING

INDIVIDUAL PP COMPRESSION

MULTIPLICATION / ACCUMULATION USING

COMBINED PP COMPRESSION

OVERALL FIR FILTER ARCHITECTURE USING MCMAT

RESULTS AND COMPARISONS

CONCLUSION

MCMAT direct FIR structure leads to minimum area, cost and power utilization even if several earlier designs are build on transposed form.

Reduced area, power and cost FIR filter designs is achieved with respect to coefficient bit width optimization and hardware sources realization.

Thank You