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iC-NGAPPLICATION NOTES
May 04 1999, Page 1/14
iC-Haus GmbH Tel +49-6135-9292-0Integrated Circuits Fax +49-6135-9292-192Am Kuemmerling 18, 55294 Bodenheim http://www.ichaus.com
Fig. 1: basic circuit with low-pass filters for complementaryinput signals.
Fig. 2: circuit as an 8-bit sine/digital converter.
APPLICATION CIRCUITS
Basic circuit (incremental mode)
Basic circuit (parallel-absolute mode)
iC-NG can be directly connected as an 8-bit sine/digi-tal converter, where the data output in parallel-abso-lute mode is controlled by the iC’s own interrupt signal.
To this end, signal output MFP must be connected toread signal NRD; parallel operation is set by SCL= 0and SDA= 0 (or configured via EEPROM). Outputvalue register NG(7:0) is addressed after the devicehas been switched on by presetting the address to "0";
a negative edge for read signal NRD accepts thecontents of register NG for output to data lines D7..0.Since the signal enables for NGUPDT and MAXFREQare also issued as presettings, any signal changeautomatically appears on the data lines.
iC-NGAPPLICATION NOTES
May 04 1999, Page 2/14
22
VREF15 iC-NGSensor case
1Vss to120 SIN24
NSIN23
PSIN+
-RS08120
1kRS03
- PSIN
1kRS04
2kRS01
2kRS02
SIN
NSIN+
Fig. 3: input circuit for voltage signals with 1Vss.
SIN24
NSIN23
PSIN22
VREF15 iC-NGSensor
11µAsscurrent output
Ground
+
-
CS0127pF
RS030
PSIN
RS040
RS01182k
RS02182k
SIN
NSIN
CS0227pF
+
-
Fig. 4: input circuit for current signals with 11µAss.
SIN24
NSIN23
PSIN22
VREF15 iC-NG
+
-
RS0110k
RS02 10k
SIN
NSIN 5kRS03
1VssV-GEN
RS065kGND
Fig. 5: input circuit for non-symmetrical voltagesignals.
Fig. 6: circuit with external offset compensation.
Possible input circuits
Input circuit with offset compensation
With iC-NG, the offset parameters are evaluated withthe amplitude of the input signal not used in the seg-ment in order to keep the intersections of the segmentjunctions stable. This concept is required to correct thesignals of phase-shifted and distorted sine/cosinesignals.
External offset compensation may be necessary forsensor applications with varying signal amplitudes; thelinearity of the converter suffers if the signal amplitudechanges once the compensation parameters havebeen set.
iC-NGAPPLICATION NOTES
May 04 1999, Page 3/14
+5V
VREF
A3
E1
E2
E3
GND
INV
NERTNER
TRI
VBVCC
A1
A2
AX
BX
ZX
NER
+
+
ZERO
NSIN
NWR
NZERO
PCOS
PSIN
PZERO
RCLKSCL SDA
SIN
24C02
D3
D4
D5
D6
D7
GND
MFP
NCOS
NER
NRD
NRES
COS
D0
D1
D2
VB VBR
VCC
VCCA
VHVHL
NER
+5Vanalog
Reset
+5Vdig
SIN+
SIN-
COS+
GND
OUT_AX
OUT_BX
OUT_ZX
ERROR
Reset
+10..30V
COS-
+5Vanalog
+5Vdig
R1527k
C1100pF
47pFC2
100pFC5
C447pF
100pFC6 C3
100pF
C121µF
4.7µFC13
iC-WE SO20W
ERROR
LOW VOLTAGE
MODE
CHAN1
CHAN2
CHAN3
T. SHUTDOWN
LVH
220µH4.7µFCVH
RVB
1
100nFC9
C114.7µF
5kR8
OP2
R4220k
R145k
R610k
10kR3
R1210k
C71µF
1kR16
C101µF
REGULATORVCCA
REGULATORVCC
REFERENCE
THERMALSHUTDOWN
TEMPERATURE
OSCILLATOR
VH SWITCHINGREGULATOR
VREFiC-WD
ERROR DETECTION
D1
5kR13
SIN
COS
ZERO
iC-NGR115k
R7220k220k
R10
R110k
220kR2
10kR5
10kR9
OP1
1µFC8
GND
VDD
EEPROM
-
-
A Bridge
B Bridge
+5Vdig
Fig. 7: MR sensor circuit with a line driver and 10%30V voltage supply.
Application circuitry for an MR sensor system
iC-NGAPPLICATION NOTES
May 04 1999, Page 4/14
VREF
SUB-D 9pole
Application field for input configuration
components not assembled
7
8
5 01
4
6
5
7
6
2
1
4
5
3 ISO_RxD
ISO_TxD
NINT0NINT1
NPSEN
NRDNWR
P1(7:0)
P2(7:0)
RES
RxD
T0T1
TxD
VCC
VCC_OUT
5V
A(7:0)
AD(7:0)
ALE
CLKGND
ISO_GND
2
0
1
3
7
A012 A1
A23GND4
SCL 6
SDA 5VDD8
GND2
IN1 OUT3
24 3
VDD
14
15
ZERO18
26NRES
NSIN23
NWR 4
NZERO17
PCOS19
PSIN22
PZERO16
RCLK13
SCL
28
SDA
27
SIN24
D3 8
D4 9
D5 10
D6 11
D7 12
GND
25
MFP 2
NCOS20
1NER
NRD 3
COS21
D0 5
D1 6
D2 7
MFPNER
NRDNWR
6
MFP
R0011k1k
R0021k
R008
AXOB ROT
Z4 B4
A4
ZX BX
AX
1kR013
D0
D1
D2
D3
D4
D5
D6
R0144.75k
CZ06 RZ06
RC07
CC07
CC01 RC01
RS06
CZ07
CZ01 RZ01
RCLK
CS04
RS04
CS02 RS02
CS05 RS05
CS06
1kR011
LATCHADDR.
80C51RS232isol.
5V Regulator
JSupply
J4
GND2
RC03
R0051k
10uFE003
SSCL
SSDANER.
MFP.
R0121k
GND
VDD
GND1
J030
E00110uF
RESET
10uFE002
NRESPSIN
CZ05
R0101k
NSINCS01
CC06
RZ07
RZ04RZ08
RZ02
CZ04
RZ05
E004100nF
PCOS
NCOS
PZERO
RC02
CC04
CC05 RC05
SIN
COS
CC03
RS03
RZ03
CZ03
NZERO
ZERO
1kR006 R004
1k
NER
NRD
R0091k 1k
R003
78xx7805X003
D7
1kR007
100nFC001
X00224C02
Ser. EEPROM
NWR
SCL
RS08
SDA
iC-NG
ZERO
COS
SIN
X001
R015100k
RS07
CS07
RS01
J029
RC06 CC02
CZ02
CS03
VREF
RC04RC08
J3
Fig. 8: demo board circuit diagram.
DEMO BOARD
An iC-NG demo board with an 8OC51 controller andinsulated serial interface is available for test purposes.The package includes a partially-equipped circuitboard, a 3.5" floppy disk with PC software (system re-quirements: processors from 80386, DOS 6.x, OS/2,
Windows 3.11, Windows NT 3.51, Windows 95 andupwards), a lead for the serial interface and operatinginstructions.
iC-NGAPPLICATION NOTES
May 04 1999, Page 5/14
serialVoltage supply
free area forclock divider free
Controller
Indicators (free)
5V Regulator (free)
plug-in field for input circuitry
reset iC-NG
clock frequ.
µC reset
Power-on LED
free forEEPROM
interface
Fig. 9: iC-NG demo board, component side.
iC-NG Winkeldekodierer Sinus/Digital V1.8 NG:00 00 00 3E TPOS:00 00 00 00 AX:0 A4:I NGUPDT :O,I RES :256 ROT :O SIC :O CSIN :12.0pF BX:0 B4:I POSKOMP:O,O HYS :R100% ADAP :O SLCNTEN :O CZERO:12.0pF ZX:0 Z4:I MAXFREQ:O,I ZCONF :O NGLJ :O COUNTEN :O FREQ :O AB:0 RO:I STEPINP:O,O OUTSEL:O LATINT:O CBZ :O TACHO:D7 ERRV :O,O ACCMOD:O LATERR:O CLC :O G O Funktionsanpassung(FA) SEG1 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG2 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG3 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG4 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG5 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG6 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG7 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEG8 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 3E 00 00 00 FA D7 C0 1F 30 00 00 05 FF F8 F8 F8 10 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 20 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 30 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 40 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 60 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 70 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F1 HELP F2 SAVE F3 LOAD F4 READ F5 OREAD F6 ADR F7 PULS F8 FIT F10 QUIT
On-screen mask
Demo Board PCB
Demo board control programThe user interface depicts the iC’s internal registers.By selecting the letters printed in bold in the inputmask, individual registers can be directly accessedand altered. Data transfer to the demo board and toiC-NG runs in the background.Complete sets of data can be stored on floppy or harddisk and can be used to transfer information to
EEPROM programming units, for example. Variousspecial functions are also available; among otherthings, these permit the cyclic readout and on-screendisplay of certain iC-NG registers, the continuousmeasurement of pulses or segments, or the approxi-mate, automatic determination of parameters whichadapt the converter for distorted signals.
iC-NGAPPLICATION NOTES
May 04 1999, Page 6/14
GENERAL
Generating trigger signalsOption 1 (incremental mode)
Through external wiring, a zero signal can be preset(static) and the display at pin ZX/D2 influenced usingrelevant programming. To this end, the zero signalinput is configured so that iC-NG contains "ZERO = 1".This is made possible by pin NZERO being connectedto GND and by pin PZERO being connected to ahigher potential, such as +5V, for example. OutputZERO remains open.For each sine cycle, iC-NG now generates a zeropulse at ZX/D2 which can be used to trigger theoscilloscope. The position of the zero pulse can beprogrammed via ZCONF (address 9) and shifted insteps of 45°.
Generating trigger signalsOption 2 (parallel-absolute mode)
A trigger signal at pin MFP can be generated for anydesired stage of interpolation by comparing the targetmarker of register TPOS with the NG output value.
To do so, the 32-bit output value and target positioncomparison are limited to the 8 bits of the interpolationsteps (counter depth OUTSEL(1:0)= 00, address 9).The desired target position and trigger point are writtenunder address 0 (TPOS 7:0, zero after a reset).Position comparison POSCOMP must be enabled(EN1= 1, address 11); the change in output value viaNGUPDT the pin MFP would otherwise signal must bedisabled (EN0= 0, address 11). Following this, pinMFP now issues a trigger signal each time the targetposition is reached.
Basic correlation between the resolution, input andoutput and necessary clock frequencies
The minimum clock frequency required is determinedby the 2-fold input frequency multiplied by the internalresolution of the converter (high accuracy error).
We recommend that the clock frequency be set so thatthis is equivalent to the 8-fold value of the input fre-quency multiplied by the internal resolution of theconverter, which of course depends on how high thepermissible maximum error of rotation may be.
The maximum output frequency in parallel-absolutemode at port D0 and in incremental mode at port
D7/AXB is equivalent to half the clock frequency.
Attention must be paid to the fact that higher reso-lutions are used in special cases where RES(6:5) isnot equal to "00".
Example 1: resolution of 200, 500Hz input signalfclk = 500Hz x 8 x 200 = ca. 800kHz. Taking thediagram for the oscillator frequency characteristic,R(RCLK) has ca. 47kS.
At 500Hz input frequency, the pulse frequencies forAX and BX are 25kHz and 50kHz for AXB.
This high clock frequency means that up to 100kHzpulse frequency are possible for AX and BX and200kHz for AXB. Calculating backwards, the highestpossible input frequency is thus 2kHz. If this frequencyis exceeded, this is signalled at error message outputNER (which must be enabled).
Example 2: resolution of 8, 100kHz input signalfclk = 100kHz x 8 x 8 = ca. 6.4MHz. Taking thediagram for the oscillator frequency characteristic,R(RCLK) has ca. 5kS, if 5MHz clock frequency areselected.
Output frequencies of up to 1.25MHz are possible forAX and BX. In this instance, the highest input fre-quency possible without an error message beinggenerated is ca. 300kHz.
NotesClock frequencies which exceed 800kHz significantlyincrease the level of system noise (jitter). The(resistive) hysteresis appears to be reduced, pulsepositions are shifted and come temporally slightlyearlier. Capacitive hysteresis also reacts sensitively tosystem noise.
Despite this, the system still functions if very high clockfrequencies of 3MHz, for example, are selected. AXBpulse frequencies of up to 800kHz are possible.
Higher signal amplitudes improve the output signal;3Vss are recommended. Looping in the programmablegain amplifier (PGA) can influence the quality of thesignal (address 8, ADAP= 1). If the converter adapt-ation function is used, the clock frequency should notbe changed once the adaptation parameters havebeen set.
iC-NGAPPLICATION NOTES
May 04 1999, Page 7/14
Table for operating frequencies
Clock frequency fclk 800 kHz 1.6 MHz 3.2 MHz
Resistor R(RCLK) for clock oscillator ca. 47 kS ca. 27 kS ca. 9 kS
Max. output frequency (an output change requires 2 clock pulses) 400 kHz 800 kHz 1.6 MHz
Max. AXB pulse frequencyMax. AX resp. BX pulse frequency
200 kHz100 kHz
400 kHz200 kHz
800 kHz400 kHz
RES 200
Max. input frequency 2 kHz 4 kHz 8 kHz
Recommendations (4-fold over-sampling at fmax)
max. input frequency resulting AXB pulse frequency (AXB shows 100 pulses)resulting AX resp. BX pulse frequency
< 500 Hz< 50 kHz< 25 kHz
< 1 kHz< 100 kHz< 50 kHz
< 2 kHz< 200 kHz< 100 kHz
Example: possible moving speed with a scale where the length of acycle is 500 µm at a resolution of 2.5 µm
0.25 m/s< 1 m/s
0.5 m/s< 2 m/s
1 m/s< 4 m/s
RES 8
Max. input frequency 50 kHz 100 kHz 200 kHz
Recommendations (4-fold over-sampling at fmax)
max. input frequency < 12.5 kHz < 25 kHz < 50 kHz
Period counter, parallel or SSI output mode(2 clock pulses per change required)
Max. input frequency 200 kHz 400 kHz 800 kHz
Example:possible moving speed with a scale where the length of acycle is 500 µm (resolution of 500 µm, resolution of 2.5µm is valid with low speed only)
< 100 m/s < 200 m/s < 400 m/s
iC-NGAPPLICATION NOTES
May 04 1999, Page 8/14
OFFS = (-0.33 .. 0.33) × COS
GAIN = 0.5 .. 2
45E
0EVREF
1
OFFS
e2 × Ftan(n)
PGA Komparator
+
-
FA
A × COS(n)
1. Segment
A × SIN(n)
e2
e1 G × e1
Fig. 10: schematic circuit diagram of the converteranalog section.
1. 2. 3. 4. 5. 6. 7. 8. Segment
SIN
VREF
0E 45E 90E 135E 180E 225E 270E 315E 360E
+SIN +COS -COS +SIN -SIN -COS +COS -SIN
COS
G1 G3 G5 G7 G8G6G4G2
O1 O3 O5 O7 O8O6O4O2
Fig. 11: effects of parameters OFFSET and GAIN.
CORRECTING SIGNALS AND ADAPTING FUNCTIONS
Compensation possibilities1. Different signal amplitudes for sine and cosineThe PGA permits various signal amplitudes to becompensated for. It is, however, prudent to compen-sate externally if it is not permissible to enlarge thedynamic error (settling times when changing segment).
2. Varying signal amplitudesVarying signal amplitudes are automatically compen-sated for when the tangent is formed.
3. Signal-independent offset voltagesExternal compensation is essential. The iC-NG offsetcorrection facility is only suitable for signals whosevoltage at a zero crossing changes with the amplitude,as it is the case with phase-shifted signals.
4. Signal-dependent offset voltagesThe programmable, amplitude-weighted zero crossingcorrection feature means amplitude-dependent offsetvoltages can be compensated for.
5. Phase errorsPhase errors, e.g. through inexact sensor placement,can be eliminated by the programmable compensationfacility.
6. Signal distortion caused by harmonicsThe iC-NG converter can also resolve distorted inputsignals without detriment to the converter’s linearity viathe programmable TAN-function adaptation feature. Ifthe form of the signal is known, it is possible to predictthe adaptation parameters, taking Fourier coefficientsas a basis for calculation, for example.
Setting correction and adaptation parameters
Step 1: correcting the gain of the PGA and the offset.
Using gain setting G1, the signal at the end of the firstsegment is adapted to the cosine signal (sin45°=cos45°). Offset O1 is then set to G1 x e1 = sin(0°).
A decisive factor for the sine-cosine intersections isthe gain adaptation performed for the 1st + 2nd
segments, 3rd + 4th segments, etc. Offset settings aloneonly affect intersections with the VREF referencevoltage.
The following order of compensation is practical:First gain, then offset.
Step 2: setting the transfer function of the TAN-D/Aconverter to the value of e1/e2 (e= input signal).
iC-NGAPPLICATION NOTES
May 04 1999, Page 9/14
0E 5E 10E 15E 20E 25E 30E 35E 40E 45E
Ftan(n)= tan(n)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
FA15[1]= 0
FA15[1]= 3FA15D[1]= 0
adaptedconverter function:
Ftan(n) = n / (90° - n)
Fig. 12: effect of parameters FA. Example fortriangular input signals (1st segment).
CH1
CH4
CH3
CH2
CH1..3 0.5V/DIV
TIME 1ms/DIV
CH1..4 0V
CH4 2V/DIV
Resolution RES= 8
1.) Offset 8.Segm.2.) Gain 1.Segm.
3.) Offset 2.Segm.4.) Gain 3.Segm.
5.) Offset 4.Segm.
CH1: Pin24, SIN
CH3: Pin 15, VREFCH2: Pin 21, COS
iC-NG
CH4: Pin 12, D7/AXB
8.) Gain 7.Segm.7.) Offset 6.Segm.
6.) Gain 5.Segm.
Fig. 13: the 8 steps of compensation in clockwiseoperation.
CH1..3 0.5V/DIV
TIME 1ms/DIV
CH1..4 0V
CH4 2V/DIV
Resolution RES= 8
CH1: Pin24, SIN
CH3: Pin 15, VREFCH2: Pin 21, COS
iC-NG
CH4: Pin 12, D7/AXB
CH1
CH4
CH3
CH2
S1
S2
S3
S4
S5
S6
S7
S8
Fig. 14: output signal following compensation(clockwise). S1..8 index the compensated seg-ments.
CH1..3 0.5V/DIV
TIME 1ms/DIV
CH1..4 0V
CH4 2V/DIV
Resolution RES= 8
1.) Offset 1.Segm.8.) Gain 8.Segm.
7.) Offset 7.Segm.6.) Gain 6.Segm.
5.) Offset 5.Segm.
CH1: Pin24, SIN
CH3: Pin 15, VREFCH2: Pin 21, COS
iC-NG
CH4: Pin 12, D7/AXB
2.) Gain 2.Segm.3.) Offset 3.Segm.
4.) Gain 4.Segm.
CH1
CH4
CH3
CH2
Bild nach erfolgtem Abgleich im Rechtslauf
Fig. 15: the 8 steps of compensation in counter-clockwise operation. The output signal shown herehas been compensated in clockwise operationalready.
In its basic setting (e1 = sin, e2 = cos), the PGA has again of one and an offset of zero. The tangent functionis formed in the feedback loop. For non-sinusoidalsignals, the transfer function can either be moresharply curved or straightened in the feedback loop(Fig. 12).
Adaptation of functions should be carried out for eachof the eight segments separately.
Example: manual adaptation procedure
The following diagrams show the first step ofadaptation in a correction process for adapting theconverter, here for distorted input signals with anadditional phase error.
The diagrams show the AXB output pulse train inincremental mode at a resolution of RES= 8, fromwhich point compensation should be started. Thevarious stages of resolution are represented by theeight edges of the 4 pulses; each edge can beindividually positioned by correcting the offset andgain.Emulating incremental mode in parallel-absolute modeby performing a cyclic readout of address 4 (outputD7/AXB) is favorable to iterative compensation.
iC-NGAPPLICATION NOTES
May 04 1999, Page 10/14
S8
S7
S6
S5
S4
S3
S2
S1
CH1..3 0.5V/DIV
TIME 1ms/DIV
CH1..4 0V
CH4 2V/DIV
Resolution RES= 8
CH1: Pin24, SIN
CH3: Pin 15, VREFCH2: Pin 21, COS
iC-NG
CH4: Pin 12, D7/AXB
CH1
CH4
CH3
CH2
Fig. 16: output following compensation (counter-clockwise).
SIN()' As @ Fsin(n % nserr) % Os
COS()' Ac @ Fcos(n % ncerr) % Oc
COS(n'0) @ O1' G1 @ SIN(n'0)
O1' G1 @ SIN(n'0)COS(n'0)
'G1@(As@0 % Os)
Ac@1 % Oc'
G1@OsAc % Oc
G1 @ SIN(n'45E)' COS(n'45E)
G1' COS(n'45E)SIN(n'45E)
.
Ac
2% Oc
As
2% Os
'Ac % 2@Oc
As % 2@Os. Ac
As
Fine tuning at higher resolutions can be performedonce the clockwise and counterclockwise steps ofcompensation have been completed. In doing so, it isimportant that the input frequency is low to avoid falsesettings being made due to dynamic errors.
Incorrectly positioned segment junctions can beadjusted clockwise by offset 1, 3, 5, 7 and by gain 2, 4,6, 8. The sequence is discretionary.
If the input signal requires, the transfer function of theTAN-D/A converter can be adapted by way of detuningin the second step of adaptation. The signal formsgiven in this example would also require that thissecond stage of adaptation be carried out.
Example: calculating adaptation parameters offsetand gain using approximation formulae.
In the following example, we assume that the ampli-tude and offset values for the sine and cosine inputsignals are known and that the phase shift is free fromerror.
Formulation:
SIN() Sine input signal at angle nAs Sine amplitudeFsin Sine-similar functionOs Sine offsetnserr Sine phase errorCOS() Cosine input signal at angle nAc Cosine amplitudeFcos Cosine-similar functionOc Cosine offsetncerr Cosine phase error
Simplifications:nserr= nserr= 0, Fsin()= sin(), Fcos()= cos()
Formulation for the offset of segment 1:
Formulation for the gain of segment 1:
The resulting approximation formulae for the individualsegments are collated on the following page.
iC-NGAPPLICATION NOTES
May 04 1999, Page 11/14
Ac % 2@Oc
As % 2@Os&384 @ G1 @ Os
Ac % Oc
As % 2@Os
Ac % 2@Oc'
1G1
&384 @ G2 @ OcAs % Os
As % 2@Os
Ac & 2@Oc384 @ G3 @ Oc
As % Os
Ac & 2@Oc
As % 2@Os'
1G3
&384 @ G4 @ OsAc & Oc
Ac & 2@Oc
As & 2@Os384 @ G5 @ Os
Ac & Oc
As & 2@Os
Ac & 2@Oc'
1G5
384 @ G6 @ OcAs & Os
As & 2@Os
Ac % 2@Oc&384 @ G7 @ Oc
As & Os
Ac % 2@Oc
As & 2@Os'
1G7
384 @ G8 @ OsAc % Oc
Segment Gain Offset
1
2
3
4
5
6
7
8
The following values must be programmed into the adaptation registers:
Gain = 255 - G * 128 , when G > 1Gain = G * 255 , when G <= 1
Offset = 255 - O , when O >= 0Offset = 127 + O , when O < 0
iC-NGAPPLICATION NOTES
May 04 1999, Page 12/14
1 2 3 4 5 6 7 8
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Eingangssignale
45° 90° 135° 180° 225° 270° 315° 360°1 2 3 4 5 6 7 8
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Interne Signale (gleichgerichtet)
45° 90° 135° 180° 225° 270° 315° 360°-1 -0.5 0 0.5 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Eingangssignale (Lissajous-Figur)
G = [1.0000 1.0000 1.0000 1.0000 1.0000 1.0000 1.0000 1.0000]O = [0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000]FA()= 0
n
Acqcos(n)
Ideal sine/cosine input signals
e1
e2
Fig. 17: ideal sine/cosine input signals (Fsin= sin, Fcos= cos, As= Ac, Os= Oc= 0, nserr= ncerr= 0)It is not necessary to alter the GAIN, OFFSET and FA parameters.
G = [0.8182 1.2222 1.2222 0.8182 0.8182 1.2222 1.2222 0.8182]O = [0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000]FA() = tbd.
As= 1.1, Ac= 0.9
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Fig. 18: input signals with amplitude errors. The FA parameters should also be adapted, especially whenresolutions of higher than RES= 8 are used.
Examples: adapting the converter to real sensor signals
The adaptation of the gain necessary at the junction from 1st to 2nd segment, from 3rd to 4th segment, etc. leadsto alterations in the pulse width of the interpolation steps (see signal AXB) which follow a changeover ofsegment, especially at higher input frequencies. This dynamic error is caused by settling times and becomesmore noticeable the larger the differences in gain are. Vice versa, it follows that good sine/cosine sensor signalsalso generate considerably better incremental converter output signals.
iC-NGAPPLICATION NOTES
May 04 1999, Page 13/14
G = [0.7522 1.3294 1.0000 1.0000 1.3294 0.7522 1.0000 1.0000]O = [0.0836 -0.1209 0.0909 0.0909 -0.1209 0.0836 -0.1111 -0.1111]FA()= tbd.
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Os= +0.1, Oc= -0.1
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Fig. 19: input signals with offset errors.
G = [1.0000 1.0000 1.0000 1.0000 1.0000 1.0000 1.0000 1.0000]O = [0.2505 0.2505 -0.2505 -0.2505 0.2505 0.2505 -0.2505 -0.2505]FA()= tbd.
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n serr= +15°, n cerr= -15°
Fig. 20: input signals with phase errors.
iC-NGAPPLICATION NOTES
May 04 1999, Page 14/14
Fsin()= 1*sin(n) + 0.2*sin(2*n ) + 0.03*sin(3*n ) + 0.015*cos(n ) + 0.01*cos(2*n ) + 0.02*cos(3*n)Fcos()= 1*cos(n) + 0.2*cos(2*n ) + 0.03*cos(3*n ) + 0.015*sin(n) + 0.01*sin(2*n ) + 0.02*sin(3*n)
G = [0.5751 1.7388 1.0135 0.9867 1.7757 0.5632 1.0076 0.9924]O = [0.0270 -0.0453 0.0264 -0.0252 0.0453 -0.0259 0.0463 -0.0465]FA()= tbd.
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Signals with superimposed harmonics
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Fig. 21: input signals with superimposed harmonics.
An algorithm for predicting adaptation parameters can be provided on request. Methods of calculation can alsobe used to check if the setup ranges of the adaptation parameters are sufficient for a given sensor signal. If noformula is available for the sensor signals, sampled oscilloscope signals can also be taken as a basis forcalculation.