IC Immunity Modelingic-emc.org/download/EMCCompo 2011-Tutorial.pdf11 IC Immunity Modeling November...
Transcript of IC Immunity Modelingic-emc.org/download/EMCCompo 2011-Tutorial.pdf11 IC Immunity Modeling November...
11
IC Immunity Modeling
November 6th, 2011
Alexandre [email protected]
Etienne [email protected]
Alexandre [email protected]
Etienne [email protected]
2
Objectives of the tutorial
• Presenting the basic concepts of conducted susceptibility modeling and simulation at IC level.
• Illustrated by real case studies and a freeware for simulation (IC-EMC).
• Non exhaustive presentation of modeling methods dedicated to IC susceptibility.
3
IC-EMC
– IC-EMC is a friendly and free PC tool for modeling and simulating EMC at IC level.
– The tool is linked with the shareware WinSPICE derived from SPICE Berkeley for analog simulation (www.winspice.com)
– Download IC-EMC and the user manual http://www.ic-emc.org
– Version used for the tutorial: IC-EMC v 2.5
4
http://www.ic-emc.org
• Download the package icemc.zip
• Unzip in “C:/TEMP”• Open “/system”,
double click “ic-emc.exe” to launch IC-EMC
IC-EMC
5
Symbol palette
Schematic capture interface
IC-EMC simulation tools
Simulation command
IC-EMC main screen
IC-EMC
IC-EMC
Tools for susceptibility simulation
S parameter simulation
Zin simulation
Susceptibility
simulation
77
Summary
Context
Structure of IC immunity model
Propagation of conducted disturbances
Modeling of internal behavior
Practical trainings
Context
9
Immunity to Radio Frequency Interferences
Equipments PCBIntegrated
circuits
Electromagnetic Emission
CablesExternal disturbances
Cables Equipments
System disturbances
System
Failures
Internal activity
EMC of ICs
Integrated circuitsPCB
ICs are at the origin of EMC issues of electronic systems
EMC requirements at IC level (qualification, design rules, modeling)
10
Noise margin
Power supply voltage fluctuation
Vdd
Models for EMC of ICs
Models for IC designers
Prediction of EMI induced voltage fluctuation level and associated
functional failures, check EMC compliance of ICs.
IC design verification and improvement.
Integration of EMC models and dedicated tools in simulation flows
11
Models for EMC of ICs
Models for system designers
Prediction of susceptibility level of an electronic equipments, which
can embed several ICs.
Use of non confidential IC models (“black box approaches”).
Equipment design verification and improvement ICs are at the origin
of EMC issues of electronic systems
12
System
Cables
Equipment
Printed circuit board
Integrated circuit
Circuit modelCircuit model
PCB model
Equipment model
Models for system designers
Models for EMC of ICs
Hierarchical model
IC models are used as sub blocks of higher level system models.
Structure of IC Immunity Model
1414
Disturbed
block(s)
(Behavior?)
Source of EM
disturbances
(Conducted, radiated, harmonic, pulse…)
IC coupling
path
(Package,
I/O, PDN…)
External
coupling
path
(Cables,
PCB…)
Susceptibility
criterion
(Voltage margin,
SNR, Jitter, bit
error, offset…)
Modeling of IC immunity
Position of the problem
Integrated circuit
EMI Failure
IC Model
15
Die model• Disturbed block behavior• Internal decoupling• Power distribution
network(PDN)• I/O, ESD protection structure…
Die
Package
IC
Package model• Parasitic RLC• Package – Die resonances
Modeling of IC immunity
IC immunity model structure
IC immunity model can be linked with its physical structure.
16
Victim circuit
Electronic equipment
Cables
PCB
Radiated disturbances
Induced conducted disturbances
Vs
Zs
Zc, Td ZL
Equivalent Thevenin generator of RF disturbances
Cables, PCB lines
Input impedance of victim circuit
Modeling of IC immunity
Conducted immunity
Equivalent model
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Integrated circuit
Bias tee
DC supply or low frequency signal generator
RF generator
Power Amplifier
Directional coupler
Power meter
Conducted disturbance
DUT failure monitor
Forward and reflected power
Bus
IEC 62132-4: Direct Power Injection
Modeling of IC immunity
Conducted immunity
Frequency
Forward power
Conducted susceptibility threshold
Max. power = 20 – 30 dBm
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Susceptibility test bench
Conducted EMI
IC pins
Integrated circuit
Internal BehaviourInternal
Behaviour
Internal noise source
Internal noise source
Failure ?
Printed circuit board
Filtering / decoupling
Building blocks of IC immunity model
Modeling of IC immunity
Propagation of conducted disturbances
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Position of the problem
…… …
…
Chip (silicium)
VDD
VSS
Pad
rin
g
Power grid
Package
On-chip voltage fluctuationExternal
disturbance
RF disturbance
VEXTVINT
Filtering effect of IC PDN ?
21
Coupling of an external disturbance
Power Distribution Network
V1V2
I2 I1
External disturbance
Circuit
Sensitive
functionVss ext
VDD ext
Vss int
VDD int
Port 1Port 2 [ ]
=
2221
1211
ZZ
ZZZ
V1 : voltage fluctuations induced across the IC sensitive function
I2 : external disturbance coupled on a pin
Theoretical analysis
Hypothesis:
The PDN is purely passive (small signal assumption)
The PDN can be modeled by a quadripole (e.g. [Z] matrix)
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Coupling of an external disturbance
012
112
=
=i
i
vZ
22
12
012
1
Z
Z
v
v
i
=⇒=
Theoretical analysis
012
222
=
=i
i
vZand
The ratio V1/V2 expresses the external noise coupling across the
sensitive function.
Depending on the impedance profile of the PDN, the internal and
external voltage fluctuations can be different.
23
Coupling of an external disturbance
22
12
01
1 .2
ZZ
Z
v
v
Ciforw +=
=( )2
22
212
01
1 .4
ZZ
ZZ
p
v
C
C
iforw +=
=
( ) ( ) ( )WVZZ
ZZfH
C
CEMI /
.42
22
212
+=
Theoretical analysis Conducted immunity levels are usually expressed in terms of
power level of forward disturbance (Zc = the characteristic impedance of
the RF injection system).
The conducted interference coupling transfer function is given by the ratio between V1 and Pforw.
Quantify the efficiency of the EMI coupling on a node vs. frequency
Correlation with the impedance profile of the IC PDN.
24
Case study 1 – Filtering of EMI by IC PDN
• Characterization of the on-chip voltage fluctuation across the power supply of a digital core in CMOS 0.25 µm during a DPI test, over the range [1 – 1000 MHz].
• Set-up description:
[Ben Dhia11]
Case study 1 description
25
Asynchronous (or random) sub sampling acquisition mode Low intrusive (Zin > 500 Ω pour f < 2 GHz) Input range = [0 V; 3.75 V]
Isolation from external disturbances and circuit under test noise
[Deobarro09]
On-chip sensor description
Case study 1 – Filtering of EMI by IC PDN
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Bin width W N
Meas. Range W meas
2
minminmax
=⇒==R
Wn
R
WnN measmeas
On-chip sensor description
Case study 1 – Filtering of EMI by IC PDN
Acquisition principle:
Extraction of the statistical
distribution and statistical
properties (std deviation, peak-
to-peak ampl.)
Evaluation of the distortion
degree for harmonic
disturbance.
Basic rules for the acquisition:
Number of samples n and the number of bins N of the distribution ?
If R is the voltage resolution of the sensor:
27
[Deobarro09]
On-chip sensor characterization
Case study 1 – Filtering of EMI by IC PDN
3 dB - Bandwidth = 2.2 GHz.
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[Ben Dhia11]
Case study 1 – Filtering of EMI by IC PDN
On-chip sensor characterization Isolation between sensor and digital core under test power supplies
Good isolation up to 1 GHz
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• Example of acquisition of a sinusoidal signal• Frequency of the signal = 10 MHz, pk-to-pk amplitude = 3 V
• Sampling freq = 50 KHz, bin width = 37.5 mV, sample number = 2000.
( ) 1,1
12
<−
= xx
xpπ
Mean value
Std deviation
Meas. 1.99 V 1.03 V
Theory 2 V 1.06 V
Theoretical distribution
Case study 1 – Filtering of EMI by IC PDN
On-chip sensor characterization
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Identical results Divergence [Ben Dhia11]
Case study 1 – Filtering of EMI by IC PDN
EMI coupling characterization
Very weak
coupling∆Vdd ≈ 0.1 V @ Pforw = 10 W
Strong
coupling
∆Vdd ≈ 0.1 V @ Pforw = 1 mW
Comparison between external and internal measurements.
31
Case study 1 – Filtering of EMI by IC PDN
Circuit PDN modeling
The difference between measurement results observed
above 50 MHz can be explained by IC PDN filtering effect.
To validate this hypothesis, we extract an equivalent model
of the injection conducted disturbance on core power
supply.
Construction of the equivalent models of core PDN, PCB
PDN and DPI injection path, based on R, L, C elements.
Models available in
system\case_study\digital_core_pdn
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The on-chip capacitance of the digital core is estimated to 86 pF. The added on-chip decoupling capacitance is equal to 44 pF (component supplied). The pads add an equivalent capacitance of 2 pF between Vdd and Vss.
On-chip PDN interconnects add a serial resistance estimated to 1 Ω for Vdd and Vss. The circuit is mounted into a TQFP128 package (on pin for Vdd, 2 pins for Vss).
Case study 1 – Filtering of EMI by IC PDN
[QFP128MIXITY.geo]
Circuit PDN modeling
Extraction of the package model with IC-EMC (Tools/Advanced
Package Model).
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[model_core1_pck.sch]
Case study 1 – Filtering of EMI by IC PDN
Circuit PDN modeling
DEMO
Equivalent model tuned with S11 measurement made on Core_Vdd:
34
|Z11|
Freq
Arg (Z11)
Freq
Case study 1 – Filtering of EMI by IC PDN
IC model validation – comparison with measurements
[model_core1_pck.sch] vs. [core1alim.s1p]
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Integrated
circuit
SMA
connector
Conducted
interferences
2.5 V power
plane
1.5 µH choke
inductance100 nF
16 mm long microstrip line
W= 0.7 mm
h= 0.4 mm
Vddcore
VssCore
Case study 1 – Filtering of EMI by IC PDN
PCB PDN and DPI injection path modeling
Schematic of the test board :
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Model
validation
|Z11|
Freq
[model_core1_pcb_Cdec.sch]
Case study 1 – Filtering of EMI by IC PDN
PCB PDN and DPI injection path modeling
[PCB_injection_path.sch] vs. [S11_core1 _avec_Cdec.s1p]
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IC + PCB + test
environment model
Place port 1 on observation point, port 2
on conducted injection point
AC simulation – S parameter calculation
S to Z parameter conversion
Compute EMI coupling TF Hemi
( ) ( )222
212.4
ZZ
ZZfH
C
CEMI +
=
Case study 1 – Filtering of EMI by IC PDN
EMI coupling simulation flow
DEMO
Based on a small-signal analysis
Simulation of the EMI coupling transfer function into a passive PDN
38
• Coupling of the conducted disturbance on the package pin Core_Vdd.
Acceptable model up to 400 MHz
[Ben Dhia11]
Case study 1 – Filtering of EMI by IC PDN
IC model validation – comparison with measurements
[EMI_TF_core1_ext.sch]
39
• Coupling of the conducted disturbance on the internal Core_Vdd node.
Acceptable model up to 200 MHz
[Ben Dhia11]
Case study 1 – Filtering of EMI by IC PDN
IC model validation – comparison with measurements
[EMI_TF_core1_int.sch]
40
Identical results Divergence
Case study 1 – Filtering of EMI by IC PDN
EMI coupling simulation
The simulation confirms that above 50 MHz, the noise coupled inside
the circuit is different from the noise coupled outside.
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EMI
coupling
Phase
DetectorVCO +
Freq. Divider
/4
PLL input
(Fref = 24 MHz)
VDD PH
VSS PH
VDD VCO
VSS VCO
VDD DIV
VSS DIV
PLL output
θVCO
EMI-induced
jitter
PLL phase variations
7 MHz low
pass filter
• PLL developed in CMOS 0.25 µm• Three sub-blocks with separated power supplies• Conducted disturbances applied on the VCO power supply (Vdd VCO).
• Objective: prediction of EMI-induced voltage fluctuation on Vdd VCO.
Case study 2 – Complex PDN
Case study 2 description
42
• Three on-chip voltage sensors placed on the following nodes:
• VCO power supply Vdd VCO• Phase comparator power supply Vdd Ph• Frequency divider power supply Vdd div
• Characterization of the voltage fluctuation on Vdd VCO• Characterization of parasitic couplings between different power supply domains.
Case study 2 – Complex PDN
Case study 2 description
[Boyer11]
PCB ground
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Case study 2 – Complex PDN
Circuit PDN modeling
VDD VCO
VSS VCO
VDD PH
VSS PH
VDD DIV
VSS DIV
VDD I/O
VSS I/O
Power supply
domain PDN
Power supply
domain PDN
IC
Inter domain
coupling
Inter domain
coupling
Die-PCB
coupling
Die-PCB
coupling
Models available in system\case_study\pll_pdn.
Structure of the PDN
Case study 2 – Complex PDN
Circuit PDN modeling
[Boyer11]
Extraction of the PLL PDN
model by S parameter
measurements
Design of a specific test board
for 2 port measurements with
GS coplanar probes
Possibility to connect (or
disconnect) Vss package pins to
(or from) PCB ground plane
45
Case study 2 – Complex PDN
Circuit PDN modeling• Structure of the extracted PLL PDN model
[Boyer11]
[PDN_PLL_model.sch]
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Case study 2 – Complex PDN
Validation of the PDN model
|Z11|
Freq
[S2P_VCOVdd_PhVdd_gnd_0ohms.sch]
[s2p_VddVCO_VddPh_gnd0ohm.s2p]
≈ 7 pF
Port 1 on VddVCO, VssVCO is grounded
Extraction of the VCO on-chip capacitance
Case study 2 – Complex PDN
Validation of the PDN model
|Z11|
Freq
[S1P_VssVCO_gnd_0ohms.sch]
[s1p_VssVCO_gnd0ohms.s1p]
Package pin effect
Port 1 on VssVCO, all the other ground pins are grounded.
Resistive coupling + package inductance effect between ground pins
≈ 15 Ω
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Validation of the PDN model
|Z12|
Freq
[S2P_VssVCO_VssPh_gndOpen.sch]
[s2p_VssVCO_VssPh_gndOpen.s2p]
Case study 2 – Complex PDN
Port 1 on VssVCO, Port 2 on VssPh, all the other ground pins opened.
Capacitive coupling between the substrate and the PCB gnd plane.
≈ 30 pF
Case study 2 – Complex PDN
Validation of the PDN model
|S12|
Freq
[S2P_VddVCO_VddPh_gnd_0ohms.sch]
[s2p_VddVCO_VddPh_gnd0ohm.s1p]
Significant coupling between power supply domains
Port 1 on VddVCO, Port 2 on VddPh capacitive coupling between
different power supply domains.
50
November 11
Case study 2 – Complex PDN
EMI coupling characterization
[Boyer11]
• Comparison between external and internal measurements of the EMItransfer function on VddVCO.
• Experimentally, the forward power required to induce a voltage fluctuation with an amplitude = 0.25 V is measured (small signal conditions).
Identical results Divergence
Larger voltage fluctutation measured
inside the IC
∆Vdd ≈ 0.1 V @ Pforw = 0.1 mW
51
• Coupling of the conducted disturbance on the internal VddVCO node.
• Add PCB and DPI injection path to PLL PDN model.
IC model validation – comparison with measurements
Case study 2 – Complex PDN
[EMI_TF_VCO_Vdd.sch]
DEMO
52
• Coupling of the conducted disturbance on the internal VddVCO node.
• Add PCB and DPI injection path to PLL PDN model.
IC model validation – comparison with measurements
Case study 2 – Complex PDN
[Boyer11]Acceptable model up to 1 GHz
53
Analysis of EMI coupling with the model
Case study 2 – Complex PDN
RFI source
Zc (= 50 Ω)
1.5 µH Choke inductor
VCO equivalent impedance
100 nF decoupling capacitor
VddVCO
PCB Circuit
The RF disturbance source is connected to 3 parallel loads.
Equivalent model of conducted injection on VddVCO:
54
Analysis of EMI coupling with the model
Case study 2 – Complex PDN
The lowest impedance(s) dominate(s).
55
Is such a complex model necessary ?
Case study 2 – Complex PDN
[EMI_TF_VCO_Vdd_PDN_simple.sch]
Can we simplify the circuit model ?
Remove the substrate coupling, capacitive coupling between power
supply domains and die-board coupling.
56
Is such a complex model necessary ?
Case study 2 – Complex PDN
Large difference of EMI coupling prediction
57
Case study 2 – Complex PDN
[Boyer11]0
0,2
0,4
0,6
0,8
1
0,E+00 2,E+08 4,E+08 6,E+08 8,E+08 1,E+09
Frequency (Hz)
Tra
nsfe
r fun
ctio
n
VddPh/VddVCO
VddDiv/VddVCO
Is such a complex model necessary ? Transfer functions between VddPh/VddVCO and VddDiv/VddVCO
Non negligible noise injection on the power supplies of phase detector
and frequency divider.
0
0,2
0,4
0,6
0,8
0,E+00 2,E+08 4,E+08 6,E+08 8,E+08 1,E+09
Frequency (Hz)
Tra
nsfe
r fun
ctio
n V
ddD
iv/V
ddV
CO
Measurement
Simulation
Case study 2 – Complex PDN
Is such a complex model necessary ?
[Boyer11]
Our model overestimates the internal coupling between separated
power supply domains.
Insufficient model for couplings at board level.
58
• Regulator L4949: used for supplying 5V
to a microcontroller
• Goal: build an immunity model of the
L4949 in direct-power-injection (DPI)
• Available information:
Datasheet of the regulator
Z(f) measurement available
DPI using a +/- 200 mV shift
criterion in the Vout voltage
test Boardtest Board
Case study 3 – Non linear PDN
Case study presentation
59
1
2
3
4
8
7
6
5
L4949
VCC
GND
Si
Vz
Ct
VOUT
So
Reset
L=47µH
C=1nF
R=220ΩC=10µF
Input RF
VDC=12v
Output : 5v
Ferrites
Injection & protection pathLoad
Functional diagram of regulator
Case study 3 – Non linear PDN
Discrete component models
Ferrite Z(f) - Zin_FerriteBLM18HK102SN1.s50
DPI capacitance Z(f) - Zin_DPI_1nF.s
Inductance Z(f) - Zin_L47u.s50
Models available in system\case_study\L4949
60
Case study 3 – Non linear PDN
Discrete component models
61
[Zin_DPI_1nF.sch]
[Zin_Ferrite.sch]
[Zin_L47u.sch]
DEMO
Discrete devices
L4949 PDN
Loads
Case study 3 – Non linear PDN
Impedance validation
62
[Zf_Vcc_L4949.sch]
Z(f) is dependent
on the supply
voltage at low freq.
Used in our model:
nominal VCC 12 V
Bias dependant capacitance variation
Bias independant L,C contributions
Non linear junction capacitance
Linear PCB/package/die impedance
Case study 3 – Non linear PDN
Impedance validation
63
DEMO
[Wu11]
Case study 4 – Non linear PDN
Case study presentation
Digital core
Vss_Core
data
clock
out
Output
buffer
Out
Vdd_Core (2.5 V)
Vdd_IO (5V)
Vss_IO
PCB groundDie-PCB
coupling
Die-PCB
coupling
Vss_Core
Vdd_Core Vdd_IO
Vss_IO
Power supply
domain PDN
Power supply
domain PDNInter domain
coupling
Inter domain
couplingPDN
modeling
65
Case study 4 – Non linear PDN
I(V) characterization
I(V) characterization between the different pins of the PDN.
+ : Vdd Core
- : Vss Core
+ : Vdd IO
- : Vss IO
Protection diodes between power supply and ground against
invert biasing.
-0.7 V -0.7 V
≈
=≈ =
66
Case study 4 – Non linear PDN
I(V) characterization
+ : Vdd Core
- : Vdd IO
0.9 V
+ : Vss Core
- : Vss IO
Protection diodes between different power supply domains.
≈
=≈
=
≈
+/- 0.7 V
67
Vss_Core
Vdd_Core Vdd_IO
Vss_IO
Case study 4 – Non linear PDN
PDN with protection elements
Full PDN with protection elements.
Activation of protection diodes for large disturbances across
power supplies and grounds.
68
Summary
Circuit PDN acts as a (2 nd order) filter on external
conducted disturbances.
The EMI coupling efficiency is related to PCB and I C
PDN impedance profile.
Accurate modeling of chip – package resonances,
interblock couplings, substrate coupling, die-PCB
capacitance.
The voltage dependence of the PDN should be taken
into account if required.
Modeling of Circuit Behavior to EMI
70
Macromodelapproach
Netlist approach
Accurate, but confidential data, high complexity, long simulation time
Non confidential data, possible extraction by measurements, low complexity, small simulation time,
but less accurate
Modeling of IC behaviour to EMI
Modeling approach The response of a circuit to a large voltage fluctuation is usually non
linear Modeling and simulation difficulties.
Two types of approaches
Case study 1 – Linear voltage regulator
Everything simple
Dpi 1 nF ideal
L 47uH ideal
Ferrite 220 ohm
Load ideal
Regulator
88 ohm
27 pF capa
DPI model “A”
[L4949_modelA.sch]
71
Aggressed IC
Model (ICEM)
Package
and IO model (IBIS)
RFI and coupling
path model (Z(f))
Set RFI frequenciesIC-EMC
Time domain simulationsWinSPICE
Criterion analysis
Extract forward power
IC-EMC
DPI measurement
Case study 1 – Linear voltage regulator
DEMO
Susceptibility simulation flow
72
Case study 1 – Linear voltage regulator
No susceptibility
Perfect
decoupling
destroys RFI at
Vout
Purely linear
model, no
rectification, no
offset
Model A
DPI measurement
DPI model “A”
73
Case study 1 – Linear voltage regulator
DEMO
DPI model “B”
Less ideal load
Pcb track
Non ideal 10uF
[L4949_modelB.sch]
74
Less ideal
load
makes a
big
difference
starting 30
MHz
Low
frequency
level still
high
DPI measurement
Model B
Case study 1 – Linear voltage regulator
DPI model “B”
75
“B-element”
LPF
-7V
^2
k
DC offset at low frequency
12 V
5 V + offset
Case study 1 – Linear voltage regulator
DPI model “C”
[L4949_modelC.sch]
76
[Wu11]
Low-frequency
offset reproduced
using a macro-
model
“B-element” is a
powerful
mathematical way to
describe non-
linearities
DPI measurement
Model C
Case study 1 – Linear voltage regulator
DPI model “C”
77
78
RF disturbance
Pforw Prefl
Directional coupler
SMA connector
6.8 nF DPI capacitor Test board
Injection path
External LEDs
To the input buffer
DPI on a 16-bit
microcontroller from
Freescale, through a
6.8 nF capacitor
Criteria: Input state
modification
Case study 2 – Digital Input
Test set-up
79
Case study 2 – Digital Input
Susceptibility criterion
Coupling path
Forward Power
Input buffer
Supply network
RF source and Amplifier Vdd Vss
Led Coupler Package
model
Equipment model
Board model IC model
Modeling approach
Model available in case_study\s12x
80
Case study 2 – Digital Input
Coupling path model
Total capacitance
20 pF
Total inductance
12 nH
Total resistance 2 Ω
LC resonance
Lsma, Csma
R,LC based model
Non-ideal capa
[s12x_dpi_path.sch]
[s12x_dpi_path.z]
81
Case study 2 – Digital Input
Exploitation of IBIS
3D reconstruction
R,LC of package
recomputed
I/V curves for
diodes, switches
Positioning of
supply and IO leads
in space
DEMO
[S12X_v2.ibs]
82
Case study 2 – Digital Input
Exploitation of IBIS
R,L,C model of the
package from IC-
EMC & IBIS
C_comp from IBIS
data
I/V of diodes tuned
with IBIS
information
[s12x_io_pt3_dc.sch]
83
Case study 2 – Digital Input
DPI simulation
A simple IO model
from IBIS gives a
first-order
estimation of DPI
A more detailed IC
model (PDN, non-
linearity ) is
required for
improved tuning
[s12x_dpi_pt3.sch]
[s12x_dpi_pt3.tab]
84
Case study 2 – Digital Input
DPI simulation External Supply
Input buffer
PDN
Ccomp
Package
Input tracks
DPI capacitance
Substrate coupling
External Supply
Input buffer
PDN
Ccomp
Package
Input tracks
DPI capacitance
Substrate coupling
A more detailed IC model
(PDN, non-linearity ) with
substrate coupling and the
output buffer model enables
a fine tuning
[Boyer07]
DecouplingNetwork
2.5 V
For
war
d po
wer
DIRECTIONAL COUPLER
Ref
lect
ed p
ower
10 W POWER AMPLIFIER
POWER METER
SIGNAL SYNTHESIZER 10 – 1000 MHz
Conducted EMI
VDDVCO On-chip Sensor
SIGNAL GENERATOR
24 MHz
PLL out
ACQUISITION CARD
Internal noise measurement
Functional failure
detection
PLLPLLPLL in
Failure criterion:
+/-2 ns output period variation
Case study 3 – Phase-Locked Loop
Test set-up description
85
Phase
DetectorVCO
Freq.
Divider
Fref = 24 MHz
VDD PH
VSS PH
VDD VCO
VSS VCO
VDD DIV
VSS DIV
PLL output
EMI
coupling
+
θVCOEMI-induced
jitterθin
PLL frequency
variations
θout+∆θout
Case study 3 – Phase-Locked Loop
Failure mechanism
86
87
87 November 11
VCO (delay cell controlled ring oscillator)
Frequency divider
Phase comparator and 1st order filter
Case study 3 – Phase-Locked Loop
PLL SPICE Model
[Boyer11b]
Case study 3 – Phase-Locked Loop
PLL SPICE Model – Simulation of jitter
Without RFI
With RFI
EMI induced jitter
+/- 2 ns
42 ns
Time (ns)
PLL period (ns)
RFI
T0 +/- 2 ns
Simulation of the PLL failure with IC-EMC
Failures !
[EMC Signal Analysis]
DEMO
Simulation of the susceptibility criterion:[PLL_EMI_VddVCO.sch]
88
( )( ) ( )22
0
2
2.2
.
2
1
EMI
EMIVCOEMI
F
VK
FF
ππσ ϕ =VCO phase Jitter:
( ) ( ) ( ) 2
022 2exp1. TFjFF EMIEMIEMIT πσσ ϕ −−=VCO period Jitter:
PLL period Jitter: PLLVCOTPLLT G×= σσ
Case study 3 – Phase-Locked Loop
Failure mechanism – analytical model
Only the VCO is disturbed, by a sinusoidal
noise.
The VCO acts as a frequency modulator
dependent on power supply fluctuations.
The VCO instantaneous frequency and power
supply voltage are related by a constant
parameter called pushing coefficient Kvco.VddVCO
FVCO KVCO
F0
VDD0
89
9090 November 11
P(f) V(f)
D(f)
+
θVCO
Jitter induitθin
θout
Case study 3 – Phase-Locked Loop
Failure mechanism – analytical model Block diagram of the PLL
PLL period Jitter:
PLLVCOTPLLT G×= σσ
( ) ( )( ) ( ) ( )fDfVfP
fDfG
VCO
outPLL +
==1θ
θ
Comparison between
SPICE and analytical
model
[Boyer11]
Measurement Simulation SPICE
Case study 3 – Phase-Locked Loop
Measurement vs. simulation of PLL sensitivity to EM I
On-chip measurement with the sensor to measure the sensitivity of
PLL to voltage fluctuation on VddVCO.
Simulation reproduces the failures of the PLL.
Noise level to induce unlocking is overestimated in
simulation.91
92
PLL transistor netlist
SPICE transient
simulation
Freq. EMIVDD VCO
fluctuations
10 MHz 0.1 V
20 MHz 0.15 V
… …
Sensitivity table
Case study 3 – Phase-Locked Loop
Simulation of PLL susceptibility
Construction of the Internal Behavior Block:
The sensitivity of the PLL to VddVCO fluctuations is first simulated in time
domain and included.
And then include in a “sensitivity table”.
DEMO
Case study 3 – Phase-Locked Loop
Simulation of PLL susceptibility
Circuit PDN
PCB model
DPI test benchExtraction of VddVCO
noise amplitude
Failure detection:For each EMI frequency,
Failure if VddVCO noise > Value in sensitivity table.
[simu_immunity_PLL_List.sch]
93
Case study 3 – Phase-Locked Loop
Simulation of PLL susceptibility
[List_freq_susc_PLL_meas_2ns_v3.TXT ] [Meas_immunity_PLL_List.tab]
94
Practical training about IC susceptibility
96
EMC Training
May 2008
2-DAYS TRAINING IN EMC OF ICs
Ex. 1. FFT of typical signals Ex. 2. Transient current estimation Ex. 3. Interconnect parasitics Ex. 4. di/dt noise Ex. 5. intrinsic decoupling Ex. 6. added on-chip decoupling Ex. 7. PDN modelling
Ex. 8. Radiated emission modelling Ex. 9. Estimation of susceptibility level Ex. 10. Susceptibility of analog input Ex. 11. Susceptibility of output buffer Ex. 12. Susceptibility of a micro-controller
Quality labeled course
97
EMC Training
EX 7 - PDN MODELLING C51 Z(f): find an R,L,C model Tune to measurement file
Emission >
C51 >
c51_supply_impedance.s50
98
– Estimate the forward power to induce 1 V across the load over
the frequency range 10 MHz – 1 GHz.
– A RF generator produces a conducted disturbance whi ch is
injected on a 200 Ω load, though a directional coupler.
EX 9 - ESTIMATION OF SUSCEPTIBILITY LEVEL
EMC Training
99
– Launch Susceptibility tool
– Configure the RF disturbance and launch SPICE simulation
– Configure the voltage criterion and extract susceptibility threshold
– Display the susceptibility threshold
EMC Training
EX 9 - ESTIMATION OF SUSCEPTIBILITY LEVEL
100
– A RF disturbance is conducted to
an analog input.
– Equivalent model: serial 1 K Ω
resistor and a 22 pF capacitor.
– Susceptibility criterion : input noise
< 100 mV from 10 MHz to 1 GHz.
EX 10 - SUSCEPTIBILITY OF ANALOG INPUT
EMC Training
101
– The following output is loaded
by a 200 Ω load and a 0.5 nF
capacitance.
– The susceptibility of the buffer
is tested using DPI standard.
– Harmonic disturbances are
injected on power supply
RFI
Susceptibility criterion ?
EX 11 - SUSCEPTIBILITY OF OUTPUT BUFFER
EMC Training
102
– Injection on the Vdd pin
– Add a 100 MHz RFI sinus signal with 2 V amplitude.
Describe the failure
EMC Training
EX 11 - SUSCEPTIBILITY OF OUTPUT BUFFER
103
– Consider the following digital circuit:
CMOS 65nm technology
32 bits CPU, 250 Kgates, surface = 3 mm²
The core is supplied by 4 dedicated
power supply pairs
The IC is mounted in a 324-pin BGA
package
The circuit is soldered on a 150×100 mm
FR4 printed circuit board, with 2 internal
power supply and ground planes.
EMC Training
EX 12 - SUSCEPTIBILITY OF OUTPUT BUFFER
104
IEC62132-3 Direct Power Injection
(DPI) standard, 1 MHz – 1 GHz, power
limit 25 dBm.
Work to do
Build an equivalent model of the core.
(Suggestion: use Tools/ICEM model
expert)
Build the PCB and the injection path
models.
Predict by simulation the
susceptibility threshold of the
component.
EX 12 - SUSCEPTIBILITY OF OUTPUT BUFFER
EMC Training
105
EMC Training
A TWO-DAYS
INTRODUCTORY
COURSE IN EMC
OF ICS
Eurotraining Quality
Course
9-10 Feb 2012
Toulouse, France
Morning : lectures
Afternoon: practical
session using IC-EMC
and WinSpice
106
References[ICEMC]: E. Sicard, A. Boyer "IC-EMC User's manual version 2.5", INSA editor, October 2011, ISBN 978-2-87649-056-7, www.ic-emc.org
[Deobarro09]: M. Deobarro, B. Vrignon, S. Ben Dhia, A. Boyer, “Use of on-chip sampling sensor to evaluate conducted RF disturbances propagated insid e an integrated circuit”, EMC Compo 2009, Toulouse, November 17 – 19 2009
[BenDhia11]: S. Ben Dhia, A. Boyer, B. Vrignon, M. Deobarro, T. V. Dinh, “On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations”, to appear in IEEE Trans. On Instrumentation and Measurements
[Boyer11]: A. Boyer, B. Li, S. Ben Dhia, C. Lemoine , B. Vrignon, “Development of an Immunity Model of a Phase-Locked Loop”, 2011 Asia-Pacific In ternational Symposium on Electromagnetic Compatibility, May 16 – 19, 2011, Jeju Island, Korea
[Boyer11b]: A. Boyer, S. Ben Dhia, C. Lemoine, B. V rignon, “An On-Chip Sensor for Time Domain Characterization of Electromagnetic Interferences”, 8th International Workshop on electromagnetic Compatibility of Integrated Circuits, November 6 – 9 , 2011, Dubrovnik, Croatia
[Wu11]: Wu Jian-fei, E. Sicard, A. Cissé Ndoye, F. L afon, Li Jian-cheng, Shen Rong-jun, "Investigation on DPI Effects in a Low Dropout Volt age Regulator", EMC Compo 2011, Dubrovnick, Croatia, November 2011
[Boyer07]: A. Boyer, S. Ben Dhia, E. Sicard "Modelli ng of a Direct Power Injection Aggression on a 16 bit Microcontroller Input Buffer", EMC Compo 07 Torino, Nov 2007, Italy, pp. 35 – 39
[Sicard11]: E. Sicard, A. Boyer, “Enhancing Enginee rs Skills in EMC of Integrated Circuits”, 8 th
International Workshop on electromagnetic Compatibi lity of Integrated Circuits, November 6 – 9, 2011, Dubrovnik, Croatia