1

iBob TutorialiBob Tutorial

Dejan Markovic, Zhengya Zhang{dejan, zhengya}@eecs.berkeley.edu

2

The iBobThe iBob Xilinx (Virtex2p) emulation board

5V DC

IO

3

Step 1: SysGenStep 1: SysGen Setup

• Part as specified in the screen shot• Synthesis tool• FPGA clock (up to 200MHz)

XSG Output:*.prj

4

Step 2: Synplify ProStep 2: Synplify Pro Create shortcut on your local machine

• Open existing project: SYSGEN/*.prj• Run

Synplify Output:*.edf

5

Step 3: Project NavigatorStep 3: Project Navigator Programs / XilinxISE / Project Navigator

• Open the *.npl file from <design>/SYSGEN

6

Step 4: Pin AssignmentStep 4: Pin Assignment Uncheck “read-only” on the *.npl file User constraints / Create Timing Constraints

User constraints / assign package pins• a) Edit user constraint (use package I/O look-up table)

(note: use “gpio” pins information )• b) it is easier to edit this file in Wordpad and using pinout table from the next slide)

\\hitz\designs\BEE\tutorials\*.xls (pin assignment)

7

iBob Pinout MapiBob Pinout Map

J6

J20 (19)K20C24D24D23D22 (14)G21H21D25E25E22 (9)F22J21K21C26D26 (4)G22H22J23K23 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio0

J7

F18(19)G18K18L18D19E19 (14)F19G19H19J19D20 (9)D21F20G20K19L19 (4)C22C21E21F21 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio1

J9

K12 (19)J12H13G13D9C9 (14)K14J14F13E13E10 (9)D10H14G14D13D12 (4)D11C11K15J15 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio3

J8

F14 (19)E14C14C13L16K16 (14)G15F15D14D15J16 (9)H16G16F16E16D16 (4)L17K17G17F17 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio2(top) (top) (top) (top)

8

Pin AssignmentPin Assignment *.ucf file

iBob has diff Clk,and this needs tobe defined beforeclk_out pin

defined in *.ncffile which shouldbe empty after youcopy it here

9

Edit <des>_clk_wrapper.vhdEdit <des>_clk_wrapper.vhd Specify Clk (diff -> single ended)

entity sq_clk_wrapper is port ( ce: in std_logic := '1'; clk_n: in std_logic; clk_p: in std_logic; clk_out: out std_logic; as: out std_logic_vector(13 downto 0); zs: out std_logic_vector(15 downto 0) );end sq_clk_wrapper;

diff single ended Clk,

<next page>

architecture structural of sq_clk_wrapper is component IBUFGDS port (O : out STD_ULOGIC; I : in STD_ULOGIC; IB : in STD_ULOGIC); end component; component sq

10

Edit <des>_clk_wrapper.vhd (Cont.)Edit <des>_clk_wrapper.vhd (Cont.) Assign port map

port map

signal clk: std_logic;

begin

CLOCK_BUFFER : IBUFGDSport map (O => clk,I => clk_p,IB => clk_n);

clk_out <= clk; clk_sysgen <= clk; as <= as_x_0; zs <= zs_x_0;…

11

Step 5: Implement DesignStep 5: Implement Design Right click on “Implement Design” / Run

12

Step 6: Generate *.bit FileStep 6: Generate *.bit File Copy bit file to a local machine

Output:*.bit

13

Step 7: Program FPGAStep 7: Program FPGA Go to the lab and program *.bit file into an FPGA

• Run Xilinx ISE / IMPACT from local machine

14

iBob pinout tableiBob pinout table

- Tutorial -

15

iBob Pinout MapiBob Pinout Map

J6

J20 (19)K20C24D24D23D22 (14)G21H21D25E25E22 (9)F22J21K21C26D26 (4)G22H22J23K23 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio0

J7

F18(19)G18K18L18D19E19 (14)F19G19H19J19D20 (9)D21F20G20K19L19 (4)C22C21E21F21 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio1

J9

K12 (19)J12H13G13D9C9 (14)K14J14F13E13E10 (9)D10H14G14D13D12 (4)D11C11K15J15 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio3

J8

F14 (19)E14C14C13L16K16 (14)G15F15D14D15J16 (9)H16G16F16E16D16 (4)L17K17G17F17 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio2(top) (top) (top) (top)

16

SQ ExperimentSQ Experiment

J6

J20 (19)K20C24D24D23D22G21H21D25E25E22F22J21K21C26D26G22H22J23K23 (0)

gndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgndgnd

gpio0

NET clk_out LOC = K12;

NET "zs(15)" LOC="K23";NET "zs(14)" LOC="J23";NET "zs(13)" LOC="H22";NET "zs(12)" LOC="G22";NET "zs(11)" LOC="D26";NET "zs(10)" LOC="C26";NET "zs(9)" LOC="K21";NET "zs(8)" LOC="J21";NET "zs(7)" LOC="E22";NET "zs(6)" LOC="E25";NET "zs(5)" LOC="D25";NET "zs(4)" LOC="H21";NET "zs(3)" LOC="G21";NET "zs(2)" LOC="D22";NET "zs(1)" LOC="D23";NET "zs(0)" LOC="D24";NET "as(13)" LOC="C24";NET "as(12)" LOC="K20";NET "as(11)" LOC="J20";NET "as(10)" LOC="F21";NET "as(9)" LOC="E21";NET "as(8)" LOC="C21";NET "as(7)" LOC="C22";NET "as(6)" LOC="L19";NET "as(5)" LOC="K19";NET "as(4)" LOC="G20";NET "as(3)" LOC="F20";NET "as(2)" LOC="D21";NET "as(1)" LOC="D20";NET "as(0)" LOC="J19";

exclude

Z<15:0>

17

Logic AnalyzerLogic Analyzer

- Tutorial -

18

Main Window Main Window Select / Setup & Trig Select / Setup & Trig

19

Setup and Trigger Window / SamplingSetup and Trigger Window / Sampling

20

Setup and Trigger Window / TriggerSetup and Trigger Window / Trigger Edit switching threshold

21

Select Select Listing Listing File/Print to file/ ftp to local disk

22

Sampling Problem: Eye FinderSampling Problem: Eye Finder Eye opening scattered around Clk edge

23

ResultsResults Sampling inconsistency

0.5 1 1.5 2 2.5 3

x 104

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

24

ResultsResults Look Familiar?

0.5 1 1.5 2 2.5 3

x 104

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

25

ResultsResults

0.5 1 1.5 2 2.5 3

x 104

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

26

ResultsResults

0.5 1 1.5 2 2.5 3

x 104

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

0.5 1 1.5 2 2.5 3

x 104

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

27

Well Known ResultWell Known Result Experimentally justified logo…

0.5 1 1.5 2 2.5 3

x 104

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

today

S QR T1/

28

ResultsResults “The CITY” logo

0.5 1 1.5 2 2.5 3

x 104

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5